DETAILED ACTION
This action is responsive to the following communications: Completion of U.S. National Stage Entry requirements on February 1, 2024. All references to this application refer to the U.S. Patent Application Publication No. 2024/0428048 A1.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-24 are pending in this case. Claims 1, 9, and 17 are the independent claims. Claims 1-24 are rejected.
Priority
The present application is a U.S. National Stage Entry of PCT/CN2021/132707, filed on November 24, 2021.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7, 14, 15, 22, and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Each of dependent claims 6, 14, and 22 recite in pertinent part “based on the compare, move data for one or more of the stored chunks to one or more unused memory blocks of the plurality of memory blocks.” There is a lack of antecedent basis for “the stored chunks” in each of these claims.
Accordingly, dependent claims 6, 14, and 22 are rendered indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
To overcome these rejections, the Examiner recommends either:
Changing the dependency of the claims (which currently depend from the independent claim which lacks the necessary antecedent basis). Claim 6 could depend from claims 4 or 5, claim 14 could depend from claims 12 or 13, and claim 22 could depend from claims 20 or 21.
Add a new limitation to each of claims 6, 14, and 22 that provides the necessary antecedent basis (e.g., “divide each layer of the neural network into a plurality of chunks and store the chunks in one of the plurality of memory blocks based on the randomized memory storage pattern”
For the purposes of examination, the claims are interpreted as modifying the dependency to depend on claims 4, 12, and 20, respectively.
Dependent claims 7, 15, and 23 are rejected solely due to their dependence from a rejected parent claim.
To expedite a complete examination of the instant application, the claims rejected above under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, are further rejected as set forth below in anticipation of amendments to these claims to correct the failure.
Examiner’s Note
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Non-Patent Literature reference entitled "Seeds of SEED: Efficient Access Pattern Obfuscation for Untrusted Hybrid Memory System," by Che et al., published for the International Symposium on Secure and Private Execution Environment Design (SEED), September 20-21, 2021 (hereinafter Che), in view of U.S. Patent Application Publication No. 2014/0007250 A1, filed by Stefanov et al., on June 17, 2013, and published on January 2, 2014 (hereinafter Stefanov).
With respect to independent claim 1, Che discloses a computing system comprising:
A memory to store a neural network; and a processor to execute instructions that cause the computing system to: Che discloses a memory to store a neural network (NN) and a processor to execute instructions on a computing system (see Che, page 63 [introduction, describing the use of a computing system hosting a NN including a hybrid memory structure]).
Generate a neural network memory structure having a plurality of memory blocks in the memory; Che discloses a NN memory structure with a plurality of memory blocks (see Che, page 64 [section C, describing the non-volatile memory and hybrid memory architecture that stores the NN]).
Scatter the neural network among the plurality of memory blocks based on a randomized memory storage pattern; Che discloses initially storing the NN using a random set of memory addresses within the Obfuscation scheme for Hybrid memory system with NVM (OH-NVM) (see Che, pages 65-67 [section IV, A-C, describing the overview and initial random memory assignments for the NN data structure]).
Che fails to expressly disclose reshuffle the neural network among the plurality of memory blocks based on a neural network memory access pattern.
However, Stefanov teaches a memory shuffling technique for concealing memory access patterns from malicious users/attacks by reshuffling data stored in memory randomly based on hiding the true memory access pattern within a false/generic memory access pattern (see Stefanov, paragraphs 0060-0064 [describing how the memory is divided into blocks of predetermined sizes/partitions, and those partitions are shuffled at predetermined times (such as randomly, upon trigger conditions being met, at predetermined frequencies, etc.]).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Che and Stefanov before him before the effective filing date of the claimed invention, to modify the system of Che to incorporate reshuffling data and structures in memory as taught by Stefanov. One would have been motivated to make such a combination because this enhances security of user data, as taught by Stefanov (see Stefanov, paragraph 0011 [“Accordingly, a need exists for a practical method and apparatus for implementing a form of Oblivious RAM for concealing access patterns to electronic data storage (e.g., disk and memory) for enhancing security.”]).
With respect to dependent claim 2, Che, as modified by Stefanov, teaches the computing system of claim 1, as described above.
Stefanov further teaches the system
Wherein the plurality of memory blocks are organized into a plurality of groups of memory blocks, Stefanov further teaches the plurality of blocks being organized into groups of memory blocks of predetermined sizes (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
Wherein, for each group, the memory blocks in the respective group have a block size selected from a plurality of block sizes; Stefanov further teaches the block sizes are selected from a plurality of block sizes (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
With respect to dependent claim 3, Che, as modified by Stefanov, teaches the computing system of claim 1, as described above.
Stefanov further teaches the system
Wherein the plurality of memory blocks are organized into a plurality of groups of memory blocks, Stefanov further teaches the plurality of blocks being organized into groups of memory blocks of predetermined sizes (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
Wherein the plurality of groups of memory blocks are divided between stack space and heap space; Stefanov further teaches that the blocks are arranged between dynamic memory slices (heap) and long term memory (stacks) (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
With respect to dependent claim 4, Che, as modified by Stefanov, teaches the computing system of claim 1, as described above.
Che and Stefanov further teach the system wherein to scatter the neural network model comprises to:
Divide each layer of the neural network into a plurality of chunks; Che further teaches dividing each NN layer into a plurality of chunks (see Che, pages 65-67, described supra, claim 1).
For each layer, select, for each chunk of the plurality of chunks, one of the plurality of memory blocks based on the randomized memory storage pattern; Che further teaches selecting a memory block for each chunk (see Che, pages 65-67, described supra, claim 1). Additionally or alternatively, Stefanov further teaches assigning chunks of data randomly into memory blocks (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
Store each chunk in the respective selected memory block; Stefanov further teaches storing each chunk in the selected memory block (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
With respect to dependent claim 5, Che, as modified by Stefanov, teaches the computing system of claim 4, as described above.
Stefanov further teaches the system wherein the instructions, when executed, further cause the computing system to, for each chunk, encrypt data for the chunk stored in the respective selected memory block.
Stefanov further teaches using encryption for storing the chunks in memory blocks (see Stefanov, paragraphs 0012 [includes using encryption for protecting the data], 0045 [O-RAM uses various forms of encryption to bolster its security features], and 0088 [describing the use of cryptographic keys]).
With respect to dependent claim 6, Che, as modified by Stefanov, teaches the computing system of claim [4], as described above.
Che and Stefanov further teach the system wherein to reshuffle the neural network model comprises to:
Measure memory accesses for the neural network over a time period; Che measures memory accesses for intrusions (see Che, pages 67-68 [section IV. E-F and VI A-B describing the analysis of intrusions and memory accesses made by friend and foe].
Determine the neural network memory access pattern based on the measured memory accesses for the neural network; Che further teaches determining the memory access pattern based on the analysis (see Che, pages 67-68, described supra).
Compare the determined neural network memory access pattern and another memory access pattern; Stefanov further teaches comparing memory access patterns of applications and data (see Stefanov, paragraphs 0066-0071 [describing the problem definition of ascertaining intrusions/attacks vs true access attempts]).
Based on the compare, move data for one or more of the stored chunks to one or more unused memory blocks of the plurality of memory blocks; Stefanov further teaches moving data (e.g., shuffling) based on the analysis (see Stefanov, paragraphs 0060-0064, described supra, claim 1).
With respect to dependent claim 7, Che, as modified by Stefanov, teaches the computing system of claim 6, as described above.
Stefanov further teaches the system wherein the instructions, when executed, further cause the computing system to repeat the reshuffling of the neural network.
Stefanov further teaches repeating the reshuffling (see Stefanov, paragraph 0408 [the client repeatedly sorts and shuffles data during data accesses]).
With respect to dependent claim 8, Che, as modified by Stefanov, teaches the computing system of claim 1, as described above.
Stefanov further teaches the system wherein to reshuffle the neural network model further comprises to insert one or more camouflage memory accesses based on the determined neural network memory access pattern.
Stefanov further teaches using dummy reads to obscure access patterns (see Stefanov, paragraphs 0100-0123 [describing the use of dummy reads and access to hide the true patterns]).
With respect to independent claim 9, and its respective dependent claims 10-16, recite at least one computer readable storage medium comprising a set of instructions which, when executed by a computing system, cause the computing system to perform as the system of independent claim 1, and its respective dependent claims 2-8. Accordingly, independent claim 9, and its respective dependent claims 10-16, are rejected under the same rationales used to reject independent claim 1, and its respective dependent claims 2-8, which are incorporated herein.
With respect to independent claim 17, and its respective dependent claims 18-24, recite a method to perform as the system of independent claim 1, and its respective dependent claims 2-8. Accordingly, independent claim 17, and its respective dependent claims 18-24, are rejected under the same rationales used to reject independent claim 1, and its respective dependent claims 2-8, which are incorporated herein.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure. See PTO-892.
It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to ERIC J. BYCER whose telephone number is (571) 270-3741. The Examiner can normally be reached Monday - Thursday 9am-6pm, and alternate Fridays 9am-5pm.
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, Applicants are encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, MATT ELL can be reached on (571) 270-3264. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC J. BYCER/
Primary Examiner
Art Unit 2141
Prosecution Insights