DETAILED ACTION
Claims 1-19 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-11, and 14-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai (US PG Pub No. 2017/0206177 A1).
Tsai was disclosed in IDS dated 01/04/2024
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Tsai teaches a first physical processor comprising:
decoder circuitry ([0028]: Instruction unit 320 may include any circuitry, logic, structures, and/or other hardware, such as an instruction decoder) to decode a single instruction, the single instruction to include a field for an opcode ( [0028]: Any instruction format may be used within the scope of the present invention; for example, an instruction may include an opcode and one or more operands, where the opcode may be decoded into one or more micro-instructions or micro-operations for execution by execution unit 330); and
execution processing resources to execute the decoded single instruction according to the opcode ([0028]: Instruction unit 320 may include any circuitry, logic, structures, and/or other hardware, such as an instruction decoder, to fetch, receive, decode, interpret, schedule, and/or handle instructions (including inter-VM-IPI instruction 322, described below) to be executed by processor 300. Any instruction format may be used within the scope of the present invention; for example, an instruction may include an opcode and one or more operands, where the opcode may be decoded into one or more micro- instructions or micro-operations for execution by execution unit 330)
to cause a host to guest (H2G) notification from a virtual device ([0036]) running in a host machine ([0033]) on the first physical processor ([0062]: a sending VM may send a notification/interrupt to a target VM without a VM exit and without invoking a VMM the notify-processor for the target processor in the target VM may, in response to a notify event, send an IPI by writing to the Interrupt Command Register of the corresponding vAPIC page (e.g., vAPIC page 23) with a vector corresponding to an inter-VM-IPI. If the target VM is active, the notification/interrupt may be delivered directly to the target VM and without invoking a VMM) to a virtual device driver running on a virtual processor in a guest machine on a second physical processor ([0051]: the present invention provide for an inter-VM-IPI to be sent from guest software being executed by a first virtual processor in any VM (e.g., the first VM) to a second virtual processor in any other VM (e.g., the second VM) regardless of whether the first virtual processor and the second virtual processor are abstracted from the same physical processor or physical processor core or from two physical processors or physical processor cores in/on the same or different integrated circuits, die, chips, substrates, or packages).
Regarding claim 2, Tsai teaches wherein the execution processing resources to send a posted interrupt (PI) inter-processor posted interrupt (IPI) as the H2G notification to the second physical processor running the virtual device driver on the virtual processor in the guest machine ([0062]: a sending VM may send a notification/interrupt to a target VM without a VM exit and without invoking a VMM the notify-processor for the target processor in the target VM may, in response to a notify event, send an IPI by writing to the Interrupt Command Register of the corresponding vAPIC page (e.g., vAPIC page 23) with a vector corresponding to an inter-VM-IPI; [0051]: the present invention provide for an inter-VM-IPI to be sent from guest software being executed by a first virtual processor in any VM (e.g., the first VM) to a second virtual processor in any other VM (e.g., the second VM) regardless of whether the first virtual processor and the second virtual processor are abstracted from the same physical processor or physical processor core or from two physical processors or physical processor cores in/on the same or different integrated circuits, die, chips, substrates, or packages).
Regarding claim 3, Tsai teaches wherein the virtual device is a host user space thread on the first physical processor ([0036]).
Regarding claim 4, Tsai teaches wherein the single instruction comprises a send user inter-processor interrupt instruction and the virtual device running in the host machine executes the SENDUIPI instruction on the first physical processor ([0016]: Communication between VMs may involve a first VM sending a notification or interrupt to a second VM (any such notification or interrupt may be referred to as an inter-VM interrupt, inter-VM inter-processor interrupt, or inter-VM-IPI). The use of embodiments of the present invention to increase the efficiency of inter-VM interrupts, by eliminating VM exits, may be desired. Embodiments of the present invention may be practiced using a processor having an instruction set architecture (ISA) including instructions to support virtualization, which may be part of a set of virtualization extensions to any existing ISA, or according to a variety of other approaches).
Regarding claims 7-8, 10-11, and 14-17, they are the method and system claims of claims 1-4 above. Therefore, they are rejected for the same reasons as claims 1-4 above.
Regarding claim 9, Tsai teaches the second physical processor notifying the virtual device driver in response to receiving the PI IPI ([0062]: a sending VM may send a notification/interrupt to a target VM without a VM exit and without invoking a VMM the notify-processor for the target processor in the target VM may, in response to a notify event, send an IPI by writing to the Interrupt Command Register of the corresponding vAPIC page (e.g., vAPIC page 23) with a vector corresponding to an inter-VM-IPI. If the target VM is active, the notification/interrupt may be delivered directly to the target VM (without a VM exit or invoking VMM) and without invoking a VMM. If the target VM is scheduled, the notification/interrupt may be posted (without a VM exit or invoking VMM).
Allowable Subject Matter
Claims 5-6, 12-13, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC C WAI whose telephone number is (571)270-1012. The examiner can normally be reached Monday - Friday 9-5.
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/Eric C Wai/Primary Examiner, Art Unit 2195
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