DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/28/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "on", "layer", "portion" are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently disclose a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “used as a function word to indicate position in close proximity with”, “one thickness lying over or under another”, “an often limited part of a whole” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claim(s) 1-6, 8, 11, 13, 15, 21, 23-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hou, Hsin-Ming (CN 202111587039.4 hereinafter Hou).
Regarding Claim 1, Hou discloses in Fig 1: A semiconductor device, comprising:
a substrate (10);
a first nitride semiconductor layer (12) on the substrate;
a second nitride semiconductor layer (18a/18b) on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer;
a first doped nitride semiconductor layer (20b) on the second nitride semiconductor layer; and
a second doped nitride semiconductor layer (20a) on the second nitride semiconductor layer, wherein a dopant of the first doped nitride semiconductor layer is different from a dopant of the second doped nitride semiconductor layer [0021, 0022]. See note above for interpretation of the limitation “on”.
Regarding Claim 2, Hou discloses in Fig 1: The semiconductor device of claim 1, wherein a height of the first doped nitride semiconductor layer (20b) is substantially identical to that of the second doped nitride semiconductor layer (20a).
Regarding Claim 3, Hou discloses in Fig 1: The semiconductor device of claim 1, wherein the first doped nitride semiconductor layer (20b) is spaced apart from the second doped nitride semiconductor layer (20a).
Regarding Claim 4, Hou discloses in Fig 1: The semiconductor device of claim 1, wherein the first doped nitride semiconductor layer comprises P-type doped material (20b), and the second doped nitride semiconductor layer comprises N-type doped material (20a).
Regarding Claim 5, Hou discloses in Fig 1: The semiconductor device of claim 1, wherein the N-type doped material comprises a group 4A element [0022].
Regarding Claim 6, Hou discloses in Fig 1: The semiconductor device of claim 1, wherein the N-type doped material comprises carbon, silicon, or germanium [0022].
Regarding Claim 8, Hou discloses in Fig 1: The semiconductor device of claim 4, wherein the N-type doped material is formed by executing a first manufacturing operation, wherein the first manufacturing operation includes ion implantation; or the N-type doped material is formed by executing a second manufacturing operation wherein the second manufacturing operation includes diffusion. The limitation “doped material is formed by executing a first manufacturing operation, wherein the first manufacturing operation includes ion implantation; or the N-type doped material is formed by executing a second manufacturing operation wherein the second manufacturing operation includes diffusion” in claim 8 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in “product by process” claim or not.
Regarding Claim 10, Hou discloses in Fig 1: The semiconductor device of claim 1, The semiconductor device of any of the preceding claims, further comprising: a first conductive structure (G2) on the first doped nitride semiconductor layer (20b); and a second conductive structure (G1) on the second doped nitride semiconductor layer (20a).
Regarding Claim 11, Hou discloses in Fig 1: The semiconductor device of claim 10, wherein a length of the second conductive structure (G1) is smaller than or equal to that of the second doped nitride semiconductor layer (20a).
Regarding Claim 13, Hou discloses in Fig 1: The semiconductor device of claim 1, further comprising: a third doped nitride semiconductor layer (20b) adjacent to a lateral surface of the second nitride semiconductor layer (18a/18b), wherein a material of the third doped nitride semiconductor layer is substantially the same as that of the first doped nitride semiconductor layer (20b). Examiner notes that even though Hou does not illustrates additional transistors formed on the wafer, one of ordinary skilled in the art would understand that the next transistor over would have a third doped nitride semiconductor layer that is adjacent (interpreted as near by) to a lateral surface of the second nitride semiconductor layer.
Regarding Claim 15, Hou discloses in Fig 1: The semiconductor device of claim 1, wherein a length of the first doped nitride semiconductor layer (20b) is different from that of the second doped nitride semiconductor layer (20a). Examiner notes that the length direction is not specified and hence one of ordinary skilled in the art would arbitrarily chose the direction so as to satisfy the claimed limitation.
Regarding Claim 21, Hou discloses in Fig 1: A semiconductor device, comprising: a first operating device (T1) above a first nitride semiconductor layer (12), comprising;
a first doped nitride semiconductor layer (20b) on a second nitride semiconductor layer (18a/18b), wherein the second nitride semiconductor layer is on the first nitride semiconductor layer and the second nitride semiconductor layer has a band gap greater than a band gap of the first nitride semiconductor layer [0021]; and
a first conductive structure (G2) on the first doped nitride semiconductor layer; and a second operating device (T2) separated from the first operating device, comprising:
a second doped nitride semiconductor layer (20a) on the second nitride semiconductor layer (18a/18b); and a second conductive structure (G1) on the second doped nitride semiconductor layer (20a), wherein the first doped nitride semiconductor layer and the second doped nitride semiconductor layer have substantially identical thickness (See Fig 1) [0022-0023]. See note above for interpretation of the limitation “on”.
Regarding Claim 22, The semiconductor device of claim 21, The semiconductor device of any of the preceding claims, wherein the first operating device (T2) comprises an enhancement-mode semiconductor device, and the second operating device (T1) comprises a depletion-mode semiconductor device. It is the Examiner’s position that the limitation of a " an enhancement-mode and a depletion mode,” are functional limitations of the apparatus claimed and has therefore not been given patentable weight. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431- 32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959); MPEP 2114.
Regarding Claim 23, The semiconductor device of claim 21, wherein the first doped nitride semiconductor layer comprises P-type doped material (20b), and the second doped nitride semiconductor layer comprises N-type doped material (20a).
Regarding Claim 24, The semiconductor device of claim 21, wherein the N-type doped material comprises a group 4A element or a hydrogen element [0022].
Regarding Claim 25, The semiconductor device of claim 23, The limitation “wherein the N-type doped material is provided through executing ion implantation or diffusion.” in claim 25 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in “product by process” claim or not.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwan et al (US 11,522,077 B2 hereinafter Kwan).
Regarding claim 16, Kwan discloses in Fig 12: A method for manufacturing a semiconductor device, comprising:
forming a substrate (102);
forming a first nitride semiconductor layer (104) on the substrate;
forming a second nitride semiconductor layer (106) on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap greater than a band gap of the first nitride semiconductor layer;
forming a first doped nitride semiconductor layer (114) on the second nitride semiconductor layer;
forming a dielectric layer (802) on the second nitride semiconductor layer; and
performing ion implantation on a first region of the first doped nitride semiconductor layer to form a second doped nitride semiconductor layer (122) (Col 11 lines 27-64). See note above for interpretation of the limitation “on”.
Regarding claim 17, Kwan discloses in Fig 12: The method of any of the preceding claims, further comprising: forming a conductive layer (116, 126) on the first doped nitride semiconductor layer and the second doped nitride semiconductor layer.
Regarding claim 18, Kwan discloses in Fig 12: The method of any of the preceding claims, further comprising: removing a second portion of the first doped nitride semiconductor layer, which surrounds the first portion of the first doped nitride semiconductor layer.
Regarding claim 19, Kwan discloses in Fig 12: The method of any of the preceding claims, wherein the first doped nitride semiconductor layer comprises P-type doped material, and the second doped nitride semiconductor layer comprises N-type doped material (Col 11 lines 27-64). Examiner notes that even though Kwan discloses first conductivity type to be N-type and second conductivity type as P-type, one of ordinary skilled in the art would find it obvious that the conductivity types can be switched for one another.
Conclusion
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811