DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 05/23/2026 has been acknowledged. Claims 1, 2-3 and 6 have been amended. Claim 5 is canceled. Claims 21-27 are added. No new matter has been added.
This office action considers claims 1-4 and 6 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 05/23/2026 with respect to the rejection of claims 1 and 5-6 have been fully considered but are moot in view of the new grounds of rejection.
Objection
Claims 1-4 are objected to because of the following informalities: the formula for Al1-v-wGavInwN is written in different and inconsistent formats. The claim amendments write it as Al1-v-wGavInwN while the previous claims wrote it as Al1-v-wGavInwN, however the specifications write it as above and as Al.sub.1-v-wGa.sub.vIn.sub.wN in the claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee at al. (US 20060068601 A1 – hereinafter Lee) in view of Kim et al. (US 20120202306 A1 – hereinafter Kim), Park et al. (US 20160027964 A1 – hereinafter Park), and Liu et al. (Fabrication of crack-free AlN film on sapphire by hydride vapor phase epitaxy using an in situ etching method, Applied Physics Express 9, 2016 – hereinafter Liu).
Regarding independent claim 1, Lee teaches
(Currently Amended) A method of manufacturing an aluminum
nitride (AIN) layer ([0037] – “an AlN layer is grown” – hereinafter ‘AlN’),
comprising:
preparing a growth substrate (2 – Fig. 2 – {[0025] – “substrate 2”}, {[0065] – “substrate can be made from materials other than silicon adoptable as long as they permit epitaxial growth of nitride semiconductors, examples being sapphire, silicon compound”});
growing ([0024] – “buffer layers 9 and 10 are successively grown by epitaxy on the silicon substrate 2”) Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9 – Fig. 3 – [0028] – “first buffer layers 9 are all made from an aluminum-containing nitride semiconductor selected from among the Groups III-V compound semiconductors that are generally defined as: Al.sub.xM.sub.yGa.sub.1-x-yN where M is at least either of indium and boron; the subscript x is a numeral that is greater than zero and equal to or less than one; the subscript y is a numeral that is equal to or greater than zero and less than one; and the sum of x and y is equal to or less than one}) on the growth substrate (2);
etching ([0039] – “Those parts of the surface of the second buffer layer 10 which are left exposed by the sparse deposition of AlN will then be subjected to the etching action of the reactor atmosphere, with the consequent creation of the voids 15 in the second buffer layer”) the Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9) by decomposing and evaporating gallium (Ga) and indium (In) ([0038] – “The lowermost non-sublayered, open-worked second buffer layer 10 is created upon completion of the lowermost multi-sublayered first buffer layer 9. The same material as that of the second sublayers L.sub.2 of the first buffer layer 9 may be grown in the same MOVPE reactor for creation of the second buffer layer 10. However, the second buffer layers 10 may be made from a different material, such as InGaN, from that of the second sublayers L.sub.2 of the first buffer layer 9. The lowermost second buffer layer 10 thus grown on the lowermost first buffer layer 9 is not yet open-worked but is to be in the course of the ensuing fabrication of the lowest first sublayer L.sub.1 of the second lowest multi-sublayered first buffer layer 9”) therein to obtain a porous ([0039] – “Those parts of the surface of the second buffer layer 10 which are left exposed by the sparse deposition of AlN will then be subjected to the etching action of the reactor atmosphere, with the consequent creation of the voids 15 in the second buffer layer” – this describes a porous layer) Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9) having a first plurality of air voids;
forming a second plurality of air voids which is corresponding to the first plurality of air voids in the growth substrate (2) using the porous Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9) as an etching mask ([0070] – “The voids 15 in the second buffer layers 10 of the buffer region 3 or 3' may be created by masking and etching”), wherein the forming of the second plurality of air voids in the growth substrate is performed at temperature of 1000°C or higher under H2 reducing atmosphere;
growing an AlN layer ([0037] – “For making the lowermost multi-sublayered first buffer layer 9 on this substrate 2, the first and second sublayers L.sub.1 and L.sub.2 may be alternately grown a prescribed number of times by the known method of metal organic vapor phase epitaxy (MOVPE). If the first sublayers L.sub.1 are to be made from AlN, trimethyl aluminum (TMA) and ammonia (NH.sub.3) may be charged in required proportions into the MOVPE reactor until an AlN layer is grown each time to a thickness of five nanometers or so”) on the porous Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9),
growing a Group III-nitride semiconductor diode region containing aluminum (Al) on the AlN layer, and
separating the growth substrate from the Group II-nitride semiconductor diode region using the porous Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer as a sacrificial layer.
Lee does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Kim teaches
a first plurality of air voids (103a – Fig. 1(D) – [0049] – “a hole 103a is deepened to form a void 102a” – 103a is interpreted as a void);
forming a second plurality of air voids (102a – Fig. 1(D) – [0049] – “a hole 103a is deepened to form a void 102a”) which is corresponding to the first plurality of air voids (103a – Fig. 1(D) shows this),
wherein the forming of the second plurality of air voids (102a) in the growth substrate (102 – Fig. 1(D) – [0047] – “a first GaN layer 102 having a thickness of about 2 .mu.m is formed on the sapphire substrate 101” – this is the growth substrate) is performed at temperature of 1000°C or higher ([0062] – “crystal growth was performed at a heating temperature of 1045.degree. C”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second plurality of air void structure as taught by Kim into Lee.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [0012] – “a method of fabricating a flat and easily separable GaN substrate on a heterogeneous substrate at low cost.”
Lee and Kim do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Liu teaches
wherein the forming of the second plurality of air voids in the growth substrate is performed at temperature of 1000°C or higher under H2 reducing atmosphere (Fabrication of crack-free AlN film on sapphire by hydride vapor phase epitaxy using an in situ etching method, Applied Physics Express 9, 2016 – [Page 2, Column 2, lines 12-14] – “voids were generated by interrupting the growth and increasing the temperature to 1550 °C, before etching the sample in H2 for 2 min”);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate atmosphere forming parameters as taught by Liu into Lee and Kim.
An ordinary artisan would have been motivated to use the known technique of Liu in the manner set forth above to produce the predictable result of [page 3, first column, sentences 13-22] – “a new growth scheme for achieving thick, high-quality AlN film on sapphire using an in situ etching technique. In this approach, voids are formed at locations exhibiting high strain and high dislocation densities; they then serve as a barrier for the misfit strain and dislocations. TEM measurements, combined with Raman spectra and X-ray diffraction measurements, showed that the voids effectively relax the misfit strain and reduce the dislocation density. This technique allows the fabrication of high-quality crack-free AlN thick film.”
Lee, Kim, and Liu do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Park teaches
growing a Group III-nitride semiconductor diode region (Fig. 20 annotated, see below – hereinafter “DR’ – 100a – Fig. 10 – [0097] – “a light emitting diode 100a as shown in FIG. 10”) containing aluminum (Al) ({[0035] – “a light emitting diode is fabricated by forming an AlN layer at high temperature on the sapphire substrate or forming an AlN/AlGaN superlattice layer on the sapphire substrate, followed by forming an n-type semiconductor layer including an Al.sub.xGa.sub.(1-x)N (0.2≦x≦1), an active layer, and a p-type semiconductor layer”}, {0112] – “Growth of the second n-type semiconductor layer 133 includes introducing an Al source, a GaN source and an N source into the growth chamber, in which growth temperature can be set in the range of about 900° C. to about 1100° C”) on the AlN layer (125 – Fig. 20 – [0097] – “the AlN layer 125 remaining on the n-type semiconductor layer 130 after separation of the growth substrate 110 can be removed by various methods”), and
separating the growth substrate (110 – Fig. 20 – [0097] – “separation of the growth substrate 110 can be removed by various methods”) from the Group II-nitride semiconductor diode region (DR) using the porous Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer as a sacrificial layer ({[0083] – “additional layers, for example, a sacrificial layer, can be formed between the growth substrate 110 and the semiconductor layers, and the growth substrate 110 can be separated from the semiconductor layers by chemical lift-off or stress lift-off”},{[0109] – “a buffer layer 121, a GaN layer 123, an AlN layer 125 and an undoped nitride layer 127 are grown on a growth substrate 110” – this corresponds to a sacrificial layer).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate diode growth and sacrificial separation layer structure as taught by Park into Lee, Kim, and Liu.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of [0027] – “a method of fabricating a UV light emitting diode, which can improve crystallinity of the UV light emitting diode through a relatively simple and easy process. In addition, embodiments of the disclosure provide a UV light emitting diode, from which a growth substrate is removed, thereby providing excellent luminous efficacy. Further, some implementations of the UV light emitting diode can prevent damage due to stress within semiconductor layers, thereby providing improved reliability.”
Regarding claim 2, Lee, as modified by Kim, Liu, and Park, teaches claim 1 from which claim 2 depends. Lee further teaches
(Currently Amended) The method of claim 1, wherein the growing
and etching of [[an]] the Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9) are repeated several times ({[0037] – “fabrication of the semiconductor wafer 1, configured as above described with reference to FIGS. 1-3, starts with the preparation of the silicon substrate 2”}, {[0039] – “Then comes the fabrication of that lowest first sublayer L.sub.1 of the second lowest multi-sublayered first buffer layer 9 following the creation of the not-yet-open-worked lowermost second buffer layer 10. The lowest first sublayer L.sub.1 of the second lowest first buffer layer 9 is grown on the not-yet-open-worked lowermost second buffer layer 10 by introducing TMA into the reactor at a reduced rate”) before the forming of [[a]] the second plurality of air voids in the growth substrate (2).
Lee, Liu, and Park do not expressly disclose the other limitations of claim 2.
However, in an analogous art, Kim teaches
the second plurality of air voids (102a).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second plurality of air void structure as taught by Kim into Lee, Liu, and Park.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 3, Lee, as modified by Kim, Liu, and Park, teaches claim 1 from which claim 3 depends. Lee further teaches
(Currently Amended) The method of claim 1, wherein the etching of
the Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) layer (9) and the growing of [[an]] the AlN layer (AlN) are repeated several times (n times) ([0013] – “All the constituent layers of the buffer region and the main semiconductor region thereon are successively formed by vapor-phase growth of nitride semiconductors on the substrate. Even the required voids in the second buffer layers are formed in the course of such vapor-phase growth of the successive layers, simply by, after the growth of each second buffer layer, introducing materials for the lowermost first sublayer of the next first buffer layer into the reactor at a rate low enough for the voids to be created by the etching action of the reactor atmosphere” – this is interpreted as a repeated process between growing and etching) in the growing of [[an]] the Al1-v-wGavInwN (0≤v<1, 0≤w<1, v+w<1) (9).
Regarding claim 4, Lee, as modified by Kim, Liu, and Park, teaches claim 1 from which claim 4 depends. Lee further teaches
(Original) The method of claim 1, wherein the Al1-v-wGavInwN (0≤v<1,
0≤w<1, v+w<1) (9) layer is an Al1-v-wGavInwN (0<v<1) layer ([0029] – “the Groups III-V compound semiconductors that are generally expressed by the formula: Al.sub.aM.sub.bGa.sub.1-a-bN where M is at least either of indium and boron; the subscript a is a numeral that is equal to or greater than zero and less than one and, additionally, less than x in the formula above defining the materials for the first buffer sublayers L.sub.1; the subscript b is also a numeral that is equal to or greater than zero and less than one; and the sum of a and b is equal to or less than one. Thus the second buffer sublayers L.sub.2 can be made from such compounds as GaN, InGaN, AlInN, AlGaN, and AlInGaN, of which GaN is currently preferred”).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim, Liu, Park, and Keller et al. (US 20240063340 A1 – hereinafter Keller).
Regarding claim 6, Lee, as modified by Kim, Liu, and Park, teaches claim 1 from which claim 6 depends. Lee, Kim, Liu, and Park do not expressly disclose the limitations of claim 6.
However, in an analogous art, Keller teaches
(Currently Amended) The method of claim [[5]] 1, wherein the Group
III-nitride semiconductor diode region includes an active region ([0574] – “light emitting devices include an active region having a different indium content and emitting a different wavelength of electromagnetic radiation”) emitting ultraviolet light ([0524] – “The (Al,Ga)—N alloy system is very attractive for ultraviolet (UV) optoelectronic devices”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the diode emitting characteristics as taught by Keller into Lee, Kim, Liu, and Park.
An ordinary artisan would have been motivated to use the known technique of Keller in the manner set forth above to produce the predictable result a device capable of emitting wavelength of light corresponding to ultraviolet.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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