Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/4/2024, 8/21/2025 and 4/9/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of Claims
The present application is being examined under the claims filed on 12/29/2023.
Claims 1-11 and 15-16 are rejected.
Claims 1-11 and 15-16 are pending.
Specification
The specification filed on 12/29/2023 is acceptable for examination purposes.
Drawings
The drawings filed on 12/29/2023 are acceptable for examination purposes.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “an operator”, “a first type converter”, “a first operator”, “a second operator” and “a second type converter” in claims 1, 2, 6 and 15.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim limitations “an operator configured to perform at least one operation to obtain an operation result” [claim 1], “a first type converter configured to convert a data type of the operation result into a third data type” [claim 1], “a first operator configured to perform a first type operation in a first data type to obtain a result of the first type operation” [claim 2], “a second operator configured to perform a second type operation on the result of the first type operation in a second data type to obtain a result of the second type operation” [claim 2], and “a second type converter configured to convert the operation result in the third data type into the first data type or the second data type for subsequent operations of the first operator or the second operator” [claim 6] invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. In particular, the specification, at best, describes “a processing apparatus 400 includes an operator 401, a first type converter 402, a memory 403, and a controller 404” (Spec. p. 6) and does not provide any specific hardware or structure to support the claimed operator and converter. Thus, the disclosure provides no association between the structure and the function can be found in the specification. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
In reference to dependent claims 2-11, claims 2-11 do not cure the deficiencies noted in the rejection of independent claim 1. Therefore, these claims are rejected under the same rationale as claim 1.
For the purpose of this examination, limitations “operator” and “converter” are interpreted as software module loaded in either a memory 403 or a controller 404. See MPEP 2173.06(I).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-11 and 15-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding Claim 1,
Step 1: Claim 1 is an apparatus claim. Therefore, Claims 1-11 are directed to a machine.
Step 2A Prong 1:
[an operator configured to] perform at least one operation to obtain an operation result (mental process - performing at least one operation to obtain an operation result may be performed manually by a user with the aid of pen and paper by analyzing/performing at least one operation. An operator is interpreted as software module loaded in a controller or a memory. See MPEP 2106.04(a)(2)(III)(C).)
[a first type converter configured to] convert a data type of the operation result into a third data type, wherein data precision of the data type of the operation result is greater than data precision of the third data type, and [the third data type is suitable for storage and transfer of the operation result] (mental process - converting a data type of the operation result into a third data type may be performed manually by a user with the aid of pen and paper by observing/analyzing a data type of the operation result and converting to a third data type. See MPEP 2106.04(a)(2)(III)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
an operator configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
a first type converter configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
the third data type is suitable for storage and transfer of the operation result (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
an operator configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
a first type converter configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
the third data type is suitable for storage and transfer of the operation result (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
For the reasons above, Claim 1 is rejected as being directed to an abstract idea without significantly more. This rejection applies equally to dependent claims 2-11. The additional limitations of the dependent claims are addressed below.
Regarding Claim 2,
Step 2A Prong 1:
[a first operator configured to] perform a first type operation in a first data type to obtain a result of the first type operation (mental process - performing a first type operation in a first data type to obtain a result of the first type operation may be performed manually by a user with the aid of pen and paper by analyzing/performing a first type operation in a first data type. See MPEP 2106.04(a)(2)(III)(C).)
[a second operator configured to] perform a second type operation on the result of the first type operation in a second data type to obtain a result of the second type operation (mental process - performing a second type operation on the result of the first type operation in a second data type to obtain a result of the second type operation may be performed manually by a user with the aid of pen and paper by analyzing/performing a second type operation on the result of the first type operation in a second data type. See MPEP 2106.04(a)(2)(III)(C).)
perform a nonlinear layer operation of a neural network on the result of the second type operation to obtain a result of the nonlinear layer operation in the second data type (mental process - performing a nonlinear layer operation of a neural network on the result of the second type operation to obtain a result of the nonlinear layer operation in the second data type may be performed manually by a user with the aid of pen and paper by analyzing/performing a nonlinear layer operation of a neural network on the result of the second type operation. See MPEP 2106.04(a)(2)(III)(C).)
[wherein the first type converter is configured to] convert the result of the nonlinear layer operation into an operation result in the third data type (mental process - converting the result of the nonlinear layer operation into an operation result in the third data type may be performed manually by a user with the aid of pen and paper by observing/analyzing the result of the nonlinear layer operation and converting to an operation result in the third data type. See MPEP 2106.04(a)(2)(III)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
a first operator configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
a second operator configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
wherein the first type converter is configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
a first operator configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
a second operator configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
wherein the first type converter is configured to (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
Regarding Claim 3,
Step 2A Prong 1:
data precision of the third data type is less than the data precision of the first data type and/or the data precision of the second data type (mathematical concept - data precision of the third data type is less than the data precision of the first data type and/or the data precision of the second data type may be performed by mathematical process, comparing the data precision of the third data type with the data precision of the first data type and/or the data precision of the second data type. See MPEP 2106.04(a)(2)(I)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
wherein the first data type has data precision of low bit length, the second data type has data precision of high bit length (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
wherein the first data type has data precision of low bit length, the second data type has data precision of high bit length (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 4,
Step 2A Prong 1:
See the rejection of Claim 3 above, which Claim 4 depends on.
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
wherein the first data type includes a half-precision floating-point data type, the second data type includes a single-precision floating-point data type, and the third data type includes a TF32 data type, wherein theTF32 data type has a 10- bit mantissa and an 8-bit exponent (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
wherein the first data type includes a half- precision floating-point data type, the second data type includes a single-precision floating-point data type, and the third data type includes a TF32 data type, wherein theTF32 data type has a 10- bit mantissa and an 8-bit exponent (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 5,
Step 2A Prong 1:
See the rejection of Claim 1 above, which Claim 5 depends on.
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
wherein the first type converter is also configured for data type conversion between different operations (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
wherein the first type converter is also configured for data type conversion between different operations (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 6,
Step 2A Prong 1:
[a second type converter configured to] convert the operation result in the third data type into the first data type or the second data type for subsequent operations of the first operator or the second operator (mental process - converting the operation result in the third data type into the first data type or the second data type for subsequent operations of the first operator or the second operator may be performed manually by a user with the aid of pen and paper by observing/analyzing the operation result in the third data type and converting to the first data type or the second data type. See MPEP 2106.04(a)(2)(III)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
a second type converter configured to (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
a second type converter configured to (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 7,
Step 2A Prong 1:
[wherein the first type converter and/or the second type converter are configured to] perform a truncation operation on the operation result by using a truncation method based on a nearest neighbor principle or a preset truncation method to achieve the data type conversion (mathematical concept - performing a truncation operation on the operation result by using a truncation method based on a nearest neighbor principle or a preset truncation method to achieve the data type conversion may be performed by mathematical process, using a truncation method based on a nearest neighbor principle or a preset truncation method. See MPEP 2106.04(a)(2)(I)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
wherein the first type converter and/or the second type converter are configured to (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
wherein the first type converter and/or the second type converter are configured to (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 8,
Step 2A Prong 1:
See the rejection of Claim 1 above, which Claim 8 depends on.
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
at least one on-chip memory configured to store the operation result in the third data type, and to interact data with at least one off-chip memory in the third data type (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
at least one on-chip memory configured to store the operation result in the third data type, and to interact data with at least one off-chip memory in the third data type (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 9,
Step 2A Prong 1:
See the rejection of Claim 1 above, which Claim 9 depends on.
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
a compressor configured to compress the operation result in the third data type for storage and transfer (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
a compressor configured to compress the operation result in the third data type for storage and transfer (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 10,
Step 2A Prong 1:
[wherein one or more of the first operator, the second operator, the first type converter, and the second type converter are configured to perform one or more of following operations:] an operation that is directed to gradient propagation in a training process of the neural network, and an operation that is directed to weight updating in the training process of the neural network (mathematical concept - an operation that is directed to gradient propagation in a training process of the neural network, and an operation that is directed to weight updating in the training process of the neural network may be performed by mathematical process, using a gradient propagation (backpropagation) algorithm and updating the weight. See MPEP 2106.04(a)(2)(I)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
wherein one or more of the first operator, the second operator, the first type converter, and the second type converter are configured to perform one or more of following operations: (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
an operation that is directed to an output neuron in an inference process of the neural network (Adding insignificant extra-solution activity to the judicial exception. See MPEP 2106.05(g).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
wherein one or more of the first operator, the second operator, the first type converter, and the second type converter are configured to perform one or more of following operations: (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
an operation that is directed to an output neuron in an inference process of the neural network (MPEP 2106.05(d)(II) indicates that merely “Receiving or transmitting data over a network” is a well-understood, routine, conventional function when it is claimed in a merely generic manner (as it is in the present claim). Thereby, a conclusion that the claimed limitation is well-understood, routine, conventional activity is supported under Berkheimer)
Regarding Claim 11,
Step 2A Prong 1:
See the rejection of Claim 10 above, which Claim 11 depends on.
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
wherein, in the inference process of the neural network and/or the training process of the neural network, the first type operation includes a multiplication operation, the second type operation includes an addition operation, and the nonlinear layer operation includes an activation operation (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
wherein, in the inference process of the neural network and/or the training process of the neural network, the first type operation includes a multiplication operation, the second type operation includes an addition operation, and the nonlinear layer operation includes an activation operation (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Regarding Claim 15,
Step 1: Claim 15 is a method claim. Therefore, Claim 15 is directed to a process.
Step 2A Prong 1:
performing at least one operation to obtain an operation result (mental process - performing at least one operation to obtain an operation result may be performed manually by a user with the aid of pen and paper by analyzing/performing at least one operation. See MPEP 2106.04(a)(2)(III)(C).)
converting a data type of the operation result into a third data type, wherein data precision of the data type of the operation result is greater than data precision of the third data type (mental process - converting a data type of the operation result into a third data type may be performed manually by a user with the aid of pen and paper by observing/analyzing a data type of the operation result and converting to a third data type. See MPEP 2106.04(a)(2)(III)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
the third data type is suitable for storage and transfer of the operation result (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
wherein the apparatus includes: an operator configured to perform at least one operation to obtain an operation result (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
a first type converter configured to convert a data type of the operation result into a third data type, wherein data precision of the data type of the operation result is greater than data precision of the third data type, and the third data type is suitable for storage and transfer of the operation result (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
the third data type is suitable for storage and transfer of the operation result (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
wherein the apparatus includes: an operator configured to perform at least one operation to obtain an operation result (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
a first type converter configured to convert a data type of the operation result into a third data type, wherein data precision of the data type of the operation result is greater than data precision of the third data type, and the third data type is suitable for storage and transfer of the operation result (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
For the reasons above, Claim 15 is rejected as being directed to an abstract idea without significantly more.
Regarding Claim 16,
Step 1: Claim 16 is a non-transitory computer readable medium claim. Therefore, Claim 16 is directed to a machine.
Step 2A Prong 1:
[when executed by a processor, cause the processor to perform operations including:] performing at least one operation to obtain an operation result (mental process - performing at least one operation to obtain an operation result may be performed manually by a user with the aid of pen and paper by analyzing/performing at least one operation. See MPEP 2106.04(a)(2)(III)(C).)
converting a data type of the operation result into a third data type, wherein data precision of the data type of the operation result is greater than data precision of the third data type (mental process - converting a data type of the operation result into a third data type may be performed manually by a user with the aid of pen and paper by observing/analyzing a data type of the operation result and converting to a third data type. See MPEP 2106.04(a)(2)(III)(C).)
Step 2A Prong 2: The judicial exceptions are not integrated into a practical application.
Additional Elements:
when executed by a processor, cause the processor to perform operations including: (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
the third data type is suitable for storage and transfer of the operation result (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional Elements:
when executed by a processor, cause the processor to perform operations including: (merely using a computer as a tool to perform an abstract idea. See MPEP 2106.05(f).)
the third data type is suitable for storage and transfer of the operation result (merely reciting the words "apply it" (or an equivalent) with the judicial exception. See MPEP 2106.05(f).)
For the reasons above, Claim 16 is rejected as being directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-8 and 15-16 are rejected under 35 U.S.C. 102 as being anticipated by Chen et al. (CN 106951962 A), hereinafter Chen.
Regarding Claim 1,
Chen teaches:
“A processing apparatus, comprising” (preamble)
“an operator configured to perform at least one operation to obtain an operation result” (Chen, Paragraph 6 in Page 1, “a multiply-add module, configured to receive output data of a previous layer and a weight value of a current layer, and according to the weight of the current layer The value is used to perform a multiplication and addition operation on the output data of the previous layer to generate a multiplication and addition operation result”; Examiner’s note: an operator (i.e. a multiply-add module) configured to perform at least one operation (i.e. a multiplication and addition operation) to obtain an operation result (i.e. a multiplication and addition operation result) is taught.)
“a first type converter configured to convert a data type of the operation result into a third data type” (Chen, Paragraphs 5 and 8 in Page 6, “the composite operation unit 100 for a neural network further includes an inverse quantization module 150 and a quantization module 160 […] the so-called quantization refers to converting high-precision output data into output data with low precision in a certain manner (for example, multiplication, division, look-up table, and shift). In contrast, the so-called inverse quantization refers to quantization. Low-precision output data is converted into high-precision output data by a certain method (for example, multiplication, division, table look-up, and shifting).”; Examiner’s note: a first type converter (i.e. a quantization module) configured to convert a data type of the operation result (i.e. high-precision output data) into a third data type (i.e. output data with low precision in a certain manner) is taught.)
“wherein data precision of the data type of the operation result is greater than data precision of the third data type” (Chen, Paragraph 6 in Page 8, “[…] quantization refers to converting high-precision output data (for example, 32 bits) into output data (for example, 8 bits) with low precision by a certain method (for example, multiplication, division, look-up table, shift).”; Examiner’s note: wherein data precision of the data type of the operation result (i.e. high-precision output data, 32bits for example) is greater than data precision of the third data type (i.e. output data with low precision, 8 bits for example) is taught.)
“the third data type is suitable for storage and transfer of the operation result” (Chen, Paragraph 13 in Page 4, “The output data of the specific layer is stored in a specific storage space of the memory […]”; Chen, Paragraph 3, Page 5, “[…] the first and second memories may be off-chip double-rate (DDR) memory […]”; Examiner’s note: the third data type (i.e. the output data of the specific layer) is suitable for storage (i.e. memory) and transfer of the operation result (i.e. off-chip double-rate memory) is taught.)
Regarding Claim 2,
Chen teaches:
“The processing apparatus of claim 1, comprising” (preamble)
“a first operator configured to perform a first type operation in a first data type to obtain a result of the first type operation” (Chen, Paragraph 6 in Page 1, “a multiply-add module, configured to receive output data of a previous layer and a weight value of a current layer, and according to the weight of the current layer The value is used to perform a multiplication and addition operation on the output data of the previous layer to generate a multiplication and addition operation result”; Examiner’s note: a first operator (i.e. a multiply-add module) configured to perform a first type operation (i.e. a multiplication and addition operation) in a first data type to obtain a result of the first type operation (i.e. a multiplication and addition operation result) is taught.)
“a second operator configured to perform a second type operation on the result of the first type operation in a second data type to obtain a result of the second type operation” (Chen, Paragraph 6 in Page 1, “[…] a point-by-point operation module is configured to receive the multiplication and addition operation result and acquire a specific layer according to the stored data of the first memory. Outputting data, the specific layer precedes the current layer, and perform point-by-point operations on the output data of the specific layer and the multiply-accumulate operation result to generate a point-by-point operation result […]”; Examiner’s note: a second operator (i.e. a point-by-point operation module) configured to perform a second type operation (i.e. point-by-point operations) on the result of the first type operation (i.e. the multiplication and addition operation result) in a second data type to obtain a result of the second type operation (i.e. a point-by-point operation result) is taught.)
“perform a nonlinear layer operation of a neural network on the result of the second type operation to obtain a result of the nonlinear layer operation in the second data type” (Chen, Paragraphs 4 and 5 in Page 5, “[…] an activation function module 140 configured to write the point-by-point operation result into the second memory […] With the addition of (non-linear) activation functions, deep neural networks have layered nonlinear mapping learning capabilities. For example, commonly used activation functions include: Sigmoid, Tanh, ReLU, and so on.”; Examiner’s note: performing a nonlinear layer operation of a neural network (i.e. nonlinear activation functions) on the result of the second type operation (i.e. the point-by-point operation result) to obtain a result of the nonlinear layer operation in the second data type (i.e. activation function operation result) is taught.)
“wherein the first type converter is configured to convert the result of the nonlinear layer operation into an operation result in the third data type” (Chen, Paragraphs 5 and 8 in Page 6, “the composite operation unit 100 for a neural network further includes an inverse quantization module 150 and a quantization module 160 […] the so-called quantization refers to converting high-precision output data into output data with low precision in a certain manner (for example, multiplication, division, look-up table, and shift).”; Examiner’s note: wherein the first type converter (i.e. a quantization module) is configured to convert the result of the nonlinear layer operation (i.e. high-precision output data) into an operation result in the third data type (i.e. output data with low precision in a certain manner) is taught.)
Regarding Claim 3,
Chen teaches:
“The processing apparatus of claim 2,” (preamble)
“wherein the first data type has data precision of low bit length, the second data type has data precision of high bit length” (Chen, Paragraph 9 in Page 8, “the so-called dequantization refers to conversion of quantized low-precision output data (for example, 8 bits) into high-precision output data (for example, 32 bits) by a certain method (for example, multiplication, division, look-up table, and shift).”; Examiner’s note: wherein the first data type has data precision of low bit length (i.e. low-precision output data, 8 bits for example), the second data type has data precision of high bit length (i.e. high-precision output data, 32 bits for example) is taught.)
“data precision of the third data type is less than the data precision of the first data type and/or the data precision of the second data type” (Chen, Paragraph 2 in Page 9, “It can be seen that the above access to the memory is reduced by combining the multiply-add calculation of the N+m-th layer and the point-by-point operation and the optional ReLU operation into one operation. Specifically, by the above operation, the number of times of accessing the memory is reduced from 7 times in the prior art to 3 times (2 writes and 1 read).”; Examiner’s note: data precision of the third data type (i.e. one combined operation) is less than the data precision of the first data type (i.e. multiply-add calculation) and/or the data precision of the second data type (i.e. point-by-point operation) is taught.)
Regarding Claim 5,
Chen teaches:
“The processing apparatus of claim 1,” (preamble)
“wherein the first type converter is also configured for data type conversion between different operations” (Chen, Paragraphs 5 and 8 in Page 6, “the composite operation unit 100 for a neural network further includes an inverse quantization module 150 and a quantization module 160 […] the so-called quantization refers to converting high-precision output data into output data with low precision in a certain manner (for example, multiplication, division, look-up table, and shift). In contrast, the so-called inverse quantization refers to quantization. Low-precision output data is converted into high-precision output data by a certain method (for example, multiplication, division, table look-up, and shifting).”; Examiner’s note: wherein the first type converter (i.e. a quantization module) is also configured for data type conversion between different operations (i.e. multiplication, division, look-up table, and shift) is taught.)
Regarding Claim 6,
Chen teaches:
“The processing apparatus of claim 1, further comprising” (preamble)
“a second type converter configured to convert the operation result in the third data type into the first data type or the second data type for subsequent operations of the first operator or the second operator” (Chen, Paragraph 12 in Page 6, “the dequantization module 150 may read the low-precision quantized output data of the specific layer from the first memory and perform an inverse quantization operation on the quantized output data of the specific layer to generate the specific layer's high Accuracy outputs data, and sends the high-precision output data of the specific layer to the point-by-point operation module.”; Examiner’s note: a second type converter (i.e. the dequantization module) configured to convert the operation result in the third data type (i.e. the low-precision quantized output data of the specific layer) into the first data type or the second data type for subsequent operations of the first operator or the second operator (i.e. performing an inverse quantization operation on the quantized output data, generating the specific layer’s high Accuracy outputs data and sending the high-precision output data of the specific layer to the point-by-point operation module) is taught.)
Regarding Claim 7,
Chen teaches:
“The processing apparatus of claim 6,” (preamble)
“wherein the first type converter and/or the second type converter are configured to perform a truncation operation on the operation result by using a truncation method based on a nearest neighbor principle or a preset truncation method to achieve the data type conversion” (Chen, Paragraphs 5 and 8 in Page 6, “the composite operation unit 100 for a neural network further includes an inverse quantization module 150 and a quantization module 160 […] the so-called quantization refers to converting high-precision output data into output data with low precision in a certain manner (for example, multiplication, division, look-up table, and shift). In contrast, the so-called inverse quantization refers to quantization. Low-precision output data is converted into high-precision output data by a certain method (for example, multiplication, division, table look-up, and shifting).”; Examiner’s note: wherein the first type converter (i.e. a quantization module) and/or the second type converter (i.e. an inverse quantization module) are configured to perform a truncation operation (i.e. shift operations involve truncation) on the operation result by using a truncation method based on a nearest neighbor principle (i.e. a nearest neighbor principle is the truncation/rounding method) or a preset truncation method to achieve the data type conversion (i.e. a preset truncation method is the conventional means for the data type conversion) is taught.)
Regarding Claim 8,
Chen teaches:
“The processing apparatus of claim 1, further comprising” (preamble)
“at least one on-chip memory configured to store the operation result in the third data type, and to interact data with at least one off-chip memory in the third data type” (Chen, Paragraphs 2 and 3 in Page 5, “the output module 130 may write the result of the point-by-point operation as the output data of the current layer into the second memory […] the first and second memories may be off-chip double-rate (DDR) memory, on-chip SRAM, on-chip cache, on-chip registers.”; Examiner’s note: at least one on-chip memory (i.e. the second memory) configured to store the operation result in the third data type (i.e. the result of the point-by-point operation), and to interact data with at least one off-chip memory (i.e. off-chip double-rate (DDR) memory) in the third data type is taught.)
Regarding Claim 15,
Claim 15 recites substantially the same limitations as Claim 1, in the form of a method and a system, therefore, it is rejected under the same rationale.
Regarding Claim 16,
Claim 16 recites substantially the same limitations as Claim 1, in the form of a system, therefore, it is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Stosic et al. (“Accelerating AI Training with NVIDIA TF32 Tensor Cores”) (hereinafter Stosic).
Regarding Claim 4,
Chen teaches:
“The processing apparatus of claim 3,” (preamble)
Chen does not explicitly teach:
“wherein the first data type includes a half- precision floating-point data type, the second data type includes a single-precision floating-point data type, and the third data type includes a TF32 data type, wherein theTF32 data type has a 10- bit mantissa and an 8-bit exponent”
Stosic teaches:
“wherein the first data type includes a half- precision floating-point data type, the second data type includes a single-precision floating-point data type, and the third data type includes a TF32 data type, wherein theTF32 data type has a 10- bit mantissa and an 8-bit exponent” (Stosic, Fig. 2 and Numerics in Page 2, “Figure 2 shows the various precision options. TF32 mode in the Ampere generation of GPUs adopts 8 exponent bits, 10 bits of mantissa, and one sign bit. As a result, it covers the same range of values as FP32. TF32 also maintains more precision than BF16 and the same amount as FP16.“; Examiner’s note: wherein the first data type includes a half-precision floating-point data type (i.e. FP16), the second data type includes a single-precision floating-point data type (i.e. FP32), and the third data type includes a TF32 data type, wherein the TF32 data type (i.e. TF32) has a 10-bit mantissa (i.e. 10 bits of mantissa) and an 8-bit exponent (i.e. 8 exponent bits) is taught.
PNG
media_image1.png
267
397
media_image1.png
Greyscale
)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the invention in Chen by applying the accelerating AI training with NVIDIA TF32 Tensor Cores as taught in Stosic to the processing apparatus in Chen in order to “bring[] Tensor Core acceleration to single-precision DL workloads, without needing any changes to model scripts” (Stosic, Paragraph 1 in Page 2).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Han et al. (“DEEP COMPRESSION: COMPRESSING DEEP NEURAL NETWORKS WITH PRUNING, TRAINED QUANTIZATION AND HUFFMAN CODING”) (hereinafter Han).
Regarding Claim 9,
Chen teaches:
“The processing apparatus of claim 1, further comprising” (preamble)
Chen does not explicitly teach:
“a compressor configured to compress the operation result in the third data type for storage and transfer”
Han teaches:
“a compressor configured to compress the operation result in the third data type for storage and transfer” (Han, Sectoin 1, “Our goal is to reduce the storage and energy required to run inference on such large networks so they can be deployed on mobile devices.”; Han, Section 3, “Network quantization and weight sharing further compresses the pruned network by reducing the number of bits required to represent each weight.”; Han, Section 4, “A Huffman code is an optimal prefix code commonly used for lossless data compression (Van Leeuwen, 1976). It uses variable-length codewords to encode source symbols.”; Examiner’s note: a compressor (i.e. Huffman encoder) configured to compress the operation result (i.e. each weight) in the third data type (i.e. quantized low-bit representation) for storage and transfer (i.e. reducing the storage and energy so they can be deployed on mobile devices) is taught.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the invention in Chen by applying the deep compression, compressing deep neural networks with pruning, trained quantization and Huffman coding as taught in Han to the processing apparatus in Chen in order to “reduce the storage and energy” (Han, Section 1).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Lo et al. (US 20190347553 A1) (hereinafter Lo).
Regarding Claim 10,
Chen teaches:
“The processing apparatus of claim 6,” (preamble)
Chen does not explicitly teach:
“wherein one or more of the first operator, the second operator, the first type converter, and the second type converter are configured to perform one or more of following operations: an operation that is directed to an output neuron in an inference process of the neural network, an operation that is directed to gradient propagation in a training process of the neural network, and an operation that is directed to weight updating in the training process of the neural network”
Lo teaches:
“wherein one or more of the first operator, the second operator, the first type converter, and the second type converter are configured to perform one or more of following operations: an operation that is directed to an output neuron in an inference process of the neural network, an operation that is directed to gradient propagation in a training process of the neural network, and an operation that is directed to weight updating in the training process of the neural network” (Lo, Paragraphs [0023] and [0024], “[…] forward pass and back propagation calculations are performed using a first precision and these calculations are part of dot product calculations used for the neural network training. The first precision training calculations 206 generate an output (e.g., an intermediate output) that is precision format converted by a precision format converter 208. In some examples, an integer gradient value calculated in the back propagation phase or stage using the first precision training calculations 206 is converted to a floating point value (e.g., 32-bit value) before performing additional training operations at a different phase or stage of the training process (e.g., before performing the updating of the weights). The precision converted output is then processed using second precision training calculations 210, wherein the first precision is less than the second precision. For example, calculations to update weights in the neural network are performed using the second precision as part of the neural network training.”; Examiner’s note: wherein one or more of the first operator (i.e. first precision), the second operator (i.e. second precision), the first type converter, and the second type converter (i.e. precision format converter) are configured to perform one or more of following operations: an operation that is directed to an output neuron in an inference process of the neural network (i.e. forward pass generating an output), an operation that is directed to gradient propagation in a training process of the neural network (i.e. back propagation calculations and these calculations are part of dot product calculations used for the neural network training), and an operation that is directed to weight updating in the training process of the neural network (i.e. calculations to update weights in the neural network are performed using the second precision as part of the neural network training) is taught.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention was made to modify the invention in Chen by applying the training neural networks using mixed precision computations as taught in Lo to the processing apparatus in Chen so that “processing time and processing resources needed for training the neural network are reduced” (Lo, Paragraph [0016]).
Regarding Claim 11,
The combination of Chen and Lo teaches:
“The processing apparatus of claim 10,” (preamble)
“wherein, in the inference process of the neural network and/or the training process of the neural network, the first type operation includes a multiplication operation, the second type operation includes an addition operation, and the nonlinear layer operation includes an activation operation” (Lo, Equations 1, 2 & 3 and Paragraph [0033],
PNG
media_image2.png
126
411
media_image2.png
Greyscale
“In the above equations, W is a weight, b is a bias term, σ represents non-linearity, y0 is the input, y0* is the expected output […]”; Examiner’s note: wherein, in the inference process of the neural network (i.e. forward pass) and/or the training process of the neural network (i.e. forward pass and back propagation), the first type operation includes a multiplication operation (i.e. weight x inputs in equation 1), the second type operation includes an addition operation (i.e. bias addition in equation 1), and the nonlinear layer operation includes an activation operation (i.e. σ represents non-linearity in equation 1) is taught.)
The reasons of obviousness have been noted in the rejection of Claim 10 above and applicable herein.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Neill teaches a Survey of Neural Network Compression.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YONG D RHO whose telephone number is (571)270-0194. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Viker Lamardo can be reached at 5712705871. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YONG DOO RHO/Examiner, Art Unit 2147
/VIKER A LAMARDO/Supervisory Patent Examiner, Art Unit 2147
Prosecution Insights