Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on June 26, 2025 and November 20, 2025. U.S. patents, U.S. patent application publications, and non-patent literature documents have been considered.
Specification
The specification submitted on December 30, 2023 and the amendments to the specification submitted on December 30, 2023 have been considered and accepted, with the exception of the abstract submitted on December 30, 2023.
The abstract of the disclosure is objected to because the abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (U.S. patent application publication 20140181460 A1), hereinafter referred to as Hsu, in view of Chauvel (U.S. patent 6779085 B2), hereinafter referred to as Chauvel.
Regarding claim 1, Hsu teaches An apparatus (“A data processing device” [Hsu abstract]) comprising: an input/output memory controller (Hsu the “input/output memory management unit (IOMMU)” found in paragraphs 44 and 45, which would be an input/output memory controller [see paragraph 37 of the instant application “I/O memory controller 118 (e.g., IOMMU)”]) to perform a direct memory access of a memory for an input/output device separate from a processor core; (“In a canonical case, a CPU 241, 242 may perform some work on some regions of memory 210 that brings translations of the addresses in that region into its TLB hierarchy 230. The CPU 241, 242 may also offloads some work on that memory region to one or more of the GPUs 261, 262 to perform. The GPU 261, 262 then requires the appropriate address translations in order to access the memory correctly” [Hsu paragraph 42]. This memory access by the GPU described by Hsu would be a direct memory access. The GPU 261 is an input/output device separate from a processor core [paragraph 40 of the instant application “In certain embodiments, I/O device(s) 112 include a network interface card (NIC), graphics processor unit (GPU), … “]. The IOMMU would be involved in performing the direct memory access: “the GPU TLB 250 operates in the context of an input/output memory management unit (IOMMU)” [Hsu paragraph 44]) and the processor core (Hsu CPU 241 and/or 242) comprising: the single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, (“when a GPU's translation request fails within the GPU TLB, the IOMMU may be configured to send a probe message 272 that includes both the virtual address requested and an Address Space ID (ASID), to the CPU MMU, requesting the desired translation. In the example device 200 having multiple CPUs, the probe may include the id of the CPU that launched the task for which the GPU is making the address translation request thereby directing the probe 272 to that particular CPU saving probe bandwidth. If the probe is successful, the CPU MMU can provide the translation back to the IOMMU much more quickly than the IOMMU performing a full page table walk to satisfy the GPU's address translation request” [Hsu paragraph 44]. The probe to the particular CPU would be a single instruction for that CPU to identify the virtual to physical address mapping for the I/O device in memory).
Hsu does not appear to explicitly disclose a decoder circuit to decode a single instruction into a decoded single instruction, an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, and the execution circuit to execute the decoded single instruction according to the opcode.
However, Chauvel teaches a decoder circuit to decode a single instruction into a decoded single instruction (“one of the processors may include instruction decoding” [Chauvel Col. 13 Lines 14-15]. A person having ordinary skill in the art would recognize that processor instruction decoding is done through circuitry), an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, (“Another embodiment would be to use a different processor instruction opcode for each of the TLB operation” [Chauvel Col. 12 lines 44-45]; Chauvel Table 5 “TLB Control Operation[s]” “Write TLB entry”; “one of the processors may include instruction decoding and an internal state machine(s) to perform a TLB or Cache control operation in response to executing certain instructions which may include parameters to specify the requested operation, for example” [Chauvel Col. 13 Lines 14-19]) and the execution circuit to execute the decoded single instruction according to the opcode (As cited above, “one of the processors may include instruction decoding and an internal state machine(s) to perform a TLB or Cache control operation in response to executing certain instructions which may include parameters to specify the requested operation, for example”. An internal state machine would be a circuit which executes the operation according to the instruction which has been decoded. The parameters specifying the operation would be the opcode.)
Hsu and Chauvel are analogous art because they are from the same field of endeavor of memory address translation management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Hsu and Chauvel before him or her, to modify the method of Hsu to include the attributes of the decode circuit, opcode, and execution circuit of Chauvel because it will enhance apparatus efficiency.
The motivation for doing so would be that putting the decoding and execution circuitry onto the processor would enable the processor to be able to natively perform the instruction instead relying on software to emulate the functionality.
Therefore, it would have been obvious to combine Hsu and Chauvel to obtain the invention as specified in the instant claim.
Regarding claims 9 and 17, the applicant is direct to the rejection to claim 1 above as they are rejected under the same rationale.
Regarding claim 2, the combination of Hsu/Chauvel teaches The apparatus of claim 1, wherein the opcode (“Another embodiment would be to use a different processor instruction opcode for each of the TLB operation” [Chauvel Col. 12 lines 44-45]) is to indicate the execution circuit is to cause the input/output memory controller to send a message to the input/output device that identifies the virtual address to physical address mapping (“the GPU TLB 250 operates in the context of an input/output memory management unit (IOMMU) that conducts the page table walks. In such context, when a GPU's translation request fails within the GPU TLB, the IOMMU may be configured to send a probe message 272 that includes both the virtual address requested and an Address Space ID (ASID), to the CPU MMU, requesting the desired translation. ... If the probe is successful, the CPU MMU can provide the translation back to the IOMMU much more quickly than the IOMMU performing a full page table walk to satisfy the GPU's address translation request” [Hsu paragraph 44]. Wherein satisfying the GPU’s address translation request would mean providing (sending a message to) the GPU with the address mapping).
Regarding claims 10 and 18, the applicant is direct to the rejection to claim 2 above as they are rejected under the same rationale.
Regarding claim 3, the combination of Hsu/Chauvel teaches The apparatus of claim 2, wherein the message further comprises a process address space identifier (“when a GPU's translation request fails within the GPU TLB, the IOMMU may be configured to send a probe message 272 that includes both the virtual address requested and an Address Space ID (ASID), to the CPU MMU, requesting the desired translation” [Hsu paragraph 44]).
Regarding claims 11 and 19, the applicant is direct to the rejection to claim 3 above as they are rejected under the same rationale.
Regarding claim 4, the combination of Hsu/Chauvel teaches The apparatus of claim 3, wherein the opcode is to indicate the execution circuit is to determine the process address space identifier from a process address space identifier register of the processor core (“As described previously, during execution of a program, the R-ID and Task-ID field comes from a register associated with a requester during each memory system access request” [Chauvel col. 12 lines 10-12] wherein programs are a series of computer instructions which are indicated by opcodes. Furthermore, “A task ID is provided by a task-ID register, such as task-ID register 344a associated with resource 340 and task-ID register 344n associated with resource 350” [Chauvel col. 8 lines 49-52], wherein resources 340 and 350 are processors (“processing resources (340) and processors (350)” [Chauvel abstract]) and a task-ID is a process address space identifier. Therefore, it would be obvious to a person having ordinary skill in the art to implement the functionality of the instant claim found in these processor cores into the processor core.
Regarding claims 12 and 20, the applicant is direct to the rejection to claim 4 above as they are rejected under the same rationale.
Regarding claim 5, the combination of Hsu/Chauvel teaches The apparatus of claim 1, wherein the one or more fields are to identify a device identification value of the input/output device (“FIG. 5 illustrates a TLB control word format used to operate on the TLB and .mu.TLBs of FIG. 3A in response to control operations as defined in Table 5. TLB control word format 400 includes a task-ID field 402, resource-ID field 404 and virtual address field 406” [Chauvel col. 12 lines 1-5]. Additionally, “resources can be instruction processors, coprocessors, DMA devices, etc” [Chauvel abstract]. Wherein these resources are input/output devices and the resource-ID field would thus be identifying an identification value of an input/output device. Furthermore, the GPU 261 of Hsu is one of these kinds of resources and therefore would be an input/output device identifiable by the fields of Chauvel).
Regarding claim 13, the applicant is direct to the rejection to claim 5 above as they are rejected under the same rationale.
Regarding claim 6, the combination of Hsu/Chauvel teaches The apparatus of claim 1, wherein the opcode is to indicate the execution circuit is to cause the input/output memory controller to perform a page walk of the memory to determine the virtual address to physical address mapping (“the data processing device 200 can be configured to conduct a walk of the page table 220 for the address translation requested by the GPU 261, 262 upon a condition that the address translation requested by the GPU 261, 262 was not found in the probe 272 of the CPU TLB hierarchy 230. Alternatively, the data processing device 200 can be configured to initiate a walk of the page table for the address translation requested by the GPU 261, 262 concurrently with the probe 272 of the CPU TLB hierarchy 230” [Hsu paragraph 41]. Additionally, “the GPU TLB 250 operates in the context of an input/output memory management unit (IOMMU) that conducts the page table walks” [Hsu paragraph 44]. Wherein it would be obvious to a person having ordinary skill in the art to implement this functionality as part of the execution of the instruction indicated by the opcode of Chauvel).
Regarding claim 14, the applicant is direct to the rejection to claim 6 above as they are rejected under the same rationale.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, in view of Chauvel, further in view of Patel et al. (US 10642501 B1), hereinafter referred to as Patel.
Regarding claim 7, Hsu/Chauvel teaches the apparatus of claim 6.
Hsu/Chauvel does not appear to explicitly disclose wherein the input/output device comprises a register, that when written with a value by execution of the single instruction, causes the input/output memory controller to perform the page walk.
However, Patel teaches wherein the input/output device comprises a register, that when written with a value by execution of the single instruction, causes the input/output memory controller to perform the page walk (“In an example, queued commands are dequeued and processed by IOMMU 112. These commands can be used, for example, to invalidate device related state such as a DTE (Device Table Entry), or a PTE (Page Table Entry) obtained on a page-table walk of the I/O Page Table, which are locally cached in the IOMMU” [Patel col. 12 lines 29-34]. Additionally, “FIG. 4B depicts an example of an implementation of IOMMU 112, in which data used by IOMMU 112 are located within memory embedded within IOMMU 112 (i.e, not stored in a separate general purpose memory, and referenced by a memory mapping, as in FIG. 4A). In the example of FIG. 4B, IOMMU 112 includes a TLB 128, which can be maintained by hypervisor 110 (and if a page walker is provided in IOMMU 112, then by or also by the page walker). A root device table 180 is maintained by hypervisor 110 and stores mappings between device addresses and guest information (as described above). A command register 178 can be written by hypervisor 110 and can be used to effect commands that would have been provided to a command queue as in previous examples” [Patel col. 25 lines 53-66]. The commands written to the register can include performing a page walk, as cited above).
Hsu/Chauvel and Patel are analogous art because they are from the same field of endeavor of memory address translation management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Hsu/Chauvel and Patel before him or her, to modify the apparatus of Hsu/Chauvel to include the attributes of wherein the input/output device comprises a register, that when written with a value by execution of the single instruction, causes the input/output memory controller to perform the page walk of Patel because it will enhance apparatus ease of use and performance.
The motivation for doing so would be “The disclosed aspects of hardware IOMMU virtualization allow software implementing a Hypervisor to be simplified and often provide better performance” [Patel col. 1 line 66 – col. 2 line 2].
Therefore, it would have been obvious to combine Hsu/Chauvel and Patel to obtain the invention as specified in the instant claim.
Regarding claim 15, the applicant is direct to the rejection to claim 7 above as they are rejected under the same rationale.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, in view of Chauvel, further in view of Santos et al. (US 20120017029 A1), hereinafter referred to as Santos.
Regarding claim 8, Hsu/Chauvel teaches the apparatus of claim 1, wherein the opcode is to indicate the execution circuit is to cause the input/output memory controller (see the rejection to claim 1 above).
Hsu/Chauvel does not appear to explicitly disclose to add an entry into a secure address translation service data structure of the input/output memory controller that indicates the input/output device is allowed to access the physical address in the memory.
However, Santos teaches to add an entry into a secure address translation service data structure of the input/output memory controller that indicates the input/output device is allowed to access the physical address in the memory (“Referring to FIG. 3, the IOMMU table 300 enables hardware I/O devices (e.g., the devices 108a-d of FIG. 1) to access shared VM memory pages. The driver domain 106 reserves a range of I/O addresses in the IOMMU table 300 for each of the guest domains 104a-c (that is also allocated a mapping region in the DVM virtual address space table 200) to provide address translations between the virtual addresses of the DVM virtual address space table 200 and machine physical memory addresses of the guest domains 104a-c (i.e., guest addresses). The IOMMU table 300 protects against improper memory accesses from hardware I/O devices by ensuring that each memory access request from a hardware device provides a memory address for which a valid translation exists in the IOMMU table 300” [Santos paragraph 25]. Wherein IOMMU table 300 is an address translation service data structure that provides security, reserving a range of addresses in the table is synonymous with adding entries to the table, and the cited functionality can be implemented as execution circuitry (“Additionally, any or all of the example processes of FIGS. 7-9 may be performed sequentially and/or in parallel by, for example, separate processing threads, processors, devices, discrete logic, circuits, etc.” [Santos paragraph 42])).
Hsu/Chauvel and Patel are analogous art because they are from the same field of endeavor of memory address translation management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Hsu/Chauvel and Santos before him or her, to modify the apparatus of Hsu/Chauvel to include the to add an entry into a secure address translation service data structure of the input/output memory controller that indicates the input/output device is allowed to access the physical address in the memory of Santos because it will enhance apparatus security.
The motivation for doing so would be “An IOMMU provides address translation for hardware I/O devices so that all DMA memory accesses from such hardware I/O devices undergo address translation using an I/O page table (or IOMMU table). An IOMMU protects memory against improper I/O device accesses by ensuring that a valid address translation exists in the IOMMU table for each DMA request. In this manner, IOMMU tables can be used to protect against incorrect or malicious memory accesses from I/O devices to address spaces that are not shared and, thus, not translated in the IOMMU tables” [Santos paragraph 17].
Regarding claim 16, the applicant is direct to the rejection to claim 8 above as they are rejected under the same rationale.
Response to Arguments
Examiner thanks the applicant for their remarks of November 19, 2025. The remarks have been accepted and fully considered, but they are not persuasive.
Regarding the objection to the specification, applicant writes on page 6 of their remarks, “The abstract is a brief narrative of the disclosure as a whole and is as concise as the disclosure permits”. This is not persuasive as the abstract does not meet the following requirements: it must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b) “A brief abstract of the technical disclosure in the specification must commence on a separate sheet, preferably following the claims, under the heading "Abstract" or "Abstract of the Disclosure." The sheet or sheets presenting the abstract may not include other parts of the application or other material”.
On page 6 of their remarks, applicant recites “The cited portions of the references do not teach or suggest the Applicant's claims. For example, in reference to Hsu of the alleged combination, pages 4-5 of the Office action allege "The probe to the particular CPU would be a single instruction for that CPU to identify the virtual to physical address mapping for the I/O device in memory"(emphasis added). If this is Official notice, the Applicant hereby traverses it as not "capable of instant and unquestionable demonstration as being well-known" and thus improper (see, e.g., MPEP §2144.03).”
The 103 rejection to the claims is based upon the broadest reasonable interpretation (hereinafter BRI) of the claims. The BRI of “instruction” includes the plain language meaning of “a direction or order”, with which the term “probe”, in the context of Hsu, is synonymous. Therefore a probe as described in Hsu could be considered a single instruction, rendering the claimed limitation obvious.
On pages 6-7 of their remarks, applicant recites “Further, there is no teaching or suggestion in Hsu of the alleged combination of any specific instruction, let alone a "single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, and an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device" as recited, inter alia, in Applicant's independent claim 1.
The examiner disagrees that Hsu does not teach or suggest “single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory”, and Hsu is not solely relied on for the claimed limitation “an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device”. As cited in the rejection to claim 1 above, Hsu teaches that the probe “includes both the virtual address requested and an Address Space ID … requesting the desired translation” and “If the probe is successful, the CPU MMU can provide the translation back to the IOMMU”. These would comprise fields to identify a virtual to physical address mapping for the input/output device in the memory, as claimed. This is analogous to figs. 4 and 5 of the instant application which show the instruction having an “operand of the virtual address” (a field) that is used to fetch and return the translated address. Additionally, the rejection to claim 1 above is based on the teachings of the combination of Chauvel with Hsu, so it is moot whether Hsu individually teaches the opcode or its related elements. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 7 of their remarks, applicant recites “In sharp contrast, paragraph [0017] of Hsu of the alleged combination merely discusses "In addition, another embodiment provides a non-transitory computer-readable storage medium storing a set of instructions for execution by a general purpose computer to facilitate manufacture of a selectively designed integrated circuit"”
This remark is moot because this portion of Hsu discusses the manufacturing process to create the apparatus of Hsu, rather than any functions or features of the apparatus pertinent to the claimed invention.
On page 7 of their remarks applicant recites “Figure 3A of Chauvel of the alleged combination (reproduced below) illustrates micro-TLBs (pTLBs) 310(0)-310(m) and shared TLB 300 separate from "resource 340". In sharp contrast, Applicant's independent claim 1 recites, inter alia, "an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device"”
The rejection to claim 1 is based upon the combined teachings of Hsu and Chauvel (for example in “it would have been obvious to one of ordinary skill in the art, having the teachings of Hsu and Chauvel before him or her, to modify the method of Hsu to include the attributes of the decode circuit, opcode, and execution circuit of Chauvel because it will enhance apparatus efficiency. The motivation for doing so would be that putting the decoding and execution circuitry onto the processor would enable the processor to be able to natively perform the instruction instead”). The cited portions of Chauvel include teachings such as “to use a different processor instruction opcode for each of the TLB operation”, including opcodes for writing to TLBs, and executing instructions based on the parameters indicating the operation (i.e., the opcode), which would suggest to a person having ordinary skill in the art to implement opcodes for TLB operations. In combination with the cited portions of Hsu which teach providing address translations to an input/output device when they are missing in the input/output device’s TLB, it would have been obvious to a person having ordinary skill in the art that in view of other prior art (Chauvel) containing suggestions to implement opcodes for writing to TLBs, to implement an opcode for Hsu’s method of sending address translations to input/output devices with TLBs (which a person having ordinary skill in the art would recognize that TLBs exist for the purpose of storing address translations, especially in light of the teachings of Hsu and Chauvel), including storing the opcode in the input/output device’s TLB.
Applicant’s remarks on pages 8-9 are addressed by the examiner’s response above and are not persuasive under the same rationale. The examiner disagrees that no prima facie case of obviousness was made (see the response above). The argument that the dependent claims would be allowable based on the alleged allowability of the independent claims is moot as the examiner disagrees that the independent claims are allowable (see above).
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130031333 A1 - Sankaran et al.
Relevant excerpt: “Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries” [Abstract]. Additionally, Fig. 2
US 20170031835 A1 - Serebrin
Relevant excerpt: “Peripheral Component Interconnect Express (PCIe) address translation services (ATS) allows a device to request an address translation from an IOMMU and cache the translation locally on the device, e.g., in a translation lookaside buffer (TLB).” [Paragraph 3]
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTIAN O’CONNELL whose telephone number is (571)270-7784. The examiner can normally be reached on Monday-Friday 9:30 AM - 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138