DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-6, 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chodavarapu (U.S. Publication No. 2007/0138028) in view of Ayele (U.S. Publication No. 2018/0372679).
Regarding claim 1, Chodavarapu teaches a differential pH sensor, comprising (a pH sensor; abstract): a first ion-sensitive transistor “IST’-operational-transconductance-amplifier “PIOTA” comprising (a first IOTA 13A; figure 1, paragraphs [0024], [0026)): a first p-channel IST disposed in a first n-type substrate region (a p-channel IST 22 of IOTA 13A (first IST) disposed in a substrate which would be n-channel; figures 3, 7, paragraphs [0025], [0033], [0045]); and a first n-channel load transistor having a source and a drain (a n-channel load transistor 25 of OTA 13A (first load transistor) having a source and drain; figures 1, 3, paragraphs [0025], [0033]), wherein the first n-channel load transistor has a first drain-to-source resistance “Rds"(the n-channel load transistor 25 of [OTA 13A having a first Rds; claim 1 of CHODAVARAPU), and wherein the drain of the first n-channel load resistor is electrically connected to a drain of the first p-channel IST (the drain of the n-channel load transistor 25 is coupled to drain of p-channel IST 22; figures 1, 3, claim 1 of CHODAVARAPU); a second PIOTA comprising (a first OTA 13B; figure 1, paragraphs [0024], [0026]): a second p-channel IST disposed in a second n-type substrate region (a p-channel IST 22 of IOTA 13B (second IST) in a substrate which would be n-channel; figures 3, 7, paragraphs {0025}, [0033}, [0045}; figure 1, paragraph [0025]); and a second n-channel load transistor having a source and a drain, and wherein the second n-channel load transistor has a second Rds which is different from the first Rds (a n-channel load transistor 25 of IOTA 13B (second load "| transistor) having a source and drain and has a second Rds different from the first Rds: figure 1, paragraph [0025]), and wherein the drain of the second n-channel load resistor is electrically connected to a drain of the second p-channel IST (the drain of the n-channel load transistor 25 is coupled to drain of p-channel IST 22; figure 1, claim 1 of CHODAVARAPU); a differential sensor having a differential sensor output configured to provide a voltage indicative of a difference in potential between an output of the first PLOTA and an output of the second PIOTA (a differential sensor 19 having a differential sensor output 40 to provide a voltage indicative of a difference in potential between an output of the IOTA 13A and 138; figure 1, paragraphs [0029], [0030], claim 1 of CHODAVARAPU). Chodavarapu teaches the salient features of the claimed invention except the IST configured to receive a control voltage for controlling a sensitivity of the IST. Ayele discloses the IST configured to receive a control voltage for controlling a sensitivity of the IST (an ISFET configured to receive a gate voltage to control the sensitivity of the ISFET; paragraph [0023], claim 1 of Ayele). It would have been obvious to one of ordinary skill in the art, at the time of the invention, to modify the sensor of CHODAVARAPU to implement the IST configured to receive a control voltage for controlling a sensitivity of the IST, as taught by Ayele, in order to vary sensitivity levels based on applications, enhancing the efficacy of the sensor. Although only a single ISFET is disclosed in Ayele, it is obvious to use the technique across both ISTs in CHODAVARAPU to enhance the efficacy of the sensor.
Regarding claim 5, CHODAVARAPU in view of Ayele discloses the sensor of claim 1. Modified CHODAVARAPU discloses wherein the first PIOTA further comprises an amplifier wherein the input of the amplifier is electrically connected to the drain of the first p-channel IST and drain of the first n-channel load transistor, and wherein an output of the amplifier is the first PIOTA output (the IOTA 13A comprises an amplifier 28 whose input is coupled to the drain of the IST 22 and the drain of the load transistor 25 and whose output is the OTA 13A’s output 31; figures 1, 3, paragraph [0026)).
Regarding claim 6, modified CHODAVARAPU discloses wherein the second PIOTA further comprises an amplifier wherein the input of the amplifier is electrically connected to the drain of the second p-channel IST and the drain of the second n-channel load transistor, and wherein an output of the amplifier is the second PIOTA output (the IOTA 13B comprises an amplifier 28 whose input is coupled to the drain of the IST 22 and the drain of the load transistor 25 and whose output is the IOTA 13B’s output 31; figures 1, 3, paragraph [0026]).
Regarding claim 8, CHODAVARAPU discloses a p-channel ion-sensitive transistor “IST"-operational-transconductance-amplifier. “PIOTA" having adjustable sensitivity, comprising (a IOTA 13A comprising a p-channel IST; abstract, paragraphs [0025]-[0027]): a p-channel IST . disposed in a first n-type substrate region (a p-channel IST 22 of IOTA 13A (first IST) disposed in a substrate which would be n-channel; figures 3, 7, paragraphs [0025], [0033], [0045]); and an n-channel load transistor having a source and a drain (a n-channel load transistor 25 of IOTA 134 (first load transistor) having a source and drain; figures 1, 3, paragraphs [0025], [0033]), wherein the n-channel load transistor has a drain-to-source resistance “Rds"(the n-channel load transistor 25 of IOTA 13A having a first Rds; claim 1 of ‘| CHODAVARAPU), and wherein the drain of the n-channel load resistor is electrically connected to a drain of the p-channel IST (the drain of the n-channel load transistor 25 is coupled to drain of p-channel IST 22: figures 1, 3, claim 1 of CHODAVARAPU); an amplifier wherein the input of the amplifier is electrically connected to the drain of the p-channel IST and drain of the n-channel load transistor, (an amplifier 28 whose input is coupled to the drain of the IST 22 and the drain of the load transistor 25; figures 1, 3, paragraph [0026]), and having an output configured to provide a voltage which varies based on a pH of a sample (and whose output is the IOTA 13A's output 31 provides a voltage which varies based on a pH of a sample; figures 1, 3, paragraph [0026], [0050]). CHODAVARAPU fails to disclose the IST configured to receive a control voltage for controlling a sensitivity of the IST. STM discloses the IST configured to receive a control voltage for controlling a sensitivity of the IST (an ISFET configured to receive a gate voltage to control the sensitivity of the ISFET; paragraph [0023), claim 1 of Ayele). It would have been obvious to one of ordinary skill in the art, at the time of the invention, to modify the sensor of CHODAVARAPU to implement the IST configured to receive a control voltage for controlling a sensitivity of the IST, as taught by Ayele, in order to vary sensitivity levels based on applications, enhancing the efficacy of the sensor.
Regarding claim 12, CHODAVARAPU discloses a pH sensor integrated circuit "IC" or "chip", comprising (a pH sensors on a single integrated chip; abstract, paragraph [0041)): a first ion-sensitive transistor “IST’-operational-transconductance-amplifier "PIOTA” comprising (a first IOTA 13A; figure 1, paragraphs [0024], [0026]): a first p-channel IST with a drain region, wherein the first p-channel IST is disposed in a first n-type substrate region (a p-channel IST 22 of IOTA 13A (first IST) with a drain and disposed in a substrate which would be n-channel; figures 3, 7, paragraphs [0025], [0033], [(0045]): and a first n-channel load transistor including a source region, a drain region, and a - channel region, the channel region electrically connecting the source region and the drain region, and wherein the first n-channel load transistor has a first drain-to-source resistance “Rds” (an n-channel load transistor 25 of IOTA 13A (first load transistor) having a source, channel and drain, the channel connecting the source and drain and the n-channel load transistor 25 has a first Rds; figures 1, 3, paragraphs [0025], [0033], claim 1 of CHODAVARAPU); wherein the drain region of the first p-channel IST is electrically connected to the drain region of the first n-channel load transistor (the drain of the n-channel load transistor 25 is coupled to drain of p-channel IST 22; figures 1, 3, claim 1 of CHODAVARAPU); a second PIOTA comprising (a second [OTA 13B; figure 1, paragraphs [0024], [0026]): a second p-channel IST with a drain region, wherein the second p-channel IST is disposed in a second n-type substrate region (a p-channel IST 22 of IOTA 13B (second IST) with a drain and disposed in a substrate which would be n-channel; figures 3, 7, paragraphs [0025], [0033], [0045]); and a second n-channel load transistor including a source region, a drain region and a channel region, the channel region electrically connecting the source region and the drain region, and wherein the second n-channel load transistor has a second Rds which is different from the first Rds (an n-channel load transistor 25 of IOTA-13B (second load transistor) having a source, channel and drain, the channel connecting the source and drain and the n-channel load transistor 25 has a second Rds different from the first Rds; figures 1, 3, paragraphs [0025], [0033], claim 1 of CHODAVARAPU); wherein the drain region of the second p-channel IST is electrically connected to the drain region of the second n-channel load transistor (drain of the n-channel load transistor 25 is coupled to drain of p-channe] IST 22; figures 1, 3, claim 1 of CHODAVARAPU); a differential sensor comprising: a first input connected to an output of the first PIOTA (a differential sensor 19 with first input coupled to the output 31 of IOTA 13A; figure 1, paragraphs [0029], [0030], claim 1 of ; CHODAVARAPU); a second input connected to an output of the second PIOTA (second input coupled to the output 31 of IOTA 13B; figure 1, paragraphs [0029], [0030], claim 1 of CHODAVARAPU); and a differential sensor output configured to provide a voltage indicative of a difference in potential between the first input and the second input (a differential sensor output 40 configured to provide a voltage indicative of a difference in potential between the first and second input; figure 1, paragraphs [0029], [0030], claim 1 of CHODAVARAPU). CHODAVARAPU fails to disclose the IST configured to receive a control voltage for controlling a sensitivity of the IST. STM discloses the IST configured to receive a control voltage for controlling a sensitivity of the IST (an ISFET configured to receive a gate voltage to control the sensitivity of the ISFET; paragraph [0023], claim 14 of Ayele). It would have been obvious to one of ordinary skill in the art, at the time of the invention, to modify the sensor of CHODAVARAPU to implement the IST configured to receive a control voltage for controlling a sensitivity of the IST, as taught by Ayele, in order to vary sensitivity levels based on applications, enhancing the efficacy of the sensor. Although only a single ISFET is disclosed in Ayele, it is obvious to use the technique across both ISTs in CHODAVARAPU to enhance the efficacy of the sensor.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chodavarapu (U.S. Publication No. 2007/0138028) in view of Ayele (U.S. Publication No. 2018/0372679) and further in view of Fife (U.S. Publication No. 2012/0168784). Chodavarapu as modified teaches the first PIOTA, the second PIOTA, and the differential sensor (the IOTA 13A, IOTA 13B and differential sensor 19; figure 1, paragraphs [0024]-[0026}), the IC (single integrated circuit; paragraph [0041]). CHODAVARAPU teaches the salient features of the claimed invention except for the transistors and the sensor make up a pixel, and the IC comprises a plurality of such pixels. FIFE discloses the transistors and the sensor make up a pixel, and the IC comprises a plurality of such pixels (the transistors which are part of the sensor make up a pixel and the system comprises a pixel array; paragraphs [0043], (0127}-[0136]). It would have been obvious to-one of ordinary skill in the art, at the time of the invention, to modify the sensor of CHODAVARAPU to implement the transistors and the sensor make up-a pixel, and the IC comprises a plurality of such pixels, as taught by FIFE, in order to enhance the industrial applicability of the IC.
Regarding claim 17, CHODAVARAPU in view of Ayele and FIFE disclose the IC of claim 16. CHODAVARAPU teaches the salient features of the claimed invention except for the plurality of pixels are arranged as an array. FIFE discloses the plurality of pixels are arranged as an array (the pixels form an array; paragraphs [0043], [0127]-[0136]). It would have been obvious to one of ordinary skill in the art, at the time of the invention, to modify the sensor of CHODAVARAPU to include the plurality of pixels arranged as an array, as taught by FIFE, in order to enhance the industrial applicability of the IC.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chodavarapu (U.S. Publication No. 2007/0138028) in view of Ayele (U.S. Publication No. 2018/0372679) and Fife (U.S. Publication No. 2012/0168784), and further in view of Ui (U.S. Publication No. 2010/0013969). Chodavarapu as modified teaches the salient features of the claimed invention except for wherein each pixel of the plurality-of pixels is configured to have a sensitivity different from a sensitivity of at least one of the other pixels of the plurality of pixels. Ui discloses wherein each pixel of the plurality of pixels is configured to have a sensitivity different from a sensitivity of at least one of the other pixels of the plurality of pixels (the optical sensitivity of the pixels are different from each other pixel in a different region; claim 1 of Ui). It would have been obvious to one of ordinary skill in the art, at the time of the invention, to modify the sensor of CHODAVARAPU to provide pixels having a sensitivity different from a sensitivity of at least one of the other pixels of the plurality of pixels, as taught by Ui, in order to enhance the industrial applicability of the IC.
Allowable Subject Matter
Claims 10-11 are allowed.
Claims 2-4, 7, 9, 13-15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed January 27, 2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The applicant argues that there is no suggestion for incorporating the biasing taught by Ayele in to the FETs of Chodavarapu. The reasoning put forth by the applicant is that Ayele is directed to sensitivity enhancement in a dual gate ISFET which comprises a silicon on insulator and not a PIOTA with a p channel IST disposed in an n-type substrate. Chodavarapu is used to teach a PIOTA with a p channel IST disposed in an n-type substrate. Ayele is relied upon to teach that it was known to apply a bias voltage to the gate of a FET used to detect PH. One of ordinary skill in the art would not try to bodily incorporate a dual bias system from a silicon on insulator FET. However, one of ordinary skill in the art of FET design can and would take the teaching of Ayele, biasing the gate to improve sensitivity, and apply it to any FET. In this case the FETs of Chodavarapu, which are not biased, can be biased at the gates as taught by Ayele. If one FET can be biased, each FET of Chodavarapu may be biased depending on desired sensitivity.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER E MAHONEY/ Primary Examiner, Art Unit 2852