DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8 and 20 objected to because of the following informalities:
Claim 8 recites the limitation "the same length" in line 2. There is insufficient antecedent basis for this limitation in the claim. The Examiner reads claim 8 as with “[[a same length”.
Claim 20 recites the limitation "the same length" in line 3. There is insufficient antecedent basis for this limitation in the claim. The Examiner reads claim 20 as with “[[a same length”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 11-13, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fastow et al., US 2020/0395328 (corresponding to US 10,923,450).
In r e Claim 1, Fastow discloses a memory device (Fig. 4) comprising: a first substrate structure 408 including a plurality of sense amplifiers (S/A) 418 ([0071]) and a peripheral circuit unit 415; a second substrate structure 404a bonded to a first (upper) surface side of the first substrate structure 408 and including a first cell block 418 including a plurality of first memory cells 456a and a plurality of first bit lines 464a; and a third substrate structure 404b bonded to a second (bottom) surface side of the first substrate structure 408 and including a second cell block including a plurality of second memory cells 456b and a plurality of second bit lines 464b, wherein each of the plurality of first bit lines 464a and each of the plurality of second bit lines 464b are commonly connected to each of the plurality of sense amplifiers (S/A) 418 (Figs. 1-8; [0024 – 0141]).
In re Claim 4, Fastow discloses the memory device of Claim 1, wherein at least some of the plurality of sense amplifiers (S/A) 418 are arranged to be adjacent to each other in a first (horizontal) direction, wherein at least some of the plurality of first bit lines 464a and at least some of the plurality of second bit lines 464b corresponding thereto are arranged to be spaced apart from each other or to be adjacent to each other in a second (vertical) direction perpendicular to the first (horizontal) direction when observed from above (Fig. 4).
In re Claim 11, Fastow discloses the memory device of claim 1, wherein the memory device is a three-dimensional stacked memory device ([109]).
In r e Claim 12, Fastow discloses the memory device of claim 1, wherein the memory device is a three-dimensional stacked DRAM device ([0026], [0109]).
In re Claim 13, Fastow discloses a manufacturing method of a memory device comprising: preparing a first substrate structure 408 including a plurality of sense amplifiers (S/A) 418 ([0071]) and a peripheral circuit unit 415; bonding a second substrate structure 404a including a first cell block 418 including a plurality of first memory cells 456a and a plurality of first bit lines 464a to a first (top) surface side of the first substrate structure 408; and bonding a third substrate structure 404b including a second cell block including a plurality of second memory cells 456b and a plurality of second bit lines to a second surface side of the first substrate structure, wherein each of the plurality of first bit lines 464b and each of the plurality of second bit lines are commonly connected to each of the plurality of sense amplifiers (S/A) 418 (Figs. 1-8; [0024-0141]).
In re Claim 15, Fastow discloses the manufacturing method of a memory device of wherein at least some of the plurality of sense amplifiers (S/A) 418 are arranged to be adjacent to each other in a first (horizontal) direction, wherein at least some of the plurality of first bit lines 464a and at least some of the plurality of second bit lines 464b corresponding thereto are arranged to be spaced apart from each other or to be adjacent to each other in a second (vertical) direction perpendicular to the first (horizontal) direction when observed from above (Fig. 4).
In re Claim 18, Fastow discloses the manufacturing method of a memory device of claim 13, wherein the first substrate structure 408 is a first wafer structure, the second substrate structure 404a is a second wafer structure, and the third substrate structure 404b is a third wafer structure (Figs. 1-8; [0024, [0109]).
In re Claim 19, Fastow discloses the manufacturing method of a memory device of claim 13, wherein the memory device is a three- dimensional stacked memory device ([0024, [0109]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Fastow as applied to claim 1 above.
In re Claim 2, Fastow discloses all limitations of Claim 2 including that at least some of the plurality of sense amplifiers (S/A) 418 are arranged to be adjacent to each other in a first (horizontal) direction, wherein at least some of the plurality of first bit lines 464a and at least some of the plurality of second bit lines 464b (Fig. 4), except for that at least some of the plurality of first bit lines 464a and at least some of the plurality of second bit lines 464b corresponding thereto are arranged alternately along the first (horizontal) direction when observed from above.
The difference between the Applicant’s Claim 2 and Fastow’s memory device is in the specified arrangement of the bit lines. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to arrange alternately along the first (horizontal) direction when observed from above, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (MPEP2144.04.VI. C).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow as applied to claim 1 above.
In re Claim 6, Fastow discloses all limitations of Claim 4 including that each of at least some of the plurality of first bit lines 464a and each of at least some of the plurality of second bit lines 464b (Fig. 4), except for that the pluralities are arranged so that their positions coincide with each other when observed from above. The difference between the Applicant’s Claim 6 and Fastow’s reference is in the specified arrangement of the first bit lines 464a and each of at least some of the plurality of second bit lines 464b. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to arrange the plurality so that their positions coincide with each other when observed from above, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (MPEP2144.04.VI. C)
In re Claim 7, Fastow discloses all limitations of Claim 7 including that each of at least some of the plurality of first memory cells 456a and each of at least some of the plurality of second memory cells 456b corresponding thereto, except for that at least some of the plurality of first memory cells 456a and each of at least some of the plurality of second memory cells 456b corresponding thereto are arranged so that their positions coincide with each other when observed from above.
The difference between the Applicant’s Claim 7 and Fastow’s reference is in the specified arrangement of the memory calls. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to arrange the memory cells so that their positions coincide with each other when observed from abo, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (MPEP2144.04.VI. C)
In re Claim 8, Fastow discloses all limitations of Claim 8 except for that the first bit line 464a and the second bit line 464b commonly connected to one sense amplifier (S/A) 408 have [[a same length. It is known in the art that the length the line is a result effective variable – because its mass depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the bit line 464a and 464b of [[a same length, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
In re Claim 9, Fastow discloses all limitations of Claim 9 except for that a length of a connection wiring 455a from the first bit line 464a to the sense amplifier (S/A) 408 is same as a length of a connection wiring 455b from the second bit line 464b to the sense amplifier (S/A) 408. It is known in the art that the length of the wiring is a result effective variable – because its mass depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use length of a connection wiring 455a from the first bit line 464a to the sense amplifier (S/A) 408 is same as a length of a connection wiring 455b from the second bit line 464b to the sense amplifier (S/A) 408, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
In re Claim 14, Fastow discloses all limitations of Claim 14 including that at least some of the plurality of sense amplifiers (S/A) 418 are arranged to be adjacent to each other in a first (horizontal) direction, wherein at least some of the plurality of first bit lines 464a and at least some of the plurality of second bit lines 464, except for that at least some of the plurality of first bit lines 464a and at least some of the plurality of second bit lines 464b corresponding thereto are arranged alternately along the first (horizontal) direction when observed from above.
The difference between the Applicant’s Claim 14 and Fastow’s memory device is in the specified arrangement of the bit lines. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to arrange alternately along the first (horizontal) direction when observed from above, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (MPEP2144.04.VI. C).
In re Claim 16, Fastow discloses all limitations of Claim 16 including that each of at least some of the plurality of first bit lines 464a and each of at least some of the plurality of second bit lines 464b corresponding thereto are arranged (Fig. 4), except for that their positions coincide with each other when observed from above. The difference between the Applicant’s Claim 16 and Fastow’s reference is in the specified arrangement of the first bit lines 464a and each of at least some of the plurality of second bit lines 464b. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to arrange the plurality so that their positions coincide with each other when observed from above, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 (MPEP2144.04.VI. C).
In re Claim 20, Fastow discloses all limitations of Claim 20 except for that the first bit line 464a and the second bit line 464b commonly connected to one sense amplifier (S/A) 418 have [[a same length.
Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the bit line 464a and 464b of [[a same length, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
Allowable Subject Matter
Claims 3, 5, 10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 3: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 3 as: “at least some of the plurality of second memory cells are arranged to be shifted by a given distance in the first direction or in a reverse direction”, in combination with limitations of Claims 1 and 2 on which it depends.
In re Claim 5: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 3 as: “at least some of the plurality of second memory cells are arranged to be shifted by a given distance in the second direction or in a reverse direction thereof with respect to at least some of the plurality of first memory cells corresponding thereto”, in combination with limitations of Claims 1 and 4 on which it depends.
In re Claim 10: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 10 as: “the plurality of first bit lines are respectively in contact with the plurality of first contact pads, and the plurality of second bit lines are respectively in contact with the plurality of second contact pads”, in combination with limitations of Claim 1 on which it depends.
In re Claim 17: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 17 as: “the plurality of first bit lines are respectively in contact with the plurality of first contact pads, and the plurality of second bit lines are respectively in contact with the plurality of second contact pads”, in combination with limitations of Claim 13 on which it depends.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893
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