DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2013/0258599 Danello et al.
1. Referring to claim 1, Danello et al. teaches a wafer assembly comprising: a cooling system, (Figure 2F #20); a wafer, (Figure 2F #12); a first electronic module, (Figure 2F #14b), mounted on a first location of the wafer, (Figure 2F #12), and coupled to a first portion of the cooling system, (Figure 2F #20), the first electronic module, (Figure 2F #14b), and the first portion of the cooling system, (Figure 2F #20), positioned such that a first thermal interface material (TIM) , (Figure 2F #60), is disposed between the first electronic module, (Figure 2F #14b), and the first portion of the cooling system, (Figure 2F #20); a second electronic module, (Figure 2F #14d), mounted on a second location of the wafer, (Figure 2F #12), different from the first location and coupled to a second portion of the cooling system, (Figure 2F #20), the second electronic module, (Figure 2F #14d), and the second portion of the cooling system, (Figure 2F #20), positioned such that a second TIM, (Figure 2F #60), is disposed between the second electronic module, (Figure 2F #14d), and the second portion of the cooling system, (Figure 2F #20); and a height adjustment structure, (Figure 2F #62), disposed between the first location of the wafer and the first portion of the cooling system, (Figure 2F area of #14b), the height adjustment structure configured to compensate for a height difference between the first electronic module, (Figure 2F #14b), and the second electronic module, (Figure 2F #14d).
2. Referring to claim 3, Danello et al. teaches a wafer assembly of Claim 1, the height adjustment structure comprises a crown, (Figure 2F #62), disposed on the first electronic module, (Figure 2F #14b).
3. Referring to claim 5, Danello et al. teaches a wafer assembly of Claim 1, further comprising a second height adjustment structure, (Figure 2F #62 in the area of #14d), disposed between the second location of the wafer, (Figure 2F #12), and the second portion of the cooling system, (Figure 2F #20), wherein a height of the second height adjustment structure, (Figure 2F #62 in the area of #14d), is different from a height of the first height adjustment structure, (Figure 2F #62 in the area of #14b).
4. Referring to claim 6, Danello et al. teaches a wafer assembly of Claim 1, wherein the height adjustment structure comprises part of the first TIM, (Figure 2F #60 in the area of #14b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2013/0258599 Danello et al.
5. Referring to claim 2, Danello et al. teaches a wafer assembly of Claim 1, nut is silent to wherein the first electronic module is a voltage regulating module (VRM). Danello et al. teaches the devices to be low noise amplifiers, logic circuits, drain modulators, and power amplifiers. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to change an electrical component to a VRM due to the design restrains that are needed for the design layout of the total package that the market share desires, thereby increasing marketability and production, and also since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
In re Leshin, 125 USPQ 416.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent No. 6,665,187 Alcoe et al.
6. Referring to claim 1, Alcoe et al. teaches a wafer assembly comprising: a cooling system, (Figure 2 #155); a wafer, (Figure 2 #102); a first electronic module, (Figure 2 #105a), mounted on a first location of the wafer, (Figure 2 #102), and coupled to a first portion of the cooling system, (Figure 2 #155), the first electronic module, (Figure 2 #105a), and the first portion of the cooling system, (Figure 2 #155), positioned such that a first thermal interface material (TIM) , (Figure 2 #170), is disposed between the first electronic module, (Figure 2 #105a), and the first portion of the cooling system, (Figure 2 #155); a second electronic module, (Figure 2 #105b), mounted on a second location of the wafer, (Figure 2 #102), different from the first location and coupled to a second portion of the cooling system, (Figure 2 #155), the second electronic module, (Figure 2 #105a), and the second portion of the cooling system, (Figure 2 #155), positioned such that a second TIM, (Figure 2 #170), is disposed between the second electronic module, (Figure 2 #105b), and the second portion of the cooling system, (Figure 2 #155); and a height adjustment structure, (Figure 2 #180), disposed between the first location of the wafer, (Figure 2 #102), and the first portion of the cooling system, (Figure 2 #155), the height adjustment structure, (Figure 2 #180), configured to compensate for a height difference between the first electronic module, (Figure 2 #105a), and the second electronic module, (Figure 2 #105b).
7. Referring to claim 3, Alcoe et al. teaches a wafer assembly of Claim 1, the height adjustment structure comprises a crown, (Figure 2 #180), disposed on the first electronic module, (Figure 2 #105a).
8. Referring to claim 4, Alcoe et al. teaches a wafer assembly of Claim 1, wherein the height adjustment structure comprises a protrusion, (Figure 2 #180), extending from the first portion of the cooling system, (Figure 2 #155).
9. Referring to claim 5, Alcoe et al. teaches a wafer assembly of Claim 1, further comprising a second height adjustment structure, (Figure 2 #185), disposed between the second location of the wafer, (Figure 2 #102), and the second portion of the cooling system, (Figure 2 #155), wherein a height of the second height adjustment structure, (Figure 2 #185), is different from a height of the first height adjustment structure, (Figure 2 #180).
10. Referring to claim 6, Alcoe et al. teaches a wafer assembly of Claim 1, wherein the height adjustment structure comprises part of the first TIM, (Figure 2 #170).
11. Referring to claim 7, Alcoe et al. teaches a wafer assembly of Claim 1, further comprising a heat dissipation structure positioned such that the wafer is located between the cooling system and the heat dissipation
structure, (Figure 2 #120 has the ability to dissipate some heat through the solder balls and electrical traces in the PCB).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 6,665,187 Alcoe et al.
12. Referring to claim 2, Alcoe et al. teaches a wafer assembly of Claim 1, but is silent to wherein the first electronic module is a voltage regulating module (VRM). Alcoe et al. teaches the devices to be a broader range that includes electrical components and not further limited to a VRM. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to change an electrical component to a VRM due to the design restrains that are needed for the design layout of the total package that the market share desires, thereby increasing marketability and production, and also since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
In re Leshin, 125 USPQ 416.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
13. The prior art, (U.S. Patent Application Publication No. 2013/0258599 and U.S. Patent No. 6,665,187), teaches a wafer assembly comprising: a cooling system; a wafer; a first electronic module mounted on a first location of the wafer and coupled to a first portion of the cooling system, the first electronic module and the first portion of the cooling system positioned such that a first thermal interface material (TIM) is disposed between the first electronic module and the first portion of the cooling system; a second electronic module mounted on a second location of the wafer different from the first location and coupled to a second portion of the cooling system, the second electronic module and the second portion of the cooling system positioned such that a second TIM is disposed between the second electronic module and the second portion of the cooling system; and a height adjustment structure disposed between the first location of the wafer and the first portion of the cooling system, the height adjustment structure configured to compensate for a height difference between the first electronic module and the second electronic module, but is silent to the combination of a wafer assembly comprising: a wafer having a center region and an edge region around the center region; a plurality of electronic modules having different heights mounted on the wafer
such that an average height of a first group of electronic modules of the plurality of electronic modules located within the center region is greater than an average height of a second group of electronic modules of the plurality of electronic modules located within the edge region; and
a cooling system coupled to the plurality of electronic modules, the cooling system and the plurality of electronic modules positioned such that a thermal interface material (TIM) is disposed between the cooling system and the plurality of electronic modules, wherein the wafer is curved such that the edge region of the wafer is closer to the cooling system than the center region of the wafer.
14. The prior art, (U.S. Patent Application Publication No. 2020/0329551), teaches a method of manufacturing wafer assemblies, the method comprising: selecting a first group of electronic modules having different heights and placing a heat sink on the first group of electronic modules that can absorb the height differences but a fixing member, but the prior art is silent to the combination of selecting a first group of electronic modules and a second group of electronic modules from a plurality of electronic modules such that a height variation of the first group of electronic modules and a height variation of the second group of electronic modules are both less than a height variation of the plurality of electronic modules; mounting the first group of electronic modules on a first wafer and the second group of electronic modules on a second wafer; coupling a first cooling system and the first group of electronic modules such that a first thermal interface material is positioned between the first cooling system and the first group of electronic modules; and coupling a second cooling system and the second group of electronic modules such that a second thermal interface material is positioned between the second cooling system and the second group of electronic modules.
15. These combinations have been found to not be anticipated or render obvious over the prior art, hence claims 8-20 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 5/21/26
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