DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 14, 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jalili et al, Reducing Load Latency with Cache Level Prediction, ARXIV.ORG, Cornell University Library Ithaca, NY 14853, 03-27-2021 (hereafter referred to as Jalili) in view of Al Sheikh et al. (US PGPub 2019/0065375, hereafter referred to as Al Sheikh).
Regarding claim 1, Jalili teaches a processing system, comprising: two or more cache levels, each cache level including miss status holding registers (pg. 2 Section II, states that there is a multi-level cache wherein each cache has a respective miss status holding register), and a prefetcher connected to each of the two or more cache levels (pg. 4, Section III, A, describes the existence of prefetchers that exist and would need to be connected to the cache so as to prefetch data for them). Jalili does not explicitly teach the prefetcher configured to: receive feedback from the miss status holding registers at each cache level for previously sent prefetches, and control number of prefetches sent for a trained entry to each cache level of the two or more cache levels based on the feedback.
Al Sheikh teaches the prefetcher configured to: receive feedback from the miss status holding registers at each cache level for previously sent prefetches, and control number of prefetches sent for a trained entry to each cache level of the two or more cache levels based on the feedback (Paragraphs [0033] and [0043], states that depending on a hit or miss count of a miss holding register for the cache a prefetcher can increment or decrement a confidence value for a confidence predictor which is then used to determine what to prefetch). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Jalili to utilize the prefetcher of Al Sheikh so to prefetch the data to the data cache to avoid a miss in the data cache for a subsequent instance of the second instruction of the correlated pair (Al Sheikh, Paragraph [0019]).
Regarding claim 2, Jalili and Al Sheikh teach all the limitations to claim 1. Jalili further teaches wherein the feedback includes a fullness indicator of the miss status holding registers at each cache level, the prefetcher configured to: send prefetches to cache levels of the two or more cache levels which have available miss status holding registers (pg. 7, Section IV, A, states that an amount of the MSHR can be reserved for demand accesses which will alter the prefetch rate meaning how full/how much access or space the prefetcher has to work with will be a factor in determining the rate). The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 14 and 15, claims 14 and 15 are the method claims associated with claims 1 and 2. Since Jalili and Al Sheikh teach all the limitations to claims 1 and 2, they also teach all the limitations to claims 14 and 15; therefore the rejections to claims 1 and 2 also apply to claims 14 and 15.
Regarding claim 18 and 19, claims 18 and 19 are the prefetcher claims associated with claims 1 and 2. Since Jalili and Al Sheikh teach all the limitations to claims 1 and 2 and Al Sheikh further teaches one or more trained entries for each cache in at least a two-level cache hierarchy (Paragraph [0020], states the cache can be hierarchical. Paragraph [0022], describes the miss tracking table and address delta predictor which can have trained entries for the caches), they also teach all the limitations to claims 18 and 19; therefore the rejections to claims 1 and 2 also apply to claims 18 and 19.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jalili and Al Sheikh as applied to claims 1 above, and further in view of Zou et al. (US PGPub 2017/0118631, hereafter referred to as Zou).
Regarding claim 3, Jalili and Al Sheikh teach all the limitations to claim 2. Jalili and Al Sheikh do not teach wherein the fullness indicator is a relative indicator allowing the prefetcher to be uninformed of an absolute size of the miss status holding registers at each cache level.
Zou teaches wherein the fullness indicator is a relative indicator allowing the prefetcher to be uninformed of an absolute size of the miss status holding registers at each cache level (Paragraph [0083], states that when buffers are full the prefetcher can be disabled and when the fulness drops below a threshold value (relative indicator) the prefetcher can be re-enabled). Since both Jalili/Al Sheikh and Zou teach operating prefetchers it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Jalili and Al Sheikh to also use a relative fulness indicator as taught in Zou to obtain the predictable result of wherein the fullness indicator is a relative indicator allowing the prefetcher to be uninformed of an absolute size of the miss status holding registers at each cache level.
Allowable Subject Matter
Claims 4-13, 16, 17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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