DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: ELECTRONIC PRINTING SYSTEM INCLUDING IMAGING APPARATUS AND ELECTRONIC PAPER, METHOD OF OPERATING ELECTRONIC PRINTING SYSTEM, AND METHOD OF FABRICATING IMAGING APPARATUS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 11-12, 14 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gila et al. (US 2014/0240299 A1, hereinafter Gila 1).
As to claim 1, Gila 1 discloses an electronic printing system (Gila 1, FIG. 6I, [0068], “writing system 600”), comprising an imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) and an electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) that can be detached from each other (Gila 1, e.g., see FIGS. 10-11) and can be coupled together (Gila 1, FIG. 6I, [0059], “complaint layer 108, being made of a flexible material, allows firm contact between the array of electrodes 604 and the e-paper 610 and charges are applied to the layer of microcapsule 106 without loss, thus resulting in enhanced quality of the display”) to perform one or more functionalities (Gila 1, FIG. 6I, [0059], “writing module 602 writes the information to the e-paper 610 through the complaint layer 608”);
wherein the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) comprises a first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”) and a first passivation layer (Gila 1, FIG. 6I, [0066], “compliant layer 622”) on the first electrode (Gila 1, see FIG. 6I, [0068], “array of electrodes 604”);
wherein the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) comprises a second electrode (Gila 1, FIG. 6I, [0063], “conductive ground layer 110”), an electro-optic layer (Gila 1, FIG. 6I, [0059], “layer of microcapsule 106”) on the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”), and a second passivation layer (Gila 1, FIG. 6I, [0059], “compliant layer 608”) on a side of the electro-optic layer (Gila 1, see FIG. 6I, [0059], “layer of microcapsule 106”) away from the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”);
wherein, when the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) and the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) are coupled together (Gila 1, FIGS. 6A-6I, [0059], “ FIG. 6E depicts the writing module 602 in full contact with the e-paper 610”) to perform at least one of the one or more functionalities (Gila 1, see FIGS. 6A-6I, [0059], “the writing module 602 writes the information to the e-paper 610 through the complaint layer 608”), the first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”), the first passivation layer (Gila 1, FIG. 6I, [0066], “compliant layer 622”), the second passivation layer (Gila 1, FIG. 6I, [0059], “compliant layer 608”), the electro-optic layer (Gila 1, FIG. 6I, [0059], “layer of microcapsule 106”), and the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”) are sequentially arranged in a stacked structure (Gila 1, see FIG. 6I), the first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”) and the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”) being configured to apply an electric field to the electro-optic layer (Gila 1, e.g., FIG. 6D, [0051], “in a writing phase, an electrical field applied to the compliant layer 608 with respect to the conductive ground layer 110 may cause redistribution of charged pigments in the layer of the microcapsules 106”);
wherein, the first passivation layer (Gila 1, FIG. 6I, [0066], “compliant layer 622”) and the second passivation layer (Gila 1, FIG. 6I, [0059], “compliant layer 608”) can be detached from each other (Gila 1, e.g., see FIGS. 6 and 10-11).
As to claim 2, Gila 1 discloses the electronic printing system of claim 1, wherein the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) is a passive electronic paper (Gila 1, FIG. 1A, [0026], “The microcapsules 106 are designed to exhibit image stability using physico-chemical adhesion between particles and/or between the particles and the microcapsule surface. For example, the black and white microcapsules ideally can hold text and images indefinitely without drawing electricity, while allowing the text or images to be changed later”).
As to claim 11, Gila 1 discloses the electronic printing system of claim 1, wherein the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”) comprises a non-transparent electrode material (Gila 1, FIG. 1A, [0025], “conductive ground layer 110 can be composed of … an opaque conductive material and can have a thickness ranging from approximately 5 nm to approximately 1 mm”).
As to claim 12, Gila 1 discloses the electronic printing system of claim 1, wherein the first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”) comprises a non-transparent electrode material (engineering choice), and the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”) comprises a non-transparent electrode material (Gila 1, FIG. 1A, [0025], “conductive ground layer 110 can be composed of … an opaque conductive material and can have a thickness ranging from approximately 5 nm to approximately 1 mm”).
As to claim 14, Gila 1 discloses a method of operating an electronic printing system (Gila 1, FIG. 6I, [0068], “writing system 600”), comprising:
providing an imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) and an electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) that can be detached from each other and can be coupled together (Gila 1, e.g., see FIGS. 6-10) to perform one or more functionalities (Gila 1, FIG. 6C, [0050], “In the writing phase, the writing module 602 establishes contact with the e-paper 610 through the compliant layer 608”); and
assembling the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) and the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) so that a first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”) from the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) and a second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”) from the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) are capable of forming an electric field for driving an electro-optic layer in the electronic paper (Gila 1, e.g., FIG. 6D, [0051], “in a writing phase, an electrical field applied to the compliant layer 608 with respect to the conductive ground layer 110 may cause redistribution of charged pigments in the layer of the microcapsules 106”).
As to claim 20, Gila 1 discloses the method of claim 14, further comprising: conforming a shape of the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) to a shape of an object having the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) attached thereon; and performing the one or more functionalities with the imaging apparatus and the electronic paper having complementary conforming shapes (Gila 1, FIG. 6D, [0060], “the two-dimensional array of electrodes 604 may be dimensioned to substantially match the dimensions of the e-paper 610. This facilitates the array of electrodes 604 to erase and write to the entire e-paper 610 without scanning”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 9 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1) in view of Yamazaki (US 2011/0141082 A1).
As to claim 3, Gila 1 does not teach the electronic printing system of claim 1, wherein the imaging apparatus comprises a first transistor, a capacitor, and the first electrode; a gate electrode of the first transistor is coupled to a gate line which is coupled to a gate driving integrated circuit;
a first source electrode of the first transistor is coupled to a data line which is coupled to a data driving integrated circuit; a first drain electrode of the first transistor is coupled to the first electrode and a second capacitor electrode of the capacitor; and a first capacitor electrode of the capacitor is coupled to a reference signal line.
However, Yamazaki teaches the concept that the imaging apparatus (Yamazaki, FIG. 2, [0065], the circuit corresponding to “pixel 40” with “pixel electrode 35” without “electrophoretic element 32” and “common electrodes 37”) comprises a first transistor (Yamazaki, FIG. 2, [0065], “selection transistor TRs”), a capacitor (Yamazaki, FIG. 2, [0065], “storage capacitor C1”), and the first electrode (Yamazaki, FIG. 2, [0065], “pixel electrode 35”);
a gate electrode of the first transistor (Yamazaki, FIG. 2, [0065], “selection transistor TRs”) is coupled to a gate line (Yamazaki, see FIG. 2, [0065], “scanning line 66”) which is coupled to a gate driving integrated circuit (Yamazaki, see FIGS. 1-2, [0059], “scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2, . . . , and Ym)”);
a first source electrode of the first transistor (Yamazaki, FIG. 2, [0065], “selection transistor TRs”) is coupled to a data line (Yamazaki, see FIG. 2, [0065], “data line 68”) which is coupled to a data driving integrated circuit (Yamazaki, see FIGS. 1-2, [0060], “data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2, . . . , and Xn)”);
a first drain electrode of the first transistor (Yamazaki, FIG. 2, [0065], “selection transistor TRs”) is coupled to the first electrode (Yamazaki, see FIG. 2, [0065], “pixel electrode 35”) and a second capacitor electrode of the capacitor (Yamazaki, see FIG. 2, [0065], “storage capacitor C1”); and
a first capacitor electrode of the capacitor (Yamazaki, see FIG. 2, [0065], “storage capacitor C1”) is coupled to a reference signal line (Yamazaki, see FIG. 2, [0061], “capacity lines 69 (H1, H2, . . . , and Hm)”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “writing module 602” taught by Gila 1 to further comprise the circuit structure as in FIG. 2, as taught by Yamazaki, in order to “provide an electrophoretic writing device, a driving method of the electrophoretic writing device, and an electronic device, capable of lengthening a time when an electrophoretic element can be driven by one-time charging of a storage capacitor, and of efficiently writing images” (Yamazaki, [0007]).
As to claim 9, Gila 1 in view of Yamazaki teaches the electronic printing system of claim 1, wherein the first passivation layer (Gila 1, FIG. 6I, [0066], “compliant layer 622”) encapsulates transistors (Yamazaki, FIG. 2, [0065], “selection transistor TRs”) and capacitors (Yamazaki, see FIG. 2, [0065], “storage capacitor C1”) of the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”); and
the first passivation layer (Gila 1, FIG. 6I, [0066], “compliant layer 622”) is a multiple layer structure comprising sub-layers (Gila 1, FIG. 6I, [0066], “first compliant layer 622-1” and “second compliant layer 622-2”) made of silicon oxide (SiOy), silicon nitride (SiNy, e.g., Si3N4), silicon oxynitride (SiOxNy), or graphene (Gila 1, FIG. 6I, [0067], “rubber, polymer and elastomers … conductive silicon and conductive sponge”). Examiner renders the same motivation as in claim 3.
As to claim 15, Gila 1 in view of Yamazaki teaches the method of claim 14, further comprising printing an image on the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”) by:
turning on a first transistor (Yamazaki, FIG. 2, [0065], “selection transistor TRs”) in the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”) by an effective voltage of a gate driving signal provided by a first gate line (Yamazaki, see FIG. 2, [0065], “scanning line 66”);
allowing a data signal provided by a data line (Yamazaki, see FIG. 2, [0065], “data line 68”) to pass through the first transistor (Yamazaki, FIG. 2, [0065], “selection transistor TRs”), charging a capacitor (Yamazaki, see FIG. 2, [0065], “storage capacitor C1”) and the first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”) in the imaging apparatus (Gila 1, FIG. 6I, [0068], “writing module 602”); and
applying an electric field formed by the first electrode from the imaging apparatus and the second electrode from the electronic paper to the electro-optic layer in the electronic paper (Gila 1, e.g., FIG. 6D, [0051], “in a writing phase, an electrical field applied to the compliant layer 608 with respect to the conductive ground layer 110 may cause redistribution of charged pigments in the layer of the microcapsules 106”), thereby electronically printing an image on the electronic paper (Gila 1, e.g., see FIGS. 9-10). Examiner renders the same motivation as in claim 3.
As to claim 16, Yamazaki teaches the method of claim 14, further comprising resetting the electronic paper to an initial state by providing a reset signal through a data line to first electrodes respectively in all units of the imaging apparatus (Yamazaki, FIG. 8, [0111], “here is a case where reset is performed so that the entire surface displays white by driving only the pixels 40 forming displayed image components to perform the image erasure … if the scanning line 66 is not selected, the selection transistor TRs is turned off, but the voltage Vp at the pixel electrode 35 is maintained by the storage capacitor C1, and the pixel 40 displays white”). Examiner renders the same motivation as in claim 3.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1) in view of Yamazaki (US 2011/0141082 A1) and Kim et al. (US 2012/0162186 A1).
As to claim 4, it differs from claim 3 only in that it is the same imaging apparatus of claim 3, further comprising a circuit structure regarding “second transistor”; “first gate line”; “second gate line”; “gate driving integrated circuit”; and “read line”, and recites substantially the same limitations as in claim 3. Miyazaki teaches them, and Examiner renders the same motivation as in claim 3.
Gila 1 in view of Miyazaki does not teach the circuit structure regarding “second transistor”; “first gate line”; “second gate line”; “gate driving integrated circuit”; and “read line”.
However, Kim teaches the concepts of the circuit structure (Kim, see FIG. 6) regarding “second transistor (Kim, FIG. 6, [0064], “second transistor T2”)”; “first gate line (Kim, FIG. 6, [0064], “first gate line GL1i”)”; “second gate line (Kim, FIG. 6, [0064], “second gate line GL2i”)”; “gate driving integrated circuit (Kim, FIGS. 1 and 6, [0043], “gate driving unit 120”)”; and “read line (Kim, FIG. 6, [0064], “data line DLj”)”.
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the driving circuit taught by FIG. 2 of Yamazaki to further comprise the circuit structure regarding “second transistor T2”, “first gate line GL1i”, “second gate line GL2i”, “gate driving unit 120” and “data line DLj”, as taught by FIG. 6 of Kim, in order to “reduce the number of data channels” (Kim, [0006]).
As to claim 5, Kim teaches the electronic printing system of claim 4, wherein the read line (Kim, FIG. 6, [0064], “data line DLj”) is the data line (Kim, FIG. 6, [0064], “data line DLj”). Examiner renders the same motivation as in claim 4.
As to claim 6, Kim teaches the electronic printing system of claim 4, further comprising a connecting line (Kim, see FIG. 6) connecting the second drain electrode of the second transistor (Kim, FIG. 6, [0064], “second transistor T2”) to the read line (Kim, FIG. 6, [0064], “data line DLj”). Examiner renders the same motivation as in claim 4.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1).
As to claim 10, Gila 1 teaches the electronic printing system of claim 1, wherein the second passivation layer (Gila 1, FIG. 6I, [0059], “compliant layer 608”) encapsulates the electro-optic layer (Gila 1, see FIG. 6I, [0059], “layer of microcapsule 106”) and the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”) of the electronic paper (Gila 1, FIG. 6I, [0068], “e-paper 610”); and
the second passivation layer (Gila 1, FIG. 6I, [0059], “compliant layer 608”) is made of silicon oxide (SiOy), silicon nitride (SiNy, e.g., SisN4), silicon oxynitride (SiOxNy), or graphene (Gila 1, FIG. 6I, [0053], “the compliant layer 608 is made of a compliant material, such as rubber or polymer, such as urethane. Other examples of the compliant material include conductive silicon, conductive sponge”).
Gila 1 does not explicitly teach the second passivation layer is “a multiple layer structure comprising sub-layers”.
However, Gila 1 teaches the concept that the first passivation layer (Gila 1, FIG. 6I, [0066], “compliant layer 622”) is a multiple layer structure comprising sub-layers (Gila 1, FIG. 6I, [0066], “first compliant layer 622-1” and “second compliant layer 622-2”).
At the time of effective filing date, especially considering that the 1st and 2nd passivation layers have similar functions and are counterparts to each other, it would have been obvious to one of ordinary skill in the art to modify the “compliant layer 608” taught by Gila 1 to further comprise a multiple layer structure, as taught by Gila 1, as an engineering choice to enhance the similar functions.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1) in view of Gila et al. (US 2017/0052421 A1, hereinafter Gila 2).
As to claim 13, Gila 1 teaches the electronic printing system of claim 1, wherein the imaging apparatus has a first size; the electronic paper has a second size; and the first size is greater than the second size (Gila 1, FIG. 6D, [0060], “the two-dimensional array of electrodes 604 may be dimensioned to substantially match the dimensions of the e-paper 610. This facilitates the array of electrodes 604 to erase and write to the entire e-paper 610 without scanning”).
Gila 1 does not explicitly teach “the second electrode is a second base substrate of the electronic paper; the electronic paper is absent of a layer that covers a side of the second electrode away from the electro-optic layer and the second electrode”.
However, Gila 2 teaches the concept that the second electrode (Gila 2, FIG. 3, [0027], “ground electrode 302”) is a second base substrate (Gila 2, see FIG. 3) of the electronic paper (Gila 2, FIG. 3, [0027], “e-paper display 300”); and
the electronic paper (Gila 2, FIG. 3, [0027], “e-paper display 300”) is absent of a layer that covers a side of the second electrode (Gila 2, FIG. 3, [0027], “ground electrode 302”) away from the electro-optic layer (Gila 2, see FIG. 3, [0027], “active layer 304”) and the second electrode (Gila 2, FIG. 3, [0027], “ground electrode 302”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to substitute the “e-paper 610” taught by Gila 1 with the “e-paper display 300”, as taught by Gila 2, in order to “enable a secure electrical connection between a writing module and a ground return path of an e-paper display device” (Gila 2, [0015]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1) in view of Hattori (US 2006/0262257 A1).
As to claim 17, Gila 1 does not teach the method of claim 14, further comprising scanning an image displayed on the electronic paper by: assembling the imaging apparatus and the electronic paper so that the first electrode from the imaging apparatus and the electro-optic layer from the electronic paper are close enough to induce a charge in the first electrode by a unit in the electro-optic layer; and detecting the charge as a sensing signal by transmitting the sensing signal through a signal line to a detection integrated circuit.
However, Hattori teaches the concept of scanning an image displayed on the electronic paper by: assembling the imaging apparatus and the electronic paper so that the first electrode from the imaging apparatus and the electro-optic layer from the electronic paper are close enough to induce a charge in the first electrode by a unit in the electro-optic layer; and detecting the charge as a sensing signal by transmitting the sensing signal through a signal line to a detection integrated circuit (Hattori, FIG. 5, [0066]-[0067], “When the control unit 25 applies electric signals to prescribed first electrodes 10a and second electrodes 11a in this state, the white charged particles 15 and black charged particles 16 in the capsules 13 interposed between these first electrodes 10a and second electrodes 11a separately migrate toward the first electrodes 10a side and second electrodes 11a side. In this way, it is possible to display images through the white and black contrast appearing on the surface of the display medium 7. Further, by scanning the lines to which voltage is applied and reversing the polarity applied to the first electrodes 10a and second electrodes 11a, it is possible to rewrite the image displayed on the display medium 7”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “writing module 602” taught by Gila 1 to further perform the “scanning”, as taught by Hattori, in order to provide “an electronic paper that can be treated like ordinary paper and that can be manufactured at a reduced cost” (Hattori, [0009]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1) in view of Hattori (US 2006/0262257 A1) and Yamazaki (US 2011/0141082 A1).
As to claim 18, Gila 1 in view of Hattori does not teach the method of claim 17, prior to inducing the charge in the first electrode, further comprising: resetting the capacitor; and applying a constant voltage signal to the second electrode to induce a charge in the unit of the electronic paper.
However, Yamazaki teaches the concept of, prior to inducing the charge in the first electrode, resetting the capacitor; and applying a constant voltage signal to the second electrode to induce a charge in the unit of the electronic paper (Yamazaki, FIG. 8, [0111], “there is a case where reset is performed so that the entire surface displays white by driving only the pixels 40 forming displayed image components to perform the image erasure … if the scanning line 66 is not selected, the selection transistor TRs is turned off, but the voltage Vp at the pixel electrode 35 is maintained by the storage capacitor C1, and the pixel 40 displays white”). Examiner renders the same motivation as in claim 3.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Gila et al. (US 2014/0240299 A1, Gila 1) in view of Xu et al. (US 2024/0053844 A1).
As to claim 21, Gila 1 teaches a method of fabricating an imaging apparatus (Gila 1, FIG. 6I, [0068], “writing system 600”) substrate”), comprising: forming a first passivation layer (Gila 1, FIG. 6I, [0059], “compliant layer 608”) on a side of the first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”).
Gila 1 does not teach “forming a first transistor and a capacitor; forming a planarization layer on a side of the first transistor and the capacitor away from the first base substrate; forming a first via extending through the planarization layer; forming a first electrode on a side of the planarization layer away from the first base substrate, the first electrode connected to a first drain electrode and/or a second capacitor electrode through the first via; wherein forming the planarization layer comprises encapsulating the first transistor and the capacitor using an organic material having high hermeticity”.
However, Xu teaches the concepts of forming a first transistor (Xu, FIG. 5, [0090], “transistor 11A”) and a capacitor (Xu, FIG. 5, [0090], “storage capacitor 11B”) on a first base substrate (Xu, FIG. 5, [0090], “base substrate 10”);
forming a planarization layer on a side of (Xu, see FIG. 5, [0091], “a planarization layer”) the first transistor (Xu, FIG. 5, [0090], “transistor 11A”) and the capacitor (Xu, FIG. 5, [0090], “storage capacitor 11B”) away from the first base substrate (Xu, see FIG. 5, [0090], “base substrate 10”);
forming a first via (Xu, FIG. 5, [0090], a “via” connecting “anode 31” and “drain electrode of the transistor 11A”) extending through the planarization layer (Xu, see FIG. 5);
forming a first electrode (Xu, FIG. 5, [0090], “anode 31”) on a side of the planarization layer away from the first base substrate (Xu, see FIG. 5, [0090], “base substrate 10”), the first electrode (Xu, FIG. 5, [0090], “anode 31”) connected to a first drain electrode (Xu, FIG. 5, [0090], “drain electrode of the transistor 11A”) and/or a second capacitor electrode through the first via (Xu, FIG. 5, [0090], a “via” connecting “anode 31” and “drain electrode of the transistor 11A”);
wherein forming the planarization layer (Xu, FIG. 5, [0090], “ encapsulation layer 14”) comprises encapsulating the first transistor and the capacitor using an organic material having high hermeticity (Xu, FIG. 5, [0090], “second encapsulation layer 42 may be made of an organic material … so as to prevent external water vapor from entering the light emitting structure layer 13”).
At the time of effective filing date, especially given that Gila 1 already teaches that the working mechanism of the “writing module 602” is substantially the same as the driving pixels of electronic papers (Xu, [0063], “The display substrate or display backplane may be … or an Electrophoretic Display (EPD)), it would have been obvious to one of ordinary skill in the art to modify the “writing module 602” taught by Gila 1 to be configured to comprise the circuit shown in FIG. 5, as taught by Xu, in order to provide it as the driving circuits for the “array of electrodes 604”.
Allowable Subject Matter
Claims 7-8 and 19 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 7, the closest known prior art, i.e., Gila et al. (US 2014/0240299 A1), Yamazaki (US 2011/0141082 A1), Kim et al. (US 2012/0162186 A1), Gila et al. (US 2020/0150509 A1), Hattori (US 2006/0262257 A1), Xu et al. (US 2024/0053844 A1), Gila et al. (US 2020/0147978 A1), Chun et al. (US 2017/0052421 A1) and Wang (US 2014/0111593 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the read line is in a same layer as source electrodes and drain electrodes of the first transistor and the second transistor, and the second capacitor electrode; the connecting line is in a same layer as the first electrode; and the connecting line extends through at least one of a planarization layer or a third passivation layer to connect to the second drain electrode of the second transistor, and extends through at least one of the planarization layer or the third passivation layer to connect to the read line”.
As to claim 8, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the read line is in a same layer as source electrodes and drain electrodes of the first transistor and the second transistor, and the second capacitor electrode; the connecting line is in a same layer as gate electrodes of the first transistor and the second transistor; the second drain electrode extends through at least an inter-layer dielectric layer to connect to the connecting line; and the read line extends through at least the inter-layer dielectric layer to connect to the connecting line”.
As to claim 19, Gila 1 in view of Yamazaki and Kim teaches the method of claim 18, further comprising: inducing the charge in the first electrode (Gila 1, FIG. 6I, [0068], “array of electrodes 604”) by the constant voltage signal (Yamazaki, FIG. 8, [0111], “the voltage Vp at the pixel electrode 35 is maintained by the storage capacitor C1”) applied to the second electrode (Gila 1, see FIG. 6I, [0063], “conductive ground layer 110”);
turning on a second transistor (Kim, FIG. 6, [0064], “second transistor T2”) by an effective voltage of a second gate driving signal provided by a second gate line (Kim, FIG. 6, [0064], “second gate line GL2i”).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “transmitting a sensing signal caused by the charge on the first electrode through the second transistor and a data line to a detection integrated circuit”.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Gila et al. (US 2020/0147978 A1) teaches the concept of “writing on electronic paper” (Abs.); Chun et al. (US 2017/0052421 A1) teaches the concept of the first electrode as the base substrate (FIG. 3A, “counter electrode 140 (e.g. base)”); and Wang (US 2014/0111593 A1) teaches the concept of “e-paper printing device” (Abs.).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Dec. 23, 2025
/RICHARD J HONG/Primary Examiner, Art Unit 2621