DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/19/2026 has been entered.
Status of Claims
This office action is a response to an amendment filed on 06/19/2026. Claims 1-18 are currently pending, of which claims 1, 6 and 13-18 are amended.
Response to Arguments
Applicant’s remarks, see pages 6-9, with respect to the rejections under 35 USC 103 have been fully considered. The amended claims overcome the prior rejections; therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made, necessitated by the amendments.
Claim Objections
Claim 17 is objected to because of the following informalities:
Claim 17 recites “the address prediction information for use in predicting upcoming instructions be executed by processing circuitry” but should read “the address prediction information for use in predicting upcoming instructions to be executed by processing circuitry”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 8, 10-13 and 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Blasco et al. (US 2025/0378157), hereinafter Blasco.
Regarding claim 1, Blasco discloses an apparatus comprising:
processing circuitry to execute instructions (Blasco, [0025]-[0026]);
address prediction storage circuitry to store address prediction information for use in predicting upcoming instructions to be executed by the processing circuitry, wherein (Blasco, [0008], [0102]: RAS (address prediction storage circuitry) stores and provides a predicted return address (address prediction information) as prediction information used to select a predicted branch target address for instruction fetching (i.e., for use in predicting upcoming instructions))
the processing circuitry is responsive to an instruction to generate a pointer signature for a pointer to generate the pointer signature for the pointer based at least in part on an address of the pointer and a cryptographic key (Blasco, [0056], [0070]: Sign instruction (instruction to generate a pointer signature) causes generation of a signature from the return address (address of the pointer) and key (cryptographic key));
the address prediction storage circuitry is configured to store address prediction information for the pointer, the address prediction information comprising at least the pointer (Blasco, [0100], [0102]: RAS (address prediction storage circuitry) stores the return address (pointer) and associated signature, and provides the return address as the predicted target for instruction fetching (i.e., for use in predicting upcoming instructions); [the stored return address and associated signature is “address prediction information”]); and
the processing circuitry is responsive to an instruction to authenticate a given pointer to (Blasco, [0061]: Auth instruction (instruction to authenticate) initiates authentication of the return/jump address (given pointer) in source register RS): obtain, based on the address prediction information for the given pointer, a predicted pointer signature (Blasco, [0008]: authenticator generates a signature (predicted pointer signature) based on the copy of the return address (address prediction information) from the RAS); compare the predicted pointer signature with a pointer signature identified by the instruction to authenticate (Blasco, [0062], [0008]: signature generated from the RAS predicted return address (predicted pointer signature) is compared with signature field 22 (pointer signature) in the source register data selected by the Auth instruction); and responsive to the comparing detecting a match, determine that the given pointer is unmodified (Blasco, [0062], [0042]: a match between the generated and stored signature passes authentication and indicates that the return address (given pointer) has not been modified).
Regarding claim 2, Blasco discloses wherein: the address prediction information for the given pointer further comprises the pointer signature (Blasco, [0102]: the RAS stores predicted return address (given pointer) along with its cryptographic signature (pointer signature); [RAS contents is the “address prediction information”]); and the processing circuitry is configured to obtain the predicted pointer signature by identifying the pointer signature in the address prediction information for the given pointer (Blasco, [0102]: authenticator retrieves from the RAS contents (address prediction information) the signature copy (predicted pointer signature) stored with the predicted return address and uses that retrieved signature in the comparison).
Regarding claim 3, Blasco discloses wherein: the processing circuitry is configured to obtain the predicted pointer signature by generating the predicted pointer signature based at least in part on an address of the given pointer from the address prediction information and the cryptographic key (Blasco, [0008]-[0009]: authenticator obtains signature (predicted pointer signature) by generating it from the copy of the return address from the RAS (address of the given pointer from the address prediction information) and one or more keys (cryptographic key)).
Regarding claim 4, Blasco discloses wherein: the processing circuitry is configured to generate the pointer signature based further on context information associated with a current execution state of the processing circuitry (Blasco, [0069]-[0070]: generating the pointer signature using the current thread’s stack pointer derived virtual address (context information) in addition to the return address (pointer) and key).
Regarding claim 5, Blasco discloses wherein: the processing circuitry is configured to maintain a stack pointer indicative of a location in a memory system corresponding to the end of a program stack referenced by the processing circuitry (Blasco, [0069]: each thread is provided with a stack pointer; the virtual address is the stack pointer added to an offset which identifies the location at which the return address is to be pushed (i.e., the location in a memory corresponding to the end of a program stack)) ; and the context information comprises the stack pointer (Blasco, [0069]: the virtual address (context information) used in signing the return address is the stack pointer).
Regarding claim 7, Blasco discloses wherein: obtaining the predicted pointer signature comprises generating the predicted pointer signature based at least in part on an address of the given pointer from the address prediction information, the cryptographic key and context information associated with a state of the processing circuitry (Blasco, [0008], [0069]-[0070]: generating a cryptographic signature from the predicted return address from the RAS (address of the given pointer from the address prediction information), a key (cryptographic key), and a stack pointer derived virtual address (context information)).
Regarding claim 8, Blasco discloses wherein: the context information used to generate the predicted pointer signature is current context information associated with an execution state of the processing circuitry when the predicted pointer signature is generated (Blasco, [0083]: using the stack pointer, or a stack pointer derived virtual address (context information), existing at the time the signature is regenerated as an input to that regeneration).
Regarding claim 10, Blasco discloses wherein: the processing circuitry is configured to generate the pointer signature in connection with a function call operation (Blasco, [0100]: authenticator generates signature (pointer signature) before the procedure call completes); the given pointer is a return pointer to identify a next instruction to be executed following a function return operation (Blasco, [0031]: the return address (given pointer/return pointer) identifies the branch target location at which execution resumes after the procedure return); and the processing circuitry is configured to authenticate the return pointer in preparation for the function return operation (Blasco, [0100], [0103]: authenticator regenerates and compares (authenticates) the signature for the associated return address (return pointer) with earlier copies, and permits the procedure return instruction to commit only after a match (i.e., in preparation for the function return operation)).
Regarding claim 11, Blasco discloses wherein: the address prediction storage circuitry is call-return stack storage circuitry to store call-return prediction information for use in predicting a return memory address of an instruction to be executed following a function return operation (Blasco, [0101], [0102]: RAS (call-return stack storage circuitry) stores the return address (call-return prediction information) and provides it as the predicted branch target address (return memory address) for instruction fetching when a procedure return occurs).
Regarding claim 12, Blasco discloses wherein: the processing circuitry is configured to generate an augmented pointer based on the given pointer and the pointer signature by replacing a portion of the pointer with the pointer signature (Blasco, [0041], [0100]: authenticator forms one concatenated value (augmented pointer) by storing the generated signature (pointer signature) in place of the sign extended portion of the return address pointer (i.e., replacing a portion of the pointer)) and store the augmented pointer in at least one of the address prediction storage circuitry and a memory system (Blasco, [0100]: storing the concatenated signature and return address value (augmented pointer) in both RAS (address prediction storage circuitry) and memory stack (memory system)).
Regarding claim 13, Blasco discloses wherein: the processing circuitry is configured to determine, responsive to the comparing detecting a mismatch, that the given pointer is modified (Blasco, [0042], [0053]: detecting a signature mismatch after the return address (given pointer) has been modified and producing an authentication failure indication).
Regarding claim 16, Blasco discloses wherein: the processing circuitry is configured, responsive to determining that the given pointer is modified, to raise an exception (Blasco, [0105]: generating an exception when the signature comparison produces the mismatch (i.e., when determined the given pointer is modified)).
Regarding claim 17, Blasco discloses a method of authenticating a pointer, the method comprising: generating, in response to an instruction to generate a pointer signature for a pointer, the pointer signature for the pointer based at least in part on an address of the pointer and a cryptographic key (Blasco, [0056], [0070]: sign instruction causes generation of a signature (pointer signature) from a return address (address of the pointer) and key (cryptographic key)); storing, in address prediction storage circuitry, address prediction information for the pointer, the address prediction information comprising at least the pointer, the address prediction information for use in predicting upcoming instructions be executed by processing circuitry (Blasco, [0100], [0102]: RAS (address prediction storage circuitry) stores the return address (pointer) and associated signature, and provides the return address as the predicted target for instruction fetching (i.e., for use in predicting upcoming instructions); [the stored return address and associated signature is “address prediction information”]); and in response to receiving an instruction to authenticate a given pointer (Blasco, [0061]: Auth instruction (instruction to authenticate) initiates authentication of the return/jump address (given pointer) in source register RS): obtaining, based on the address prediction information for the given pointer, a predicted pointer signature (Blasco, [0008]: authenticator generates a signature (predicted pointer signature) based on the copy of the return address (address prediction information) from the RAS); comparing the predicted pointer signature with a pointer signature identified by the instruction to authenticate (Blasco, [0062], [0008]: signature generated from the RAS predicted return address (predicted pointer signature) is compared with signature field 22 (pointer signature) in the source register data selected by the Auth instruction); and responsive to the comparing detecting a match, determining that the given pointer is unmodified (Blasco, [0062], [0042]: a match between the generated and stored signature passes authentication and indicates that the return address (given pointer) has not been modified).
Regarding claim 18, the limitations have been addressed in the rejection of claim 1, and furthermore, Blasco discloses a computer-readable medium to store computer-readable code for fabrication of an apparatus (Blasco, [0116]).
Allowable Subject Matter
Claims 6, 9, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LESA M KENNEDY whose telephone number is (571)431-0704. The examiner can normally be reached Monday-Wednesday 9:30 am - 5:30 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Umar Cheema can be reached on (571) 270-3037. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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The examiner also requests, in response to this Office Action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
/LESA M KENNEDY/Primary Examiner, Art Unit 2458
Prosecution Insights