DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 10/07/2025, for application number 18/578,276 has been received and entered into record. Claims 1 and 24 are amended. Claims 23 is cancelled. Claims 47 and 48 are added. Thus, claims 1-5, 7-10, 12-17, 19, 21 and 24-25 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 9, 10, 15-17 19, 21, 24, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Callaway Jr. et al. (US 2018/0341311 A1) in view of Myers et al. (US 10,886,919 B1) and in further view of Warneke (US 8,943,352 B1).
Regarding claim 1, Callaway Jr. teaches an integrated-circuit device (system of Figure 1, and “on-chip radio connectivity for system-on-chips (SoCs) and system-on-modules (SoMs) that implement WPAN wireless solutions for IoT.” Par 0012) comprising:
a low-resolution timer comprising a first oscillator configured to output a first clock signal at a first frequency and a first counter register incremented by the first clock signal (“Similarly, low-frequency counter 160 coupled to the low-frequency clock source 150 counts at the clock frequency of the low-frequency clock source, or a derivative thereof. As used herein, the terms clock, clock source, oscillator and crystal may be used interchangeably.” Par 0018 and “the term counter, timer and timer counter may be used interchangeably. The counters may count upwards or downwards, and may be comprised of various random logic, such as flip-flops.” par 0015) [flip-flops are used to build registers, thus under BRI, the counter may correspond to a counter register];
a high-resolution timer comprising a second oscillator configured to output a second clock signal at a second frequency and a second counter register incremented by the second clock signal, the second frequency being greater than the first frequency (“The high-frequency counter 140 coupled to the high-frequency clock source 130 is operable to count at the clock frequency of the high-frequency clock source, or a derivative thereof.” Par 0018 and “In this example, the high-frequency clock source 230 may be a 32 MHz oscillator as shown; … Low-frequency clock source 250 is illustrated as a 32.768 kHz oscillator;” par 0029) [in this embodiment, the high-resolution timer’s frequency is greater than the low-resolution timer’s];
the device is configured to transition from the sleep state to the active state, said transition comprising writing a value to the second counter register based on a value held in the first counter register (“Upon the next rising edge of the 32.768 kHz low-frequency oscillator 250 after resumption of the high-frequency oscillator 230, the timer-control state machine 220 performs the following functions: Computes the new high-frequency counter value, Y1” par 0035 and “The new high-frequency counter value, Y1, is loaded into the high-frequency counter 240, which is then enabled to resume counting at the new high-frequency counter value.” Par 0044 and “The new high-frequency counter value may thus be determined by the timer controller 120 based on a duration of time that the high-frequency clock source 130 was disabled and a previous high-frequency counter value of the high-frequency counter 140 at the first time.” Par 0022) [this shows the device transitioning from sleep to active state by computing Y1 and loading (writing) it into counter 240 (second counter register); duration of the high-frequency clock was disabled is determined using the constantly running low-frequency counter, ensuring the new high-resolution counter value is calculated (based on a value held in) the low-resolution counter];
However, Callaway Jr. does not explicitly teach a tuning register; wherein the device is configured to operate in one of a plurality of states, the plurality of states comprising: an active state in which both the high-resolution timer and the low-resolution timer are enabled; and a sleep state in which the high-resolution timer is disabled and the low-resolution timer is enabled; the tuning register is configured, when the device is in the active state, to: be incremented by a first predetermined value by the first clock signal; be decremented by a second predetermined value by the second clock signal, the second predetermined value being smaller than the first predetermined value; and the device is configured to tune the value held in the second counter register in dependence on the value held in the tuning register.
In the analogous art, Myers teaches a tuning register (“The timer circuitry may be configured to selectively adjust the increment value by selectively increasing and/or by selectively decreasing the increment value so as to thereby compensate for the various changes in the clock frequency of the real-time clock (RTC) signal.” Col. 2, ll. 30-35 and “The increment circuitry 208 generates and provides an increment value to the counter circuitry 204 to adjust the RTC signal. In some instances, the increment circuitry 208 may also be configured as decrement circuitry that provides a decrement value to the counter circuitry 204 to adjust the RTC signal.” Col. 6, ll. 5-10);
wherein
the device is configured to operate in one of a plurality of states (“In various instances, the sleep mode of operation may refer to a low power mode, a standby mode, or a deep sleep mode of operation.” Col. 7, ll. 32-34)
the tuning register is configured, when the device is in the active state, to:
be incremented by a first predetermined value by the first clock signal (“The increment circuitry 208 generates and provides an increment value to the counter circuitry 204 to adjust the RTC signal.” Col. 6, ll. 5-10);
be decremented by a second predetermined value by the second clock signal (“In some instances, the increment circuitry 208 may also be configured as decrement circuitry that provides a decrement value to the counter circuitry 204 to adjust the RTC signal.” Col. Col. 6, ll. 5-10), the second predetermined value being smaller than the first predetermined value (“In some instances, to ensure correctness of the real-time clock value (RTV), the counter 204 may be incremented and updated accordingly, such as, e.g., 8× slower clock may require addition (or increment) of 8 rather than 1.” Col. 6, ll. 51-55) [the counter’s increment value must be raised from 1 to 8 to preserve accuracy; this shows when the clock frequency is reduced (8 times slower), the compensating increment value must be increased to maintain accuracy; since this increment value is scaled up, a required counter adjustment is typically a much smaller value (1) to ensure tuning remains controlled]; and
the device is configured to tune the value held in the second counter register in dependence on the value held in the tuning register (“The timer circuitry may be configured to selectively adjust the increment value by selectively increasing and/or by selectively decreasing the increment value so as to thereby compensate for the various changes in the clock frequency of the real-time clock (RTC) signal.” Col. 2, ll. 30-35) [this shows the high-resolution counter (second counter) value is effectively tuned by adjusting its increment value (tuning register) based on changes in the clock frequency].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Callaway Jr. and Myers before him before the effective filing date of the claimed invention, to have modified Callaway Jr. to incorporate the teachings of Myers to integrate the clock adjusting techniques to maintain the original precision of the real time count value, while reducing RTC dynamic power by up to 8x. (Myers, column 6)
However, Callaway Jr. and Myers do not explicitly teach the plurality of states comprising: an active state in which both the high-resolution timer and the low-resolution timer are enabled; and a sleep state in which the high-resolution timer is disabled and the low-resolution timer is enabled.
In the analogous art, Warneke teaches the plurality of states comprising:
an active state in which both the high-resolution timer and the low-resolution timer are enabled (“The node may have a primary high frequency oscillator having a frequency of 20 MHz used to maintain timing in the node when the node is in an activated state.” Col. 8, ll. 31-34 and “Thus, for much of the time only timing components 500, 501, 502, 506, 507, 509, and 513 are active, operating at a low frequency, low power level. However, when counter 509 reaches the value in register 513, signal 512 will be asserted and cause the counter 514 to be enabled to measure out the remaining time until the event should occur to a resolution of the 505 oscillator.” Col. 10, ll. 48-54 and Figures 5A, 5B) [the active state uses the high resolution oscillator 505 and the low resolution components are active to measure event duration]; and
a sleep state in which the high-resolution timer is disabled and the low-resolution timer is enabled (“In order to reduce power consumption in the node when the node is in an inactive (or sleep) state, a high frequency oscillator may be inactivated in the node in favor of using a lower frequency oscillator having a lower power consumption.” Col. 8, ll. 13-16 and “The node may also have a secondary low frequency oscillator having a frequency of 32.768 kHz used to maintain timing in the node when the node is in an inactive state (or a sleep state).” Col. 8, ll. 34-38).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Callaway Jr., and Myers and Warneke before him before the effective filing date of the claimed invention, to have modified Callaway Jr. and Myers to incorporate the teachings of Warneke to include an active state where both high and low resolution timers are enabled and a sleep state where the high resolution timer is disabled in favor of using a lower resolution timer to reduce power consumption. This would optimize power savings via precise event scheduling. (Warneke, column 8)
Regarding claim 2, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. Callaway Jr. further teaches wherein the value written to the second counter register is a scaled copy of the value held in the first counter register (“The difference between the low-frequency count value at this transition of the low-frequency counter and that stored prior to the low-power state may be multiplied by the ratio of the high- frequency clock source to the low-frequency clock source. This result may then be added to the previously stored high-frequency count value Y0 to yield a new high-frequency counter value Y1 and re-loaded into the high-frequency counter 240.” Par 0031) [this describes how a difference in the low-frequency counter’s value is scaled by the frequency ratio to contribute to the new value loaded into the high frequency].
Regarding claim 9, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. Callaway Jr. further teaches further comprising one or more event registers each configured, when the device is in the active state, to trigger an event when a value held therein is determined to be equal to a value held in the second counter register (“Scheduled protocol operations (e.g., reception or transmission) may then occur based on a value of the high-frequency counter.” Par 0044 and “A wake-up trigger may be programmed based on a future value of the low-frequency counter 260” par 0030) [a target value is stored or configured to initiate transition from sleep to active state; the scheduled operations occurred based on value of high-frequency counter implies the system is configured with specific target counter values (implying that it is stored in a counter, which under BRI, may correspond to an event register) that, when reached, triggers the scheduled events].
Regarding claim 10, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. Callaway Jr. further teaches further comprising a compare register configured to cause the device to trigger an event when a value held therein is determined to be equal to the value held in the first counter register; wherein the device is configured to transition from the sleep state to the active state in response to the compare register triggering an event (“A wake-up trigger may be programmed based on a future value of the low-frequency counter 260 and the high- frequency clock source 230 disabled, thereby allowing the system to enter a low-power condition.” Par 0030) [this explains a specific target value for the low-frequency counter is configured to/programmed to serve as a wake-up trigger, which maps to the function of a compare register holding a value to be matched] (“The second time may be defined by a counter value of the low-frequency counter 160 reaching a predetermined value. The system controller 110 upon receiving a trigger from the low-frequency counter 160 may take steps to re-enable the high-frequency counter as will be described.” Par 0020) [this explains the comparison to a predetermined value (an event) which causes the system to reenable the counter, which corresponds to transitioning from sleep to active state].
Regarding claim 15, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. Callaway Jr. further teaches wherein the plurality of states further comprises a transition state in which both the high-resolution timer and the low-resolution timer are enabled, and in which the device is configured to determine whether to transition to the sleep state or to the active state (“The system controller 110 can selectively disable the high-frequency clock source between periods of activity of the system when the high-frequency clock is not required.” Par 0026) [the determination when to transition to a sleep state occurs during “periods of activity” when both the high-frequency (first counter register) and low frequency (second counter register) timers would be enabled].
Regarding claim 16, Callaway Jr., Myers and Warneke teach the device as claimed in claim 15. Warneke further teaches a device configured, when in the transition state, to:
determine a smallest value held in any of a plurality of event registers that is greater than the value held in the second counter register (“The retrieved operation descriptor, which may have the exemplary fields shown in FIG. 8D, can specify…the offset (field 853) into the slot at which the operation is to occur, …In state 812, the FSM will wait an amount of time specified by an operation setup time (transition 813), for example by waiting until slot counter 509 of FIG. 5A matches a particular slot number and the offset (retrieved from field 853) into the slot minus the setup time (retrieved from field 851) is reached as indicated by slot offset counter 600.” Col. 15, ll. 10-25) [the counter 901A corresponds to the second counter register; the device fetches future event times (slot number, offset) from a set of operation descriptors (event registers) then wait for the current counter 901a to reach smallest next scheduled value];
determine a difference between said determined smallest value and the value held in the second counter register (“Register 519B stores a number corresponding to the number of counts of counter 507B before the slot edge at which signal 521B should be asserted. … The value in register 519B is subtracted by subtractor 522B from the value in register 501B and the result is compared by comparator 520B to the value in counter 507B.” col. 11, ll. 17-25) [subtractor 522b calculates a difference between a target time (derived from register 501B) and a current count, which represents a difference relative to the current second current register value];
compare said difference to the predetermined timeout value held in the timeout register (“When state 822 is entered, a timer is started wherein if the SFD has not been received by the time the timer expires, transition 824 to state 835 is made indicating that the receive operation timed out.” Col. 16, ll. 55-59) [the timer’s expiration is implicitly compared against the elapsed time until a condition (SFD reception) is met, leading to a “timed out” determination]; and
determine whether to transition to the active state or the sleep state in dependence, at least in part, on said comparison (“If at the end of the window no opportunistic wake-up event has occurred, a wake-up is forced so that a worst case wake-up time is defined.” Col. 3-4, ll. 66 and ll. 1-2) [if a comparison (time elapsed vs window/timeout) indicates no prior activation, the device is forced to transition to an active state to perform the scheduled task].
Regarding claim 17, Callaway Jr., Myers and Warneke teach the device as claimed in claim 16. Warneke further teaches configured, when having determined to transition to the sleep state in the transition state, to write a value derived from the determined smallest value to a compare register (“In the example, register 902A is loaded with a value that corresponds to 4.5 ms from now (e.g., by storing a number in register 902A that the counter 901A is expected to reach in 4.5 ms) and register 903A is loaded with a value that corresponds to 5.4 ms from now (e.g., by storing a number in register 903A that the counter 901A is expected to reach in 5.4 ms)” col. 18, ll. 23-28) [this ensures a forced wakeup if no events occurs, corresponding to the smallest value (latest possible time) for the system to remain in a sleep state].
Regarding claim 19, Callaway Jr., Myers and Warneke teach the device as claimed in claim 17. Warneke further teaches wherein the second predetermined multiplicand comprises a ratio of a resolution of the event registers to a resolution of the timeout register (“In another example, in order to maintain timing information at a higher resolution, the values of registers 501 and 503 can be related to a multiple of the ratio of the slot width to the period of oscillator 500. …The multiple may enable the value of register 501 to be maintained at a higher resolution, and may thus minimize the rounding errors caused by using accumulation values related to integer portions only.” Col. 9, ll. 14-23) [the multiple (predetermined multiplicand) acts as a ratio to achieve a higher resolution for event timings (stored in register 501 as part of event registers) compared to based period of oscillator 500, which implicitly sets the resolution for simpler timeout values].
Regarding claim 21, Callaway Jr., Myers and Warneke teach the device as claimed in claim 17, further comprising multiplier logic configured, when the device transitions from the transition state to the sleep state, to:
multiply the determined smallest value by the ratio of the resolution of the event registers to the resolution of the first counter register to provide a third resultant value (“In another example, in order to maintain timing information at a higher resolution, the values of registers 501 and 503 can be related to a multiple of the ratio of the slot width to the period of oscillator 500. For instance, if oscillator 500 has a period of 30.5 us and the slot width is of 10 ms, register 503 may store a value equal to INT(128*10 ms/30.5 us)≈41967 using the multiple ‘128’.” Col. 9, ll. 14-20) [this explains multiplying a value (future event time, such as slot width) by a ratio to obtain a higher resolution result (41967), which corresponds to the third resultant value for precise timing];
subtract one from the third resultant value to provide a derived value (“Register 519B stores a number corresponding to the number of counts of counter 507B before the slot edge at which signal 521B should be asserted… The value in register 519B is subtracted by subtractor 522B from the value in register 501B and the result is compared by comparator 520B to the value in counter 507B.” col. 11, ll. 17-25); and
write the derived value to the scratch register (“When register 902C is loaded, its value is added to that in counter 901C by adder 912C and the result is stored into latch 913C and subsequently used by the comparison block 904C.” col. 18, ll. 50-53) [the derived value is stored into a temporary storage element, such as latch 913C (which under BRI, corresponds to a scratch register)]; and
copy the derived value from the scratch register to the compare register (“When the value output by counter 901C is greater than or equal to the value in latch 913C, comparison block 904C will assert the request signal 905C.” col. 18, ll. 56-59) [the derived value stored in the temporary latch 913C (scratch register) is then used by comparison block 904C (compare register) to do a comparison, indicating a “copy” or direct access for comparison].
Regarding claim 24, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. Callaway Jr. further teaches configured to add one of a set of predetermined tuning values to the second counter register in each cycle of the first clock signal, the tuning value being selected in dependence on the value held in the tuning register (“In the example illustrated in the timing diagram of FIG. 3, while the high-frequency clock is enabled, the values of the low-frequency counter and the high-frequency counter are saved at every rising edge of the low-frequency clock (at times “a” and “b”).” par 0045 and Figures 3 and 4) [when the high frequency counter is enabled, for each of the rising edge of the low frequency clock (first clock signal), the timer-control state machine 220 calculates Y1, see paragraph 35; the term added is derived from a predetermined value (dependent of the ratio of clock frequencies) and values from the low frequency counter (X1, X0, acting as a tuning reference)].
Regarding claim 25, Callaway Jr., Myers and Warneke teach the device as claimed in claim 24. Callaway Jr. further teaches wherein:
the second counter register comprises a fractional portion and an integer portion (“To address this, the remainder of the division is preserved as the remainder value (Yrv), which can be calculated by means of a division modulo 512. Division modulo 512, in turn, can be implemented as a bit-wise operation by preserving only the lowest 9 bits of the operand.” Par 0042) [the remainder value corresponds to the fractional portion], the fractional portion being configured to increment on each clock cycle of the second clock signal, and the integer portion being configured to increment each time the fractional portion overflows (“Consequently f1( ) and f2( ) are defined in this example embodiment as follows: f 1(Y 0 , X 1 , X 0 , Y rv0)=((Y 0<<9)+ 15625 * (X 1 −X 0)+Y rv0)>>9,” par 0043) [the previous integer portion, Y0) is combined with calculated values (including the old fractional part YRV0) before the final shift right operation; this implies that any carry-over from the fractional bits will increment the new integer portion, Y1; the high frequency counter’s value, including its remainder/fractional part is recalculated based on the low-frequency counter’s difference, see paragraph 33 and 35]; and
the device is configured to add one of the predetermined set of predetermined tuning values to the fractional portion of the second counter register (“To address this, the remainder of the division is preserved as the remainder value (Yrv), which can be calculated by means of a division modulo 512.” Par 0042 and “f 2(X 1 , X 0 , Y rv0)=(15625*(X 1 −X 0)+Y rv0)&0x1FF,” par 0043) [15625*(X 1 −X 0) is added to the previous remainder (fractional portion) to compute the new remainder, Yrv1, where 15625 is the predetermined value; this is then added to the fractional portion of the high frequency counter (second counter register)].
Claims 3-5, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Callaway Jr., Myers and Warneke in view of Huggett (US 11,609,539 B2).
Regarding claim 3, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. However, Callaway Jr., Myers and Warneke do not explicitly teach further comprising a scratch register and arranged to derive the value for writing to the second counter register by: copying the value held in the first counter register to the scratch register; multiplying the value held in the scratch register by a first predetermined multiplicand; and copying the multiplied value held in the scratch register to the second counter register.
In the analogous art, Huggett teaches a device further comprising a scratch register and arranged to derive the value for writing to the second counter register (“a logic circuit 1610 of the state machine 200 divides the count value L and the state S by 2.” Col. 9, ll. 4-6 and Figures 7, 8 and 16) [circuit 1610 performs calculations on registers values L and S to derive new scaled values, implying a similar function as a scratch register for this calculation] by:
copying the value held in the first counter register to the scratch register (“the register 1600 of the state machine 200 and the register 1605 of the locked pulses counter 705 are truncated, such that before the locked pulses counter 705 reaches a maximum value or goes back to zero, the logic 1610 of the state machine 200 divides the count value L and the state S by 2” col. 11, ll. 59-64) [the existing values (L and S) from internal registers are used as inputs for calculation by logic circuit, which corresponds to copying to a temporary storage for processing];
multiplying the value held in the scratch register by a first predetermined multiplicand (“a logic circuit 1610 of the state machine 200 divides the count value L and the state S by 2.” Col. 9, ll. 4-6 and Figures 7, 8 and 16) [dividing the count value by 2 is equivalent to multiplying by ½ which may correspond to a first predetermined multiplicand]; and
copying the multiplied value held in the scratch register to the second counter register (“the register 1600 of the state machine 200 and the register 1605 of the locked pulses counter 705 are truncated, such that before the locked pulses counter 705 reaches a maximum value or goes back to zero, the logic 1610 of the state machine 200 divides the count value L and the state S by 2” col. 11, ll. 59-64) [the result of the division is effectively written back into the same registers (register 1600 for state S and register 1605 for count value L) which are then truncated to hold the newly scaled values].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Callaway Jr., Myers, Warneke and Huggett before him before the effective filing date of the claimed invention, to have modified Callaway Jr., Myers and Warneke to incorporate the teachings of Huggett to enable continuous operation of counter registers within a low-power communication system by divide the count values. This allows registers to run without overflowing, which increases the performance of the time-to-digital converter.
Regarding claim 4, Callaway Jr., Myers, Warneke and Huggett teach the device as claimed in claim 3. Huggett further teaches wherein, when the device is in the active state, a first portion of the scratch register comprises a timeout counter register and a second portion of the scratch register comprises a tuning register (“the register 1600 of the state machine 200 and the register 1605 of the locked pulses counter 705 are truncated, such that … the logic 1610 of the state machine 200 divides the count value L and the state S by 2” col. 11, ll. 59-64 and “the output rate of information can be at any arbitrary rate, instead of once per frame, which increases the performance of the TDC 120 because it can adapt more quickly to changes in the scene.” Col. 15, ll. 46-49) [the logic circuit (acting as a scratchpad) calculated values from specific registers in the active state; the increase in performance due to quick adaptations corresponds to the function of a tuning mechanism] (“The auxiliary register 505 may be configured to allow the state machine to undergo one state transition per reception interval whilst preserving the behavior that it has opportunity to lock to later values of counter 115 before earlier ones may be considered. When the state is 1 and no SPAD even occurs when the value of counter 115 equals the range value, the state is decremented to 0 and the auxiliary register 505 is set. …In the next reception interval, the auxiliary register 505 remains set until the count value equals the locked value, after which it is unset.” Col. 5, ll. 1-14) [the auxiliary register manages and limits state transitions based on time-related conditions, corresponding to a timeout mechanism within the active state].
Regarding claim 5, Callaway Jr., Myers, Warneke and Huggett teach the device as claimed in claim 3. Callaway, Jr. further teaches wherein the first predetermined multiplicand comprises a ratio of a resolution of the first counter register to a resolution of the second counter register (“The computation of the new high-frequency counter value uses the ratio between the frequencies at which the high-frequency and low-frequency counters are being clocked, which in this example is 1000000 / 32768 and can be reduced to 15625 / 512” par 0042) [this predetermined ratio, 15625 / 512, is derived from the clock frequencies (which correspond to resolution) of the high-frequency (first) and low-frequency (second) counters].
Regarding claim 7, Callaway Jr., Myers, Warneke and Huggett teach the device as claimed in claim 3. Callaway Jr. further teaches comprising multiplier logic configured, when the device transitions from the sleep state to the active state and after the value held in the first counter register has been copied to the scratch register (“When the wake-up trigger occurs, the high- frequency clock source 230 is re-enabled, …The difference between the low-frequency count value at this … may be multiplied by the ratio of the high- frequency clock source to the low-frequency clock source” par 0031) [this explains the re-enablement from a sleep state and activation of multiplication logic to calculate a new counter value, where initial values would have been stored, under BRI, copied to a scratch like register], to:
add one to the value held in the scratch register to provide a first resultant value (“Consequently f1( ) and f2( ) are defined in this example embodiment as follows: f 1(Y 0 , X 1 , X 0 , Y rv0)=((Y 0<<9)+ 15625 * (X 1 −X 0)+Y rv0)>>9” par 0043) [this is used to compute a new high-frequency counter value, which includes the addition of a previous remainder value (Y rv0) which corresponds to an additive step; the first resultant value is the intermediate sum];
multiply the first resultant value by a ratio of the second frequency to the first frequency to provide a second resultant value (“The computation of the new high-frequency counter value uses the ratio between the frequencies at which the high-frequency and low-frequency counters are being clocked,” par 0042) [ratio is based on first and second clocks for computing a counter value; the second resultant value is Y1; in one embodiment, the ratio can be of the second frequency to the first frequency]; and
write the second resultant value to the scratch register before the value in the scratch register is copied to the second counter register (“The new high-frequency counter value, Y1, is loaded into the high-frequency counter 240, which is then enabled to resume counting at the new high-frequency counter value.” Par 0044 and paragraph 35) [Y1 is loaded into the high frequency counter; the timer control state machine 220 computes Y1 implying a temporary storage/processing area corresponding to a scratch register].
Regarding claim 8, Callaway Jr., Myers, Warneke and Huggett teach the device as claimed in claim 7. Callaway, Jr. further teaches further configured to enable a status bit associated with the second counter register, said status bit indicating whether the value held in the second counter register is valid, on a subsequent cycle of the first clock signal (“Upon the next rising edge of the 32.768 kHz low-frequency oscillator 250 after resumption of the high-frequency oscillator 230, the timer-control state machine 220 performs the following functions … Observes the current counter value of the low-frequency count, X1” par 0035) [machine 220 observes the value X1 (second counter register value) at a specific time; this observation (to determine further calculation) implicitly describes the low frequency counter value is valid at that specific time and ready for calculation’s use].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Callaway Jr., Myers and Warneke in view of Allarey et al. (US 7,953,993 B2).
Regarding claim 12, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. However, Callaway Jr., Myers and Warneke do not explicitly teach further comprising: one or more processor cores each associated with a respective one of a set of one or more owner IDs, the or each processor core being configured to execute instructions associated with a respective one of a plurality of security settings; and a control register having a plurality of bits which are each associated with a respective owner ID and a respective security setting such that the respective bit is configured to be writeable only by a processor core that is associated with said respective owner ID and executing instructions associated with said respective security setting.
In the analogous art, Allarey teaches a device further comprising:
one or more processor cores each associated with a respective one of a set of one or more owner IDs (“Further, each core 320 and 322 includes a core ID 321” col. 8, ll. 60), the or each processor core being configured to execute instructions associated with a respective one of a plurality of security settings (“The normal operational state or active mode for the processor 205 is the C0 state in which the processor actively processes instructions.” Col. 6, ll. 62-64) [the source describes C-states (C0-C6), see Figures 4 and 5, implying different contexts for instruction execution, which under BRI, may correspond to different security levels]; and
a control register having a plurality of bits which are each associated with a respective owner ID and a respective security setting such that the respective bit is configured to be writeable only by a processor core that is associated with said respective owner ID and executing instructions associated with said respective security setting (“the cores 320 and 322 may use a hardware semaphore “C6 order semaphore” to ensure exclusive access to the core identifier 321 field during restore.” Col. 12, ll. 63-65) [the hardware semaphore controls write access to a core identifier field (corresponding to a control register containing bits representing the ID) based on the owner ID during a transition state (i.e. C6) restricting write accesses to ensure proper synchronization; see Figure 5].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Callaway Jr., Myers, Warneke and Allarey before him before the effective filing date of the claimed invention, to have modified Callaway Jr., Myers and Warneke to incorporate the teachings of Allarey to enable the communications systems with various sleep states (i.e. C0-C6) with state integrity enforced by owner ID specific writing controls over specific registers. This would ensure multi-core state synchronization during low-power wakeup and remove the need for microcode reset to restore the states. (Allarey, Col. 17, ll. 1-3)
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Callaway Jr., Myers and Warneke in view of Roth et al. (US 2006/0107077 A1).
Regarding claim 13, Callaway Jr., Myers and Warneke teach the device as claimed in claim 1. However, Callaway Jr., Myers and Warneke do not explicitly teach a device configured to transition from the sleep state to the active state in response to one or more active conditions being met, the active conditions comprising: any bit of a control register being enabled; and/or any of a plurality of event registers being written to; and/or a value held in a compare register being determined to be equal to a value held in the first counter register; and/or the second counter register being read.
In the analogous art, Roth teaches a device configured to transition from the sleep state to the active state in response to one or more active conditions being met (“At block 708, power is applied to a power island in order to cause the power island to begin a transition from a powered down state to a fully operational power state.” Par 0075), the active conditions comprising:
any bit of a control register being enabled (“the counter registers 404 a-404 x are programmable in that their values may be set via a program bus 430, in response to one or more code instructions.” Par 0054) [the modification of values is a condition for power up]; and/or
any of a plurality of event registers being written to (“At block 708, power is applied to a power island” par 0075 and “At block 708, an incrementor (see, e.g., incrementor 420 in FIG. 4) is cleared, such that the value in the incrementor 420 is ready to be “counted up”.” Par 0076 and Figures 3-4) [the clearing of the incrementor corresponds to a write to a register]; and/or
a value held in a compare register being determined to be equal to a value held in the first counter register (“The comparators 410 a-410 x determine whether a current time count, as reflected by an incrementor 420, matches the counter value in its associated register 404 a-404 x.” par 0049) [incrementor 420 corresponds to the first counter register and register 404 corresponds to the compare register; these determine if sufficient time has passed for power up]; and/or
the second counter register being read [the above conditions are met for transitioning from the sleep state].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Callaway Jr., Myers, Warneke and Roth before him before the effective filing date of the claimed invention, to have modified Callaway Jr., Myers and Warneke to incorporate the teachings of Roth to enable power management units as taught by Roth to efficiently resynchronize the high frequency components within a power island by adding conditions required for power up. This secures critical power up timing parameters from unauthorized modifications.
Regarding claim 14, Callaway Jr., Myers, Warneke and Roth teach the device as claimed in claim 13. Roth further teaches further comprising a timeout register (programmable counter register 104 (also 304, 404, 504, 604) and a timeout counter register (incrementor 420/power-down counter), wherein:
the timeout register is configured to hold a predetermined timeout value (“The programmable counter register(s) 104 may each hold a value that represents a minimum power-up time for one or more associated power island(s) 180, 183, 185, 187.” Par 0028) [the predetermined numerical values correspond to a reference points similar to a timeout value];
the timeout counter register is configured to be incremented by the first clock signal when the device is operating in the active state and none of the active conditions are met (“an incrementor (see, e.g., incrementor 420 in FIG. 4) is cleared, such that the value in the incrementor 420 is ready to be “counted up”. For at least one embodiment, the incrementor value is incremented, between blocks 708 and 710, once for each clock cycle.” Par 0076) [this functionality may be adapted to measure inactive periods within an active state]; and
the device is configured to transition from the active state to a transition state in response to a value held in the timeout counter register being determined to be equal to the predetermined timeout value held in the timeout register (“The comparators 410 a-410 x determine whether a current time count, as reflected by an incrementor 420, matches the counter value in its associated register 404 a-404 x.” par 0049) [a comparator checks for equality between a counter’s value and a stored predetermined value, triggering a state change, which corresponds to a timeout event initiating a state transition].
Response to Arguments
Applicant’s arguments, see pages 1-2, filed 10/07/2025, with respect to the rejection(s) of claim(s) 1 and 23 under 35 U.S.C. 103 over Callaway Jr. and Huggett have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Callaway Jr. in view of Myers and in further view of Warneke.
Myers teachings a tuning register that holds an increment value to compensate for changes in the real time count value. Myers further teaches incrementing and decrementing the clock signals by predetermined values and tuning the counter register value based on the value held in the tuning register. Warneke teaches the active and sleep states with the high resolution timer being enabled and disabled for each respective state. Examiner points to the updated mapping of claim 1.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176