DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The response filed 04/24/2026 is accepted, in which, Applicant elects Group II, Species A without traverse, drawn to a high electron mobility transistor, in which claims 25-31 are read thereon. Claim 25 is independent with claims 25-31 awaiting an action on the merits as follows.
Claims 1-24 and 32-39 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/24/2026.
Claim Objections
Claim 25 is objected to for minor informalities.
Regarding claim 25, the claim recites, "a metal gate layer dispose on top…" which appears to be missing a d on the end of dispose. To further prosecution, Examiner will assume the claim should read, "a metal gate layer disposed on the top…" Propre correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25-31 are rejected for indefiniteness.
Regarding claim 25, the claim recites, "a fin structure disposed over and contacting the layer of a second semiconductor material" There is insufficient antecedent basis for the element "the layer of a second semiconductor material" To further prosecution, Examiner will assume the claim should read, "a fin structure disposed over and contacting a layer of a second semiconductor material" Proper correction is required.
Regarding claim 25, the claim recites, "the fin structure being epitaxially grown on the layer of a first semiconductor material" There is improper antecedent basis for "a first semiconductor material" since this element was introduced in the second clause of the claim. To further prosecution, Examiner will assume the claim should read, "the fin structure being epitaxially grown on the layer of the first semiconductor material" Proper correction is required.
Regarding claim 25, the claim recites, "a metal gate layer disposed on top of the fin structure of a first semiconductor material" There is improper antecedent basis for "a first semiconductor material" since this element was introduced in the second clause of the claim. To further prosecution, Examiner will assume the claim should read, "a metal gate layer disposed on top of the fin structure of the first semiconductor material" Proper correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 25-28, and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20150187924 A1), and further in view of the obviousness of range optimization.
Regarding claim 25, Dasgupta teaches a high electron mobility transistor (700, Fig 8) comprising a substrate (101);
a first dielectric layer (760) disposed over (shown over, Fig 7) the substrate (101);
a layer (710) of a first semiconductor material (GaN) disposed over (shown over) and directly contacting (shown directly contacting) the first dielectric layer (760) without (shown without) a separate adhesive layer,
a fin structure (790) disposed over (shown over) and contacting (shown contacting) the layer (730) of a second semiconductor material (AlGaN),
the fin structure (790) being epitaxially grown (epitaxially grown, [0031]) on the layer (710) of a first semiconductor material (GaN);
a metal gate layer (MG: not shown; a gate may be formed on region 780, Fig 8, [0089]) disposed on top (shown on top) of the fin structure (790) of a first semiconductor material (GaN);
a source disposed (770) over (shown over) the fin structure (790) and positioned at a first side (right) of the metal gate layer (MG); and
a drain (D: not shown; another junction region may be formed on the other end of the transistor, [0090]) disposed over (shown over) the fin structure (790) and positioned at a second side (left) of the metal gate layer (MG), the first side (right) being an opposite (shown opposite) side to the second side (left).
In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. The specification is silent to the criticality of the defect density of the first semiconductor material as claimed in claim 25. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553, 555, 188 USPQ 7, 9 (CCPA 1975).
Dasgupta discloses the claimed invention except for the layer of a first semiconductor material having a defect density of 106 defects/cm2 or less.
Dasgupta does teach designing a GaN layer stack to have a "low enough" defect density in paragraph [0015] and goes on to teach the GaN layer or stack has a defect density of less than 109 defects/cm2 in paragraph [0044].
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include the layer of a first semiconductor material having a defect density of 106 defects/cm2 or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 26, Dasgupta teaches the transistor of claim 25 and goes on to teach further comprising an array (array shown, Fig 7) of fin structures (790) each having a metal contact position (780, Fig 8) on the top (shown on top) thereof.
Regarding claim 27, Dasgupta teaches the transistor of claim 25 and goes on to teach wherein first semiconductor material (GaN) is a III-V material (GaN, well known in the art as a III-V material).
Regarding claim 28, Dasgupta teaches the transistor of claim 27 and goes on to teach wherein the III-V material (GaN) is gallium nitride.
Regarding claim 30, Dasgupta teaches the transistor of claim 27 and goes on to teach wherein the second semiconductor material (GaN; in some cases, 710 includes 1 or more layers described for layer 110; layer 110 is shown in Fig 2 to comprise several layers of GaN, therefore it would have been obvious to one of ordinary skill in the art to have the second semiconductor layer be GaN) is gallium nitride.
Regarding claim 31, Dasgupta teaches the transistor of claim 27 and goes on to teach wherein the second semiconductor material (AlGaN) is aluminum gallium nitride.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20150187924 A1), and further in view of Rachmady (US 20180158957 A1).
Regarding claim 29, Dasgupta teaches the transistor of claim 27 but fails to explicitly teach the III-V material is indium phosphide.
However, Rachmady teaches a first group II-V compound semiconductor comprising InP in paragraph [0031].
Dasgupta and Rachmady are considered analogous to the claimed invention because both are from the same field of endeavor of HEMT devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Dasgupta with the features of Rachmady to create a transistor wherein the III-V material is indium phosphide so that greater electrical isolation between source and drain ends of the fin structure may improve the short channel effect of a non-silicon transistor utilizing fin material as a gate electrode-coupled conduction channel (Rachmady, [0022]) since sub-fin material 110 may help to accommodate lattice mismatch between the materials selected for fin material and substrate, and/or provide junction isolation fin material and substrate (Rachmady, [0031]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Higuchi (US 20180219086 A1) - GaN transistor, no fins
Mohapatra (US 20180254332 A1) - epitaxial grown fin
Flynn (US 20130193444 A1) - defect density of GaN layers
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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