Prosecution Insights
Last updated: April 19, 2026
Application No. 18/579,443

INTEGRATED MAGNETO-OPTICAL MODULATOR

Non-Final OA §102§103§112
Filed
Jan 15, 2024
Examiner
CAPUTO, LISA M
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
The Regents of the University of California
OA Round
1 (Non-Final)
8%
Grant Probability
At Risk
1-2
OA Rounds
2y 2m
To Grant
0%
With Interview

Examiner Intelligence

Grants only 8% of cases
8%
Career Allow Rate
3 granted / 38 resolved
-60.1% vs TC avg
Minimal -8% lift
Without
With
+-7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
22 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 38 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Preliminary Amendment Receipt is acknowledged of the preliminary amendment filed January 15, 2024. Claim Objections Claims 15 and 18 are objected to because of the following informalities: Regarding claim 15 line 3 and claim 18 line 3, the claim recites “pattering” which seems to be a typographical error, it appears as though the word should be “patterning.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 recites the limitation "via a second" in line 5. There is indefinite because there is no second object claimed. From reading the claim, it appears that the limitation should read “via a second microstrip” and that is how the claim will be interpreted for examination purposes. Further “second microstrip” appears in lines 7-8 and this currently does not have antecedent basis in the claim. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 and 9-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pintus et al., Journal of Lightwave Technology “Micro-ring-Based Optical Isolator and Circulator with Integrated Electromagner for Silicon Photonics”, from hereinafter “Pintus”. As per claim 1, Pintus discloses an optical modulator (current induced magnetic field modulated magneto-optic devices for silicon photonics; Conclusion, page 1435) comprising: a first optical waveguide including an input port configured to receive an unmodulated optical signal and an output port (an optical isolator using a waveguide having an input and output as shown in figure 1a propagates a light signal, e.g., a non-modulated laser signal; figure 1; section III, page 1432; page IIIA, page 1433); a magneto-optical layer located adjacent to the first optical waveguide, wherein optical attributes of the magneto-optical layer vary in relation to a magnetic field (a magneto-optic garnet layer is bonded on a SOI wafer having a first patterned waveguide and an external magnetic field induces a nonreciprocal phase shift effect in the magneto-optic Ce:YIG garnet layer; figures 1a,b; sections II, IIB, page 1430); and a conductive layer located in close proximity to a portion of the magneto-optical layer located adjacent to the first optical waveguide, wherein current injected to the conductive layer generates a magnetic field oriented perpendicular to a direction of propagation of light within the first optical waveguide (a silicon layer is conductive and the magneto-optic Ce:YIG gamet layer is bonded onto the silicon-on-insulator SOI wafer having patterned first waveguides, wherein injected current induces a magnetic field using the Voigt configuration such that the magnetic field is perpendicular to the propagating direction of light which exhibits a different phase velocity according to the propagation direction, therefore achieving the nonreciprocal phase shift effect; figures 1a,b, 5a; section I, page 1429; sections I, II, page 1430; section IIC, page 1431). Regarding claim 2, Pintus discloses the optical modulator of claim 1, further comprising a micro-ring optically coupled to the first optical waveguide, the microring configured to modulate the unmodulated optical signal (a silicon microring resonator is fabricated on a SOI wafer including a fully etched silicon waveguide as shown in figure 1, wherein the integrated optical device current induced magnetic field can be switched and modulated; figure 1a,b; section IIB, page 1430; section V, page 1435). Regarding claim 3, Pintus discloses the optical modulator of claim 2, wherein a cross-section of the microring is vertically discontinuous (as shown in figure 1a, a silicon microring resonator is fabricated on a SOI wafer, and the microring is bonded with a Ce:YIG garnet grown on a substituted gadolinium gallium garnet SGGG wherein the remaining space is filled by air, the stacked layers thus depicted as vertically discontinuous in the air filled space cross sectional view shown in figure 1b; figure 1a,b; section II B, page 1430). Regarding claim 4, Pintus discloses the optical modulator of any one of claims 2-3, wherein the conductive layer comprises conductive tabs and a conductive ring, wherein the conductive ring is positioned adjacent to the microring (in a fully etched silicon waveguide design, the conductive silicon layer is patterned to include tabs and the ring in an aligned integrated chip device fabrication as shown in figure 1; figure 1a,b; section II, IIB, page 1430). Regarding claim 9, Pintus teaches that the optical modulator comprises a first magneto-optic material and a second magneto-optic material different from the first magneto-optic material (see page 1430, section IIB). Regarding claim 10, Pintus teaches wherein the first magneto-optic material is gadolinium gallium garnet (GGG) and the second magneto optic material is cerium substituted yttrium iron garnet (Ce:YIG) (see page 1430, section IIB). Although Pintus teaches SGGG instead of GGG, it is well known in the art that SGGG is an art recognized equivalent and can be used with similar results. Regarding claim 11, Pintus teaches that the first optical waveguide 11 is positioned on an insulating layer (resonator is fabricated on an SOI wafer, see page 1430, section IIB). Regarding claim 12, Pintus teaches wherein the insulating layer is positioned on a silicon substrate (resonator is fabricated on an SOI wafer, see page 1430, section IIB). Regarding claim 13, Pintus teaches wherein the output port is configured to output a modulated optical signal (see page 1433). Regarding claim 14, Pintus teaches wherein the optical modulator operates in a transverse electric (TE) mode (see page 1435, Conclusion). Regarding claim 15, Pintus discloses a method of manufacturing the optical modulator of claim 1 (fabricating current induced magnetic field modulated magneto-optic devices for silicon photonics; Abstract; Conclusion, page 1435) comprising: depositing a silicon layer onto an insulating layer (manufacturing a silicon layer of a silicon-on-insulator SOI wafer; section II; page 1430); patterning a waveguide in the silicon layer (waveguides are patterned on the silicon layer; section II, page 1430); bonding a magneto-optic material to the waveguide (a magneto-optic garnet layer is bonded on a SOI wafer having a first patterned waveguide; figures 1a,b; sections II, IIB, page 1430); depositing an oxide cladding layer (silica SiO2, thus a cladding, deposited on the SOI wafer; figure 1a,b; section II, page 1430); removing a portion of the magneto optic material (removing the areas of the bonded chip that are not covering the micro-ring, including the Ce:YIG magneto-optic garnet as shown in figure 1a,b; section IVA, page 1435); and depositing a conductive layer in alignment with the waveguide (a metallic micro-strip aligned with the device underneath is fabricated above the chip including the waveguide; figures 1a,b; section II; page 1430). Regarding claim 16, Pintus discloses the method of claim 15 wherein the magneto-optic material includes a magneto-optic substrate and a layer of magneto-optic material, wherein the magneto-optic material is different from the magneto-optic substrate (the micro-ring is bonded with a substituted gadolinium gallium garnet SGGG substrate and a layer of Ce:YIG garnet; section IIB, page 1430). Regarding claim 17, Pintus discloses the method of claim 16, wherein the magneto optic substrate is gadolinium gallium garnet GGG and the magneto-optic material is cerium substituted yttrium iron garnet Ce:YIG (the micro-ring is bonded with a substituted gadolinium gallium garnet SGGG substrate and a layer of Ce:YIG garnet; section IIB, page 1430). Regarding claim 18, Pintus discloses a method of manufacturing an optical modulator (fabricating current induced magnetic field modulated magneto-optic devices for silicon photonics; Abstract; Conclusion, page 1435) comprising: depositing a silicon layer onto an insulating layer (manufacturing a silicon layer of a silicon-on-insulator SOI wafer; section II; page 1430); patterning a waveguide in the silicon layer (waveguides are patterned on the silicon layer; section II, page 1430); bonding a magneto-optic material to the waveguide (a magneto-optic garnet layer is bonded on a SOI wafer having a first patterned waveguide; figures 1a,b; sections II, IIB, page 1430); depositing an oxide cladding layer (silica SIO2, thus a cladding, deposited on the SOI wafer; figure 1a,b; section II, page 1430); removing a portion of the magneto optic material (removing the areas of the bonded chip that are not covering the microring, including the Ce:YIG magneto-optic garnet as shown in figure 1a,b; section IVA, page 1435); and depositing a conductive layer in alignment with the waveguide (a metallic micro-strip aligned with the device underneath is fabricated above the chip Including the waveguide; figures 1a,b; section II; page 1430). Regarding claim 19, Pintus discloses the method of claim 18 wherein the magneto-optic material includes a magneto-optic substrate and a layer of magneto-optic material, wherein the magneto-optic material is different from the magneto-optic substrate (the micro-ring is bonded with a substituted gadolinium gallium garnet SGGG substrate and a layer of Ce:YIG garnet; section IIB, page 1430). Regarding claim 20, Pintus discloses the method of claim 19, wherein the magneto optic substrate is gadolinium gallium garnet GGG and the magneto-optic material is cerium substituted yttrium iron garnet Ce:YIG (the micro-ring is bonded with a substituted gadolinium gallium garnet SGGG substrate and a layer of Ce:YIG garnet; section IIB, page 1430). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Pintus as applied to claim 1 above, and further in view of Schaffner et al. (US Patent No. 5,208,697, from hereinafter “Schaffner”). Regarding claim 5, Pintus discloses the optical modulator of claim 1, wherein the conductive layer is configured as a coupled waveguide to modulate the unmodulated optical signal (a silicon layer is a conductive layer of the SOI wafer having patterned waveguides coupled via induced magnetic field using the Voigt configuration, the fabricated optical isolator as shown in figure 1a propagates a light signal, e.g., a non-modulated laser signal; figures 1a,b; sections I, II, page 1430; section III, page 1432). However, Pintus fails to specifically teach a microwave-waveguide. Schaffner discloses a microwave-waveguide (a coplanar waveguide 24 for coupling an input microwave frequency electrical signal to the optical waveguide 14 to modulate the optical signal; figures 1-3; column 4, lines 28-38). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a microwave frequency waveguide as taught by Schaffner within the device as disclosed by Pintus in order to enable the modulator to operate with smooth frequency response over a wide range of microwave input frequencies (see Schaffner Abstract). Regarding claim 6, Pintus in view of Schaffner discloses the optical modulator of claim 5, and Pintus further teaches further comprising a second optical waveguide including an input port configured to receive an unmodulated optical signal and an output port (two identical optical isolators are cascaded, as shown in figure 9, and light propagates from IN-port to OUT-ports cascaded, the fabricated optical isolator propagates, e.g., a non-modulated laser signal; Pintus figures 1a,b, 9; sections I, 11, page 1430; section III, page 1432; section IIIB, page 1433). Regarding claim 7, Pintus in view of Schaffner discloses the optical modulator of claim 6. Schaffner further teaches wherein the microwave-waveguide comprises: a first RF signal generator pad coupled to a first RF load pad via a first microstrip (the first pad shaped input section 28 of the coplanar waveguide 24, as best shown in figure 2 depicting a Chebyshev design, provides microwave signal input generated via transformer 50, and is similarly coupled to a first pad shaped microwave frequency output section 32 which is loaded by a similar output impedance transformer 60 via the first microstrip line 38; figures 1-3; column 5, lines 3-35). Although Schaffner lacks the specific teaching of a second RF signal generator pad coupled to a second RF load pad via a second microstrip, wherein the second RF signal generator pad is separated from the first RF signal generator pad, the second RF load pad is separated from the first RF load pad, and the second microstrip is separated from and parallel to the first microstrip, Pintus discloses cascaded optical modulator devices having identical components (two identical optical isolators are cascaded, as shown in figure 9; Pintus figures 1a,b, 9; sections I, II, page 1430; section III, page 1432; section IIIB, page 1433). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Pintus in view of Schaffner to duplicate components in a cascaded topology such that a second RF signal generator pad coupled to a second RF load pad via a second microstrip, wherein the second RF signal generator pad is separated from the first RF signal generator pad, the second RF load pad is separated from the first RF load pad, and the second microstrip is separated from and parallel to the first microstrip, in order to enable the modulator to operate with smooth frequency response over a wide range of microwave input frequencies (Schaffner Abstract). Moreover, it has been held that a mere duplication of essential working parts of a device involves only routine skill in the art. Regarding claim 8, Pintus in view of Schaffner discloses the optical modulator of claim 7, wherein Pintus further teaches that the first microstrip is positioned above the first optical waveguide and the second microstrip is positioned above the second optical waveguide (using direct wafer bonding, optical isolators and circulators are manufactured on a SOI wafer wherein the waveguides are patterned on the silicon layer, and next a metallic micro-strip aligned with the device underneath is fabricated above the chip, and moreover, the basic structure shown in Figure 1 can be cascaded as shown in figures 9 and 10 and thus achieves the component topology; Pintus figures 1a,b, 9, 10; sections I, II, page 1430; section III, page 1432; section IIIB, page 1433). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent No. 5,005,932 to Schaffner et al. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
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Prosecution Timeline

Jan 15, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
8%
Grant Probability
0%
With Interview (-7.9%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 38 resolved cases by this examiner. Grant probability derived from career allow rate.

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