DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of U.S. Patent No. 7,042,330 (to Nakamura et al.). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Nakamura teaches the metal strip (electrodes) contacting the end portions of the resistor body to form a clad structure, wherein the metal strip is affixed to the resistor body by thermal diffusion bonding.
Above claimed limitations are equivalent to the electrodes being connected to the resistor body by diffusion bonding recited in claims 1 and 2 of the current invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuda et al., US Pub. 2016/0133362.
Regarding claims 1-2 and 5, Tsuda teaches a built-in chip resistor for a substrate having a plate shape (the rectangular shaped resistor built-in within insulating layers 12 and 12a [substrate]; see at least figs. 4-5 and paragraph 0071-0074) comprising:
a resistance body (resistive element 15);
a first electrode (first electrode 13 may be formed by cladding; see paragraph 0105) bonded to a first end of the resistance body with a first clad portion;
a second electrode (second electrode 13) bonded to a second end of the resistance body with a second clad portion; and wherein
the first clad portion is a bonded portion where the material forming the resistance body
and the material forming the first electrode are diffusion bonded (resistive element and the electrodes are of the same material and are diffusion bonded to each other; see paragraphs 0066 and 0075-0076), and
the second clad portion is a bonded portion where the material forming the resistance
body and the material forming the second electrode are diffusion bonded.
Regarding claim 3, Tsuda teaches the built-in chip resistor for the substrate according to claim 1, wherein a difference between a most protruded part and a most depressed part on a first surface of the chip resistor (protrusion/depression difference is between the resistive element 11 and the electrode 13 on the upper surface of the resistive element; see fig. 5B) being equal to or greater than 0 µm and equal to or less than 100 µm (the electrodes 13 have a thickness between 10 to 100 µm; see paragraph 0130) in a region extending from a first connection region provided for a part of the first electrode (the connection region of the electrode 13 to the resistive element 11) to a second connection region provided for a part of the second electrode.
Regarding claims 4 and 7, resistive element 15 is trimmed to form a recess (recess 16 formed; see figs 5C-5D and paragraph 0072) on the second surface (opposite the electrode surface) towards the first surface, the trimming for the purpose of reducing the resistive element.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirabayashi et al., US Pub. 2021/0181036.
Regarding claim 1, Hirabayashi teaches a built-in chip resistor for a substrate having a plate shape (“built-in” process shown in figs. 10 and 11, the built-in steps starts from paragraph 0099) comprising:
a resistance body (resistance body 14; paragraph 0071);
a first electrode bonded to a first end of the resistance body with a first clad portion (bonding electrode 16 diffusion bonded to the resistive element 14) ; and
a second electrode bonded to a second end of the resistance body with a second clad
portion.
Regarding claim 6, Hirabayashi teaches the manufacturing method of resistor built-in module into which the built-in chip resistor for the substrate according to claim 1 is built (the built-in step starts in paragraph 0099), the method comprising:
a layer forming step of forming a first layer (sheet 106) and a second layer (sheet 102) so as to sandwich the chip resistor (“hot pressed”; paragraph 0100);
a through hole forming step of forming a first through hole reaching the first electrode in
at least one of the first layer and the second layer (through holes, by reference number 24a, allows for diffusion bonding; see paragraph 0089) and forming a second through hole reaching the second electrode in at least one of the first layer and the second layer; and
a filling step of filling an electrically conductive material into the first through hole and
the second through hole (conductive material filling the through hole; see paragraph 0104).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at 571-272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYUNG S LEE/Primary Examiner, Art Unit 2831
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