Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s filing of claims 1-20 on 1/16/24 is acknowledged. Claims 1-20 are pending and are under examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/9/24 was acknowledged. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over LV et al. (“LV,” US Pub. No. 2020/0171491) in view of Cui et al. (“Cui,” US Pub. No. 2021/0322973).
As to claim 1, LV discloses microfluidic substrate, comprising: a base substrate (e.g., 102); and a conductive layer arranged on the base substrate, wherein patterns of the conductive layer comprise one or more electrode patterns and one or more trace patterns (e.g., [0070] et seq.); wherein an orthogonal projection (e.g., [0015] et seq.) of at least a portion of each trace pattern onto the base substrate is on one side of an orthogonal projection of a corresponding electrode pattern onto the base substrate. See e.g., [0032] et seq.
Regarding claim 1, LV does not specifically disclose a minimum spacing of greater than or equal to 4 micrometers from an outer contour of the corresponding electrode pattern. Cui discloses the spacing between the first electrode and the second electrode being about 10 μm to about 50 μm in [0042]. It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have the specific spacing because it would allow for the shape and size of the electrode pattern to be designed according to a particular need (e.g., [0040] of Cui).
As to claim 2, the combination of LV and Cui disclose an outer contour of each of at least a portion of the electrode patterns comprises an arc portion, and a minimum spacing between an orthogonal projection of at least a portion of a corresponding trace pattern onto the base substrate and an orthogonal projection of the arc portion onto the base substrate is greater than or equal to 4 micrometers. See [0040] of Cui.
As to claim 3, the combination of LV and Cui disclose the electrode patterns comprise a plurality of first electrodes spaced apart from each other and a plurality of second electrodes spaced apart from each other, wherein the trace patterns comprise a plurality of first traces, at least one of the first electrodes is coupled to at least one of the second electrodes via a corresponding one of the first traces. See [0070] et seq. of LV and [0040] of Cui.
As to claim 4, the combination of LV and Cui disclose a dielectric layer covering one side of the conductive layer away from the base substrate; a hydrophobic layer covering one side of the dielectric layer away from the base substrate; wherein an orthogonal projection of the hydrophobic layer onto the base substrate coincides with orthogonal projections of the second electrodes onto the base substrate, and an orthogonal projection of at least a portion of the first electrodes onto the base substrate is located outside orthogonal projections of the dielectric layer and the hydrophobic layer onto the base substrate, to enable the at least a portion of the first electrodes to be exposed to a surface of the microfluidic substrate. See [0070] et seq. of LV and [0046] of Cui.
As to claim 5, the combination of LV and Cui disclose the trace patterns further comprise one or more second traces, one end of each second trace is coupled to one of the second electrodes, and the other end thereof is a floating end. See [0070] et seq. of LV and [0046] of Cui.
As to claim 6, the combination of LV and Cui disclose the electrode patterns further comprise one or more third electrodes each located on one side of and spaced apart from the floating end. See [0070] et seq. of LV and [0046] of Cui.
As to claim 7, the combination of LV and Cui disclose the floating end is spaced apart from the third electrode by less than or equal to 20 micrometers. See [0070] et seq. of LV and [0042] of Cui.
As to claim 8, the combination of LV and Cui disclose a middle region and a peripheral region located at a periphery of the middle region, and the one or more electrode patterns and the one or more trace patterns are located in the middle region; the patterns of the conductive layer further comprise an outer-charge shielding region located at the peripheral region to surround the middle region. See [0070] et seq. of LV and [0046] of Cui.
As to claim 9, the combination of LV and Cui disclose a distance between the outer-charge shielding region and a peripheral edge of the base substrate is greater than or equal to 5 mm. See [0070] et seq. of LV and [0042] of Cui.
As to claim 10, the combination of LV and Cui disclose the patterns of the conductive layer further comprise a charge neutralization region, an orthogonal projection of the charge neutralization region onto the base substrate is located in the middle region with a spacing from an orthogonal projection of the outer-charge shielding region onto the base substrate, the charge neutralization region comprises a covering portion and an opening portion, a pattern of at least a part of the opening portion has a same shape as at least one electrode pattern and at least one trace pattern, and the covering portion covers at least an area in the middle region except the one or more electrode patterns and the one or more trace patterns, and the covering portion is insulated from at least a portion of the electrode patterns and the trace patterns. See [0070] et seq. of LV and [0042] of Cui.
As to claim 11, the combination of LV and Cui disclose the covering portion is spaced apart from the electrode patterns and the trace patterns that are insulated from the covering portion by a distance of greater than or equal to 25 micrometers. See [0070] et seq. of LV and [0042] of Cui.
As to claim 12, the combination of LV and Cui disclose the orthogonal projection of the charge neutralization region onto the base substrate is spaced apart from the orthogonal projection of the outer-charge shielding region onto the base substrate by a distance of greater than or equal to 20 micrometers. See [0015] et seq. of LV and [0042] of Cui.
As to claim 13, the combination of LV and Cui disclose the electrode patterns further comprise a plurality of fourth electrodes disposed in a floating manner, the charge neutralization region is electrically connected to at least one of the fourth electrodes, and at least a part of the fourth electrodes is exposed to a surface of the microfluidic substrate. See [0015] et seq. of LV and [0042] of Cui.
As to claim 14, the combination of LV and Cui disclose at least one first electrode is a driving electrode for driving a droplet to move; at least one second electrode is a signal terminal electrode for applying an electric signal to the driving electrode. See [0004] et seq. of LV and [0042] of Cui.
As to claims 15 and 16, the combination of LV and Cui disclose a microfluidic chip, comprising a first substrate and a second substrate arranged opposite to each other to form a cell, wherein a sample flow channel is formed between the first substrate and the second substrate; wherein the microfluidic substrate according to claim 1 is used as the first substrate. See [0015] et seq. of LV and [0042] of Cui.
As to claim 17, the combination of LV and Cui disclose an outer contour of each of at least a portion of the electrode patterns comprises a sharp portion, and a minimum spacing between an orthogonal projection of at least a portion of a corresponding trace pattern onto the base substrate and an orthogonal projection of the sharp portion onto the base substrate is greater than or equal to 25 micrometers. See [0070] et seq. of LV and [0042] of Cui.
As to claim 18, the combination of LV and Cui disclose an outer contour of each of at least a portion of the electrode patterns comprises a linear portion, and a minimum spacing between an orthogonal projection of at least a portion of a corresponding trace pattern onto the base substrate and an orthogonal projection of the linear portion onto the base substrate is greater than or equal to 20 micrometers. See [0070] et seq. of LV and [0040] of Cui.
As to claim 19, the combination of LV and Cui disclose an outer contour of each of at least a portion of the electrode patterns comprises an arc portion, and a minimum spacing between an orthogonal projection of at least a portion of a corresponding trace pattern onto the base substrate and an orthogonal projection of the arc portion onto the base substrate is greater than or equal to 4 micrometers. See [0070] et seq. of LV and [0042] of Cui.
As to claim 20, the combination of LV and Cui disclose an outer contour of each of at least a portion of the electrode patterns comprises a sharp portion, and a minimum spacing between an orthogonal projection of at least a portion of a corresponding trace pattern onto the base substrate and an orthogonal projection of the sharp portion onto the base substrate is greater than or equal to 25 micrometers. See [0070] et seq. of LV and [0040] of Cui.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LORE RAMILLANO JARRETT whose telephone number is (571)272-7420. The examiner can normally be reached Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lyle Alexander can be reached at 571-272-1254.
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/LORE R JARRETT/Primary Examiner, Art Unit 1797
5/30/26
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