Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1 –
Claim 1 contains the phrase “and/or”, which is not explicitly defined in either the claims or specification, therefore a person of ordinary skills would not be able to determine the metes and bound of these claims.
Appropriate correction is required for clarity of the record.
For the purpose of compact prosecution of this application, Examiner will interpret the term “and/or” as being “or”.
Regarding claim 6 –
Claim 6 contains the phrase “for exact one cycle”, which appears to be a translation or typographical error. For the purpose of compact prosecution, Examiner will interpret the intended phrase as “for exactly one cycle”.
In addition to these two claims, Examiner also rejects all claims which depend from them under 112(b); as a result, claims 2-11 (which depend from claim 1) are also rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 - 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication 20210303393-(Eckhardt et al.) [herein “Eckhardt”].
Regarding claim 1 –
Eckhardt teaches (a) data storage circuit comprising; (Fig 2)
Eckhardt also teaches a plurality of configuration registers onfigured to store configuration data (Fig 2, Item 232) plus “The contents of the PHY configuration registers are determined by design” (page 3, Paragraph [0029]) plus “The microcontroller 210 loads the PHY register image into the PHY registers 232 during system initialization” (page 3, Paragraph [0030]).
In addition, Eckhardt teaches an error detection unit (Fig 2, Item 234) plus “A checksum checker 234 is coupled to the register set 232” (Page 3, Paragraph [0032]).
Eckhardt also teaches configured to detect errors in the configuration data “During runtime, the checksum checker 234 can verify the PHY register contents by reading the selected registers or the complete register set 232, calculating a current value of the checksum for those registers, and comparing the current checksum to the saved checksum in the checksum register 238” (Page 3, Paragraph [0032]).
Additionally, Eckhardt teaches and , (Fig 1) plus (Fig 2) plus “The decision of whether a given register is to be protected by register lock 120, checksum 130, and/or ECC 140 can be made at design time (e.g. when the PHY is designed and/or fabricated). In some instances, that decision can even be made for some registers at runtime ( e.g. when the PHY is actually operating). If the register participation decision is made at design time, either all of the registers can be selected, or else a selection bit can be added to the register providing a second selection point at runtime, as well as an opportunity to include a subset of the registers in the protection method. Any given register can be protected by one, two, or all three of protection schemes 120, 130 and 140” (Page 2, Paragraph [0020]).
Regarding claim 2 –
Eckhardt teaches all the limitations of claim 1 above.
Eckhardt also teaches comprising configured configured to store the generated parity bit “Parity or ECC 140 can be used for protection of important configuration registers in the PHY that could be overwritten by a software glitch, noise, ESD spike, radiation introducing soft errors (SER), or similar issues. Parity refers to the evenness or oddness of the number of bits having a value of one within a given set of bits, and is thus determined by the value of all the bits. The parity bit checks whether the total number of I-bits in the string is even for even parity or odd for odd parity. Parity can be calculated by an exclusiveOR (XOR) sum of the bits, yielding a O for even parity or a 1 for odd parity. Incorrect register contents can be detected with the addition of one or two parity bits to each register that is to be protected in this manner” (Page 2, Paragraph [0024]).
In addition, Eckhardt teaches wherein the error detection units are configured to read out the stored parity bit , “A selection of whether a given register will be protected by parity or ECC 140 can be made at design time or at runtime. This selection can also include whether 1-bit parity, 2-bit parity, or an ECC algorithm will be used. In some cases where ECC is used, a code describing the data bit sequence is calculated and stored along with the data. When the data is read, an ECC code for the read data is calculated and compared to the original ECC code. If the codes match, the data is deemed to be uncorrupted.” (Page 2, Paragraph [0025]).
Regarding claim 3 –
Eckhardt teaches all the limitations of claim 1 above.
Eckhardt also teaches wherein configured to detect errors by use of an error correction code “A selection of whether a given register will be protected by parity or ECC 140 can be made at design time or at runtime. This selection can also include whether 1-bit parity, 2-bit parity, or an ECC algorithm will be used. In some cases where ECC is used, a code describing the data bit sequence is calculated and stored along with the data. When the data is read, an ECC code for the read data is calculated and compared to the original ECC code. If the codes match, the data is deemed to be uncorrupted.” (Page 2, Paragraph [0025])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 - 11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20210303393-(Eckhardt et al.) [herein “Eckhardt”], in view of U.S. Patent Publication 20190227867-(Ellur).
Regarding claim 4 –
Eckhardt teaches all the limitations of claim 1 above.
Eckhardt does not teach wherein
Ellur, however teaches wherein , (Fig 1, Item 100 “Random Fault Detector”) plus “A fault detection circuit generates a current parity bit for configuration data currently stored in a configuration register during each clock cycle, and compares the current parity bit with a previous parity bit generated during a previous clock cycle. An error signal is asserted when a mismatch is detected” (Abstract) plus “During the parity update mode, the data source selection control signal is de-asserted in response to assertion of the register input control signal, thereby controlling the parity multiplexer to pass new (updated) configuration data from the register input signal lines to the parity calculator before the new configuration data is written into the configuration register, which in tum causes the parity calculator to generate a current parity bit value based on the even/odd parity defined by the new configuration data.” (Page 2, Paragraph [0009]).
Eckhardt and Ellur are analogous art because they are both directed to advanced methods of checking and correcting the content of configuration registers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the configuration register checking of Eckhardt with the parity-based checking scheme of Ellur, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide checking and correction of configuration register data with minimal additional memory requirements.
Regarding claim 5 –
The combination of Eckhardt and Ellur teaches all the limitations of claim 4 above.
Ellur also teaches wherein configured to store the parity bit , (Fig 1) plus “Random fault detector circuit l00C includes parity multiplexer 180, parity bit-pair generator 120, comparator 140, and output drive 170 that are configured and operate during parity update mode and parity validation mode operations” (Page 9, Paragraph [0047]).
Regarding claim 6 –
The combination of Eckhardt and Ellur teaches all the limitations of claim 5 above.
Ellur also teaches comprising configured to generate a clock signalonfigured to store the configuration end signal, (Fig 1) plus “Parity bit-pair generator 120 is configured to sequentially generate parity bits, indicated by parity bits PB[Ti] and PB[Ti+1] respectively having associated parity bit values that are determined by the configuration data byte stored in configuration register 90 during sequential cycles Ti and Ti+1 of system clock signal CLK. That is, parity bit-pair generator 120 is configured to sample the configuration data bit values transmitted onto register output signal lines RB-OUT once during each clock cycle, and to generate a pair of parity bits that include a current (first) parity bit PB[Ti+1] generated during a current (first) clock cycle CLK=Ti+1, and a previous (second) parity bit pair PB[Ti] generated during a previous (second) clock cycle CLK=Ti (i.e., previous clock cycle CLK=Ti represents the clock cycle of system clock signal CLK that occurred immediately before current clock cycle CLK=Ti+1)” (Page 5, Paragraph [0030]) Examiner notes that alternative schemes for clocking data into registers such as described here are well known in the art.
Regarding claim 7 –
The combination of Eckhardt and Ellur teaches all the limitations of claim 4 above.
Ellur also teaches wherein , (Fig 1) plus “Parity register 124 has an input terminal 124I connected to output terminal 1220 of parity calculator circuit 122 and is configured (e.g., using flip-flop FF 125) to store a previous parity bit value PV 127 (i.e., a parity bit generated during the last cycle of system clock signal CLK)…” (Page 6, Paragraph [0034]).
Regarding claim 8 –
Eckhardt teaches all the limitations of claim 1 above.
Eckhardt does not teach wherein is configured to provide.
Ellur, however teaches wherein is configured to provideunits. Ellur – (Fig 1) plus “Accordingly, because a mismatch is detected while a configuration update operation is not being performed, output driver 170A generates error signal ERR as a logic-I value, which effectively alerts the failure response circuit that a random hardware fault has occurred in the configuration register that produced configuration byte RB-OUT[T5]” (Page 7, Paragraph [0041]).
Eckhardt and Ellur are analogous art because they are both directed to advanced methods of checking and correcting the content of configuration registers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the configuration register checking of Eckhardt with the parity-based checking scheme of Ellur, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide checking and correction of configuration register data with minimal additional memory requirements.
Regarding claim 9 –
The combination of Eckhardt and Ellur teaches all the limitations of claim 8 above.
Ellur also teaches wherein is configured to provide, (Fig 3C) plus “FTG. 3C: depicts random fault detector 1 00A during a subsequent time/clock cycle T3 when parity register 124 stores parity bit PB[T2], register output signal lines RBOUT carry a four-bit byte value "1011", and register input control signal RIC is asserted, indicating that a configuration update operation is being performed at time T3. The odd parity of the byte transmitted on register output signal lines RB-OUT[T3] causes parity calculator 122 to generate a current parity bit PB[T3] having a logic-I value. Because the two values PB[T3] and PB[T2] applied to the input terminals of comparator 140A are different at time T3, mismatch signal MISMATCH is asserted (logic-I). Because register input control signal RIC is asserted (logic- I), detection enable circuit (inverter logic gate) 161 de-asserts output enable signal ERR_EN, thereby disabling output driver 170A and again preventing the generation of a false error signal” (Page 7, Paragraph [0039]).
Regarding claim 10 –
The combination of Eckhardt and Ellur teaches all the limitations of claim 9 above.
Ellur also teaches comprising onfigured to disable the provision of error flags, “Because the two values PB[T0] and PB[Tl] applied to comparator (exclusive-OR logic gate) 140A are different, mismatch signal MISMATCH is asserted (logic- I). However, because register input control signal RIC is asserted (logic-I), which causes detection enable circuit (inverter logic gate) 161 to generate output enable signal ERR_EN as a logic-0 signal value. Accordingly, even though mismatch signal MISMATCH is asserted, output driver 170A is effectively disabled by output enable signal ERR_EN, thereby preventing the generation of a false error signal (i.e., error signal ERR is generated as a logic-0 signal value)” (Page 7, Paragraph [0037]).
Regarding claim 11 –
Eckhardt teaches all the limitations of claim 1 above.
Eckhardt does not teach wherein
Ellur, however teaches wherein , (Fig 1) plus “Parity bit-pair generator 120 is configured to sequentially generate parity bits, indicated by parity bits PB[Ti] and PB[Ti+I] respectively having associated parity bit values that are determined by the configuration data byte stored in configuration register 90 during sequential cycles Ti and Ti+I of system clock signal CLK. That is, parity bit-pair generator 120 is configured to sample the configuration data bit values transmitted onto register output signal lines RB-OUT once during each clock cycle, and to generate a pair of parity bits that include a current (first) parity bit PB[Ti+I] generated during a current (first) clock cycle CLK=Ti+I, and a previous (second) parity bit pair PB[Ti] generated during a previous (second) clock cycle CLK=Ti (i.e., previous clock cycle CLK=Ti represents the clock cycle of system clock signal CLK that occurred immediately before current clock cycle CLK=Ti+I)” (Page 5, Paragraph [0030]). Examiner notes that alternative schemes for clocking data into registers such as described here are well known in the art.
Eckhardt and Ellur are analogous art because they are both directed to advanced methods of checking and correcting the content of configuration registers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the configuration register checking of Eckhardt with the parity-based checking scheme of Ellur, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to provide checking and correction of configuration register data with minimal additional memory requirements.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW W WAHLIN whose telephone number is (408)918-7572. The examiner can normally be reached Monday - Thursday 7-4:30 PT.
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/M.W.W./Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111