DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 160-179 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 160-161, 166-168, 178-179 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budagavi et al. (US 2018/0268570 A1) in view of Aflaki Beni et al. (WO 2019/162567 A1) (hereinafter “Aflaki”) and Mammon et al. (US 11,202,098 B2) (hereinafter “Mammon II”).
Consider claim 167, Budagavi teaches an apparatus comprising: at least one processor ([0049] – [0052]); and at least one non-transitory memory including computer program code ([0049] – [0052]); wherein the at least one non-transitory memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to: receive a parameterized mesh, the mesh defining a shape and attributes of an object in three-dimensional space ([0004], [0035] – [0036], [0072] – [0073], [0076] – [0086]); compress the mesh to generate a two-dimensional patch of the mesh ([0076] – [0086]), signal separation of attribute and geometry patch orientation for image packing ([0093] – [0099]).
However, Budagavi does not explicitly teach signal at least one of: projection plane changes within the patch to support patches wrapping around a three-dimensional model; separation of attribute and geometry patch level of detail scaling to support at least one high resolution attribute patch alongside at least one lower resolution geometry patch, reflecting at least one feature of at least one lower vertex count mesh.
Aflaki teaches signal at least one of: projection plane changes within the patch to support patches wrapping around a three-dimensional model (p. 2, lines 11-30, p. 13, lines 1-10, p. 16, lines 10-21, p. 19, lines 1-25, p. 24, line 35 – p. 25, line 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signaling projection plane changes within the patch to support patches wrapping around a three-dimensional model because such incorporation would reduce the amount of data to be transmitted. P. 20, lines 5-25.
However, Budagavi does not explicitly teach separation of attribute and geometry patch level of detail scaling to support at least one high resolution attribute patch alongside at least one lower resolution geometry patch, reflecting at least one feature of at least one lower vertex count mesh.
Mammon II teaches signaling separation of attribute and geometry patch level of detail scaling to support at least one high resolution attribute patch alongside at least one lower resolution geometry patch, reflecting at least one feature of at least one lower vertex count mesh (the downscaling of the at least one 2D image frame reduces a quantity of pixels of the attribute patch images or the geometry patch images packed into the at least one 2D image frame, wherein ones of the 2D image frames comprising packed geometry patch images are down-scaled to a different size, or not down-scaled, as compared to other ones of the 2D image frames comprising packed attribute patch images; and wherein a resolution of the at least one down-scaled video-encoded 2D image frame is signaled in a video encoded bit stream for the at least one down-scaled video-encoded 2D image frame instead of, or in addition to, being encoded in a header for a group of frames comprising the video encoded one or more 2D image frames. claim 1; col. 41, line 62 – col. 42, line 25; col. 46, line 59 – col. 47, line 37; col. 61, lines 3-45).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings from Mammon II into the modified apparatus of Budagavi and Aflaki because such incorporation would better support the variability of a network. Col. 46, lines 59-66.
Consider claim 168, the combination of Budagavi and Aflaki teaches the compressing of the mesh to generate the two-dimensional patch of the mesh comprises: generating a texture patch from a texture map and face information within the mesh, to determine texture coordinates of vertices on the texture map (p. 2, lines 11-30, p. 12, lines 15-30 of Aflaki); and generating a geometry patch using the texture coordinates, to determine a subsampling factor for a geometry map ([0099], [0111] – [0124], [0149] – [0151] of Budagavi).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signaling projection plane changes within the patch to support patches wrapping around a three-dimensional model because such incorporation would reduce the amount of data to be transmitted. P. 20, lines 5-25.
Consider claim 178, Aflaki teaches the signaling of the separation of attribute and geometry patch level of detail scaling to support the at least one high resolution attribute patch alongside the at least one lower resolution geometry patch, reflecting the at least one feature of at least one lower vertex count mesh comprises at least one of: per patch signaling; a flag that specifies whether separated level of detail parameters are present for a current patch of a current atlas tile; a level of detail scaling factor to be applied to a local x-coordinate of a point in an attribute patch with an index of the current atlas tile; or a level of detail scaling factor to be applied to a local y-coordinate of the point in the attribute patch with the index of the current atlas tile (p. 19, lines 16-25; p. 24, line 35 – p. 25, line 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signaling projection plane changes within the patch to support patches wrapping around a three-dimensional model because such incorporation would reduce the amount of data to be transmitted. P. 20, lines 5-25.
Consider claim 160, claim 160 recites the method implemented by the apparatus recited in claim 167. Thus, it is rejected for the same reasons.
Consider claim 161, claim 161 recites the method implemented by the apparatus recited in claim 168. Thus, it is rejected for the same reasons.
Consider claim 179, Budagavi teaches an apparatus comprising: at least one processor ([0049] – [0052]); and at least one non-transitory memory including computer program code ([0049] – [0052]); wherein the at least one non-transitory memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to: receive a compressed parameterized mesh, the mesh defining a shape and attributes of an object in three-dimensional space ([0004], [0035] – [0036], [0072] – [0073], [0076] – [0086]); decompress the mesh from a two-dimensional patch of the mesh ([0076] – [0086]); and receive signaling of separation of attribute and geometry patch orientation for image packing ([0093] – [0099])
However, Budagavi does not explicitly teach receive signaling of at least one of: projection plane changes within the patch to support patches wrapping around a three-dimensional model; separation of attribute and geometry patch level of detail scaling to support at least one high resolution attribute patch alongside at least one lower resolution geometry patch, reflecting at least one feature of at least one lower vertex count mesh.
Aflaki teaches receive signaling of at least one of: projection plane changes within the patch to support patches wrapping around a three-dimensional model (p. 2, lines 11-30, p. 13, lines 1-10, p. 16, lines 10-21, p. 19, lines 1-25, p. 24, line 35 – p. 25, line 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signaling projection plane changes within the patch to support patches wrapping around a three-dimensional model because such incorporation would reduce the amount of data to be transmitted. P. 20, lines 5-25.
However, Budagavi does not explicitly teach separation of attribute and geometry patch level of detail scaling to support at least one high resolution attribute patch alongside at least one lower resolution geometry patch, reflecting at least one feature of at least one lower vertex count mesh.
Mammon II teaches signaling separation of attribute and geometry patch level of detail scaling to support at least one high resolution attribute patch alongside at least one lower resolution geometry patch, reflecting at least one feature of at least one lower vertex count mesh (the downscaling of the at least one 2D image frame reduces a quantity of pixels of the attribute patch images or the geometry patch images packed into the at least one 2D image frame, wherein ones of the 2D image frames comprising packed geometry patch images are down-scaled to a different size, or not down-scaled, as compared to other ones of the 2D image frames comprising packed attribute patch images; and wherein a resolution of the at least one down-scaled video-encoded 2D image frame is signaled in a video encoded bit stream for the at least one down-scaled video-encoded 2D image frame instead of, or in addition to, being encoded in a header for a group of frames comprising the video encoded one or more 2D image frames. claim 1; col. 41, line 62 – col. 42, line 25; col. 46, line 59 – col. 47, line 37; col. 61, lines 3-45).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings from Mammon II into the modified apparatus of Budagavi and Aflaki because such incorporation would better support the variability of a network. Col. 46, lines 59-66.
Consider claim 166, claim 166 recites the method implemented by the apparatus recited in claim 179. Thus, it is rejected for the same reasons.
Claim(s) 162-163 and 169-170 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budagavi et al. (US 2018/0268570 A1) in view of Aflaki Beni et al. (WO 2019/162567 A1) (hereinafter “Aflaki”) Mammon et al. (US 11,202,098 B2) (hereinafter “Mammon II”), and Mammon et al. (US 2021/0090301 A1).
Consider claim 169, the combination of Budagavi and Aflaki teaches all the limitations in claim 168 but does not explicitly teach the geometry map subsampling factor is determined based on at least one of: a patch size in x-direction or y-direction; a number of vertices in a patch; an overall patch resolution; or a content of a patch.
Mammon teaches the geometry map subsampling factor is determined based on at least one of: a patch size in x-direction or y-direction; a number of vertices in a patch; an overall patch resolution; or a content of a patch ([0324] and Fig. 5H).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of determining subsampling factor based on overall patch resolution because such incorporation would improve compression efficiency. [0324].
Consider claim 170, Mammon teaches the compressing of the mesh to generate the two-dimensional patch of the mesh comprises: reprojecting a texture patch after generating a geometry patch so that coordinate texture coordinates of a texture map correspond with the geometry patch ([0008], [0148], [0518] – [0523]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of determining subsampling factor based on overall patch resolution because such incorporation would improve compression efficiency. [0324].
Consider claim 162, claim 162 recites the method implemented by the apparatus recited in claim 169. Thus, it is rejected for the same reasons.
Consider claim 163, claim 163 recites the method implemented by the apparatus recited in claim 170. Thus, it is rejected for the same reasons.
Claim(s) 164-165, 171-174, and 177 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budagavi et al. (US 2018/0268570 A1) in view of Aflaki Beni et al. (WO 2019/162567 A1) (hereinafter “Aflaki”) Mammon et al. (US 11,202,098 B2) (hereinafter “Mammon II”), and Tsai et al. (US 2020/0013235 A1).
Consider claim 171, the combination of Budagavi and Aflaki teaches all the limitations in claim 167 but does not explicitly teach the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: signal changes in dominant projection direction within a patch.
Tsai teaches the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: signal changes in dominant projection direction within a patch ([0041], [0071] – [0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signal changes in dominant projection direction within a patch because such incorporation would enhance encoding efficiency. [0041].
Consider claim 172, Tsai teaches the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: disallow changes in dominant projection direction within a patch, such that changes in the dominant projection direction lead to creation of a new patch ([0041], [0071] – [0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signal changes in dominant projection direction within a patch because such incorporation would enhance encoding efficiency. [0041].
Consider claim 173, Tsai teaches the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: allow changes in dominant projection direction within a patch ([0041], [0071] – [0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signal changes in dominant projection direction within a patch because such incorporation would enhance encoding efficiency. [0041].
Consider claim 174, Tsai teaches the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: signal the changes in the dominant projection direction ([0041], [0071] – [0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signal changes in dominant projection direction within a patch because such incorporation would enhance encoding efficiency. [0041].
Consider claim 177, Tsai teaches the signaling of the projection plane changes within the patch to support patches wrapping around the three-dimensional model comprises at least one of: signaling dominant projection direction changes in steps, after a number of geometry values and following an orientation and direction ([0041], [0061] – [0065], [0071] – [0075]); signaling dominant projection direction changes explicitly, after a number of geometry values and following an orientation and direction; or signaling dominant projection direction changes and patch three-dimensional metadata explicitly, after a number of geometry values and following an orientation and direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of signal changes in dominant projection direction within a patch because such incorporation would enhance encoding efficiency. [0041].
Consider claim 164, claim 164 recites the method implemented by the apparatus recited in claim 171. Thus, it is rejected for the same reasons.
Consider claim 165, claim 165 recites the method implemented by the apparatus recited in claim 172. Thus, it is rejected for the same reasons.
Claim(s) 175-176 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budagavi et al. (US 2018/0268570 A1) in view of Aflaki Beni et al. (WO 2019/162567 A1) (hereinafter “Aflaki”), Mammon et al. (US 11,202,098 B2) (hereinafter “Mammon II”), Tsai et al. (US 2020/0013235 A1), Sinharoy et al. (US 2020/0219286 A1).
Consider claim 175, the combination of Budagavi, Aflaki, and Tsai teaches all the limitations in claim 173 but does not explicitly teach the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: determine whether to split the patch.
Sinharoy teaches the at least one non-transitory memory and the computer program code are further configured to, with the at least one processor, cause the apparatus at least to: determine whether to split the patch ([0042], [0108] – [0109], [0111] – [0120], [0126], [0146], [0151] – [0153]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of determining whether to split the patch because such incorporation would reduce the video frame dimension and improve the compactness (or tightness) of a patch packing in the video frames. [0042].
Consider claim 176, Sinharoy teaches determining whether to split the patch is based on at least one criterion comprising at least one of: a bitrate for signaling; a complexity of the changes in the dominant projection direction; a number of possible new patches created; or a total number of patches ([0114] – [0126]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the known technique of determining whether to split the patch because such incorporation would reduce the video frame dimension and improve the compactness (or tightness) of a patch packing in the video frames. [0042].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TAT C CHIO/Primary Examiner, Art Unit 2486