DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 02/19/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kadokawa (JP 2003330555 A).
Regarding claim 1, Kadokawa teaches a discharge control circuit (abstract, stabilized power supply circuit capable of suppressing an excessive inflow current), comprising:
a first gate voltage output circuit (e.g. current limiting circuit 20) (figs.1-2) configured to output a first gate voltage (page 4, current limiting MOSFET for limiting the current flowing in the output control MOS transistor QO4) supplied to a transistor (e.g. transistor QO4) (figs.1-2) connected to a capacitive load (page 2, Further, in order to reduce the number of parts in the IC card, the voltage smoothing filter capacitor Cf1 must also be provided in the chip);
a second gate voltage output circuit (e.g. circuit comprising current mirror Q1) (figs.1-2) configured to output a second gate voltage supplied to the transistor (e.g. QI current is mirrored to gate of transistor QD4, when SW1 and SW2 are off) (figs.1-2); and
a switching control circuit (i.e. time constant circuit 30) (fig.2) configured to switch supply of the first gate voltage and the second gate voltage to the transistor (page 5, switches SW1 and SW2 are turned on only for a period),
wherein the first gate voltage output circuit is configured to control the first gate voltage so that a current flowing through the transistor is constant (page 5, the inflow current flowing into the internal circuit of the IC card LSI is limited when the supply of the input voltage VDD is started),
the second gate voltage output circuit is configured to output a voltage at a constant level as the second gate voltage (page 5, the action of the current limiting circuit 20 is immediately released, and the normal stabilized power supply circuit 10), and
the switching control circuit is configured to perform control to supply the second gate voltage after supplying the first gate voltage to the transistor (page 5, time constant circuit 30 has a resistor R30 and a capacitor C3 from the start of application of the input voltage VDD).
Regarding claim 2, Kadokawa teaches the discharge control circuit according to claim 1, wherein the first gate voltage output circuit is configured to control the first gate voltage so that a difference (page 4, error amplifier 11 as a voltage comparison circuit for amplifying a difference voltage between the feedback voltage Vrt and the reference voltage Vref) between a terminal voltage of a current detection resistor that detects the current flowing through the transistor (page 4, feedback voltage Vret) and a predetermined reference voltage is constant (page 4, reference voltage Vref).
Regarding claim 3, Kadokawa teaches the discharge control circuit according to claim 2, wherein the first gate voltage output circuit comprises a differential amplifier circuit (e.g. circuit comprising error amplifier 11) (fig.1) in which the terminal voltage of the current detection resistor is input to an inverting input terminal (e.g. Vret is input to inverting terminal of 11) (fig.1) and the reference voltage is input to a non- inverting input terminal (e.g. Vref is input to non-inverting terminal of 11) (fig.1).
Regarding claim 4, Kadokawa teaches the discharge control circuit according to claim 1, wherein a level of the second gate voltage (page 5, the action of the current limiting circuit 20 is immediately released, and the normal stabilized power supply circuit 100) is higher than a level of the first gate voltage (page 4, current limiting circuit 20 for limiting the inflow current at the start of supply of the input voltage VDD).
Regarding claim 5, it is rejected for the same reasons as stated above for claim 4.
Regarding claim 6, it is rejected for the same reasons as stated above for claim 4.
Conclusion
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/SREEYA SREEVATSA/Examiner, Art Unit 2838 09/12/2025