DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 11 should be dependent on claim 10, similar to claim 19 being dependent on claim 18. Correction make the claim(s) clear and cure the standing rejection(s). For examination purposes, Examiner will assume this to be a type and examine as if Claim(s) 11 depends on claim 10.
Claim(s) 12-14 is/are rejected as for being dependent on the above rejected parent claim(s).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SU (US 7133791 B1).
With respect to Claim(s) 1, 15, SU teaches a N-sample level-crossing estimator and the BRI of:
An apparatus/method,
comprising:
a clock signal input
to
receive N time measurements (column 3, lines 36-65; figures 1 and 2; signal g (x) 11 and two-mean N sample time interval estimator device 20),
a time measurement of the N time measurements to denote a respective time of a respective portion of a given cycle of a clock signal (column 3, line 36 - column 4, line 36; figures 1 and 2; arrow 15 and box 28; equation (5)),
the clock signal to include a frequency or period to be estimated over the N time measurements (column 3, line 36 - column 4, line 36; figures 1 and 2; box 28);
a sampling circuit
to:
generate a first sampled window from the clock signal input, the first sampled window including a sum of a plurality of a first m of the N time measurements (column 3, line 66 - column 4, line 36; equation (6) and term on the right in column 4, line 20);
and
generate a second sampled window from the clock signal input, the second sampled window including a sum of a plurality of a last m of the N time measurements (column 3, line 66 - column 4, line 36; equation (6) and term on the left in column 4, line 20);
and
an estimation circuit
to
estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window (column 3, line 66 - column 4, line 36; equation (6) & column 5, lines 26-67; figure 5; step 108).
With respect to Claim(s) 2, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
a first accumulator to generate the first sampled window and a second accumulator to generate the second sampled window (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.)
With respect to Claim(s) 3, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
m is greater than N/2 (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.).
With respect to Claim(s) 4, 16, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
a counter to count time measurements as they are received on the clock signal input (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.),
wherein:
upon reception of a given time measurement on the clock signal input, if less than m time measurements have been received, the first accumulator is to add the given time measurement to a first running total of time measurements to generate the first sampled window (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.);
upon reception of a given time measurement on the clock signal input, if m or greater time measurements have been received, the first accumulator is to maintain the first running total of time measurements (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.);
and
upon reception of a given time measurement on the clock signal input, if (N-m) or greater time measurements and less than or equal to N time measurements have been received, the second accumulator is to add the given time measurement to a second running total of time measurements to generate the second sampled window (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.).
With respect to Claim(s) 5, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
an accumulator to add successive time measurements of the first m of the N time measurements to generate the first sampled window (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.).
With respect to Claim(s) 6, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
m is less than N/2 (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.)
and
an accumulator to first generate the first sampled window and to then generate the second sampled window (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.).
With respect to Claim(s) 7, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
a counter to count time measurements as they are received on the clock signal input (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.),
wherein:
upon reception of a given time measurement on the clock signal input, if the counter indicates that less than m time measurements have been received, an accumulator is to add the given time measurement to a first running total of time measurements to generate the first sampled window (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.);
upon reception of a given time measurement on the clock signal input, if the counter indicates that m time measurements have been received, the sampling circuit is to store the first running total of time measurements as the first sampled window in a first memory and to reset the accumulator (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.);
upon reception of a given time measurement on the clock signal input, if the counter indicates that a quantity of time measurements greater than or equal to (N-m) but less than N has been received, the accumulator is to add the given time measurement to a second running total of time measurements (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.);
and
upon reception of a given time measurement on the clock signal input, if the counter indicates that N time measurements have been received, the sampling circuit is to store the second running total of time measurements as the second sampled window in a second memory (column 5, lines 3-25 | discloses a circuit using a single accumulator; column 4, line 55-column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more thana design choice, which the skilled person would make, depending on the circumstances, without exercising any inventive skills.).
With respect to Claim(s) 8, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
wherein
the accumulator is to:
accumulate the first m time measurements and store an accumulation of the first m time measurements in a first memory as the first sampled window (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.);
and
accumulate the last m time measurements and store an accumulation of the last m time measurements in a second memory as the second sampled window (column 3, line 66 - column 4, line 36; figure 2 and equation (6) & column 5, lines 26-67; figure 5; steps 102-106 | discloses using accumulators and memories to perform the required calculations in the N measurements to estimate the frequency or period of the signal; column 4, line 55 - column 5, line 2 | discloses an example of an implementation circuit where m=N/2. Using other values for m amounts to no more than a design choice, which the skilled person would make, depending on the circumstances, without requiring any inventive skills.).
With respect to Claim(s) 9, 17, SU teaches the BRI of the parent claim(s).
SU further teaches the BRI of:
upon the sampling circuit reception of N time measurements, subtract the first sampled window from the second sampled window, and to apply a result from the subtraction to a multiplication factor of 1/(m(N-m)) to yield an estimated frequency or period of the clock signal (column 3, line 66 - column 4, line 36; figure 2 and equation (6)).
Allowable Subject Matter (over prior art)
Claim(s) 10, 18-20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter over prior art:
Examiner’s closest prior art to the claimed subject matter:
citations above;
MIYAHARA (US 20110301895 A1) teaches a phase measuring device that can measure phase differences with high precision using the digital circuits;
HAARTSEN ET AL. (US 20110087449 A1) teaches calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal;
HUTCHINSON (US 20100141240 A1) teaches determining timestamps for signal timing edges for use in, e.g., a reciprocal counter for determining the frequency of a signal;
BREAM ET AL. (US 5019823 A) teaches measuring the frequency of an input signal.
None of the cited prior art alone or in combination provides motivation to explicitly teach:
sample a given time measurement and to skip sampling of a next L time measurements after the given time measurement and to exclude the next L time measurements from generation of the first sampled window and the second sampled window
of claim(s) 10, 18 (including dependent claim(s)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYMOND NIMOX whose telephone number is (469)295-9226. The examiner can normally be reached Mon-Thu 10am-8pm CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREW SCHECHTER can be reached at (571) 272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
RAYMOND NIMOX
Primary Examiner
Art Unit 2857
/RAYMOND L NIMOX/Primary Examiner, Art Unit 2857
Prosecution Insights