DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 07/24/2026, for application number 18/581,839 has been received and entered into record. Claims 1, 3-6, 8, 11-15, 17-20 are amended. Claim 16 is cancelled. Claim 21 is added. Thus, claims 1-15 and 17-21 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 19 and 20 are objected to because of the following informalities: “first and second threshold are associated…” should read “first and second thresholds are associated…” (emphasis added). Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 8, 9, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Scott (US 2005/0135247 A1) in view of Anubolu et al. (US 2022/0321504 A1).
Regarding claim 1, Scott teaches a system comprising one or more circuits (Figures 2, 3 and 8) to:
receive a power profile (“the installer can provide the necessary programming information to the power budgeter unit 90.” Par 0097) [the programming/configuration information provided by installer corresponds to the power profile which is received by power budgeter], wherein the power profile defines a first time period associated with a first threshold and a second time period associated with a second threshold (“when aggregate transceiver activity reaches and/or exceeds the predefined threshold during a first time period, transceiver activity during the second time period is limited” par 0033 and “A minimum threshold may also be considered such that the restriction period is extended into subsequent monitored time periods so that a minimum service level to all active transceivers can be maintained.” Par 0077), wherein the first and second threshold are associated with one or more of bandwidth and power (“The predefined threshold corresponds to the maximum amount of allowable heat dissipation in a multiple transceiver unit in which the transceivers reside” par 0032 and “The threshold is calculated by taking the maximum allowable heat dissipation in multiple transceiver unit 62 specified by code, subtracting the heat dissipated by the common components residing in the multiple transceiver unit 62, and then correlating the remaining allowable heat dissipation to a data flow rate.” Par 0047) [power budgeting system uses installer programming to enforce consecutive period limits that throttle data rates and heat dissipation (power)];
monitor one or more of data traversing the system and power consumption of the system during the first time period (“a digital signal processor (DSP) configured to monitor data flow through the transceiver during a predefined first time period;” claim 1 and “DSP 110 monitors data flow through transceiver 104 during a predefined time period.” Par 0043 and “Knowing the actual heat dissipated by the transceivers for various data flow rates, the actual total heat dissipated by all transceivers may be computed.” Par 0049) [by monitoring data flow, the DSP can compute and track power consumption (heat dissipation) based on data rates and heat, see par 49];
determine at least one of the data traversing the system and the power consumption of the system exceeds the first threshold within the first time period (“if total transceiver data flow in transceiver port cards 66, 68 and 70 exceeds the threshold, the power budgeter 60 issues a control signal to active transceivers that limits data flow” par 0038 and “if a sufficient number of transceivers are active, such that the total heat dissipation of the active transceivers would exceed the specified limit of the multiple transceiver unit during the monitored time period, the power budgeter operates such that transceiver activity is limited (actual data transmit and receiver rates are throttled back)” par 0033 and Figure 7).
However, Scott does not explicitly teach in response to determining the at least one of the data traversing the system and the power consumption of the system exceeds the first threshold within the first time period, limit one or more of the data traversing the system and the power consumption of the system until the first time period lapses and the second time period begins.
In the analogous art, Anubolu teaches in response to determining the at least one of the data traversing the system and the power consumption of the system exceeds the first threshold within the first time period, limit one or more of the data traversing the system and the power consumption of the system until the first time period lapses and the second time period begins (“as shown in FIG. 3C, the “Throttle Factor” may be immediately set to the ceiling, or “ConfiguredHiClock”, and remain there until the surplus power budget is exhausted, at which point throttling is incurred and the “Throttle Factor” ramps down to “Configured LoClock” for the remainder of the thermal average period.” Par 0030 and “When the thermal average period elapses, throttle control 280 may assert a reset signal to energy estimator 290, which in turn may perform a reset or initialization of surplus power budgets and other values according to configurable throttle policies for each thermal average period.” Par 0025 and paragraphs 30-31, Figures 3C, 4) [the system uses an aggressive ramping policy, where if allocated power budget is exhausted during active thermal average period (first time period), throttling of power is triggered and maintained for remainder of first time period until it lapses and lasts until the next time period (second time period) starts].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott and Anubolu before him before the effective filing date of the claimed invention, to have modified Scott to incorporate the teachings of Anubolu to implement an aggressive ramping policy to limit data traversal and power consumption within the same time period they exceed a threshold to prioritize burst performance and rapidly bring power consumption within operational limit and reduce latency spikes.
Claim 19 corresponds to claim 1 and is rejected accordingly.
Regarding claim 2, Scott and Anubolu teach the system of claim 1. Anubolu further teaches wherein monitoring the data traversing the system comprises monitoring one or more of a bandwidth, a packet rate, a buffer utilization, and a queue length (“Throttle control 280 is able to count the number or rate of incoming ingress packets, and thus cells, for throttling. Further, throttle control 280 may receive ingress scheduler (IS) metadata, for example buffer fill rates.” Par 0024 and paragraph 32).
Regarding claim 6, Scott and Anubolu teach the system of claim 1. Scott further teaches wherein the first threshold indicates a user-defined power consumption limit (“the preferred embodiment of the PB logic 96 residing in the power budgeter unit 90 has a variety of user selectable options that enable the power budgeter unit 90 to fully allocate data flow capacity among the active transceivers, and thus be tailored to the specific needs of each unique installation. During installation, the installer could specify the features to be applied by programming the power budgeter unit 90 through interface 102.” Par 0073 and paragraphs 72, 97 and Figure 3).
Claim 21 corresponds to claim 6 and is rejected accordingly.
Regarding claim 8, Scott and Anubolu teach the system of claim 1. Scott further teaches wherein the first threshold indicates a user-defined bandwidth limit (“a user interface coupled to the means for controlling and configured so that a user may specify the predefined time period and the predefined threshold.” Claim 6 and “The power budgeter monitors transceiver activity (data flow) during a predefined period, and limits transceiver data transmit and receive rates during times when the aggregate transceiver activity would otherwise exceed a predefined threshold.” Abstract and paragraphs 72, 73 and 97).
Regarding claim 9, Scott and Anubolu teach the system of claim 8. Scott further teaches wherein the one or more circuits are further to determine a power requirement based on the bandwidth limit (“The threshold is calculated by taking the maximum allowable heat dissipation in multiple transceiver unit 62 specified by code, subtracting the heat dissipated by the common components residing in the multiple transceiver unit 62, and then correlating the remaining allowable heat dissipation to a data flow rate.” Par 0047) [the system calculates power requirements and limits and correlates transceivers’ allowable heat dissipation (power requirement) to active data transfer rates (bandwidth)].
Regarding claim 20, Anubolu teaches a switch (Figure 1A, network switch 104) comprising:
one or more ports (“ The electronic devices 102A-C may be connected to the network switch 104, such that the electronic devices 102A-C may be able to communicate with each other via the network switch 104. The electronic devices 102A-C may be connected to the network switch 104 via wire (e.g., Ethernet cable)” par 0020 and Figure 1A, network switch has ports); and
a power profile controller (Figure 2B, throttle control 280, step control 282, clock regulator 284, power gating block 230).
The remainder of claim 20 corresponds to claim 1 and is rejected accordingly.
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Scott and Anubolu in view of Khatri et al. (US 2017/0031431 A1).
Regarding claim 3, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein the one or more circuits are further to correlate the monitored data traversing the system with the power consumption of the system and to adjust of the first threshold based on the correlation to account for leakage of power until the first time period lapses.
In the analogous art, Khatri teaches wherein the one or more circuits are further to correlate the monitored data traversing the system with the power consumption of the system and to adjust of the first threshold based on the correlation to account for leakage of power until the first time period lapses (“Micro-controller 122 determines the node peak power limits or thresholds 230 (i.e. node peak limits 166, 232, 234 and 236) and the node average power limits or thresholds 240 (i.e. node average limits 168, 242, 244 and 246) for each of the processing nodes based on the power-usage data and workload data,” par 0074 and “PMM 120 (FIG. 1) dynamically allocates peak and sustained node power limits for several processing nodes during operation of IHS 100 based on power-usage and workload data.” Par 0067 and “The node controllers are triggered to determine and set, based on the node peak power threshold, a device peak power limit for at least one variable performance device … dynamically adjusts a respective performance metric value based on the device peak power limit.” par 0008) [the PMM correlates real time monitored workload data with measured power usage (power leakage) to recalculate and reallocate (adjust) node and device thresholds that regulate both system power and bandwidth during each periodic monitoring (first time period)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Khatri before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Khatri to adjust the threshold based on monitored power to adapt power limits to real time node demands, optimizing power usage in the system.
Regarding claim 7, Scott and Anubolu teach the system of claim 6. However, Scott and Anubolu do not explicitly teach wherein the system receives power from a power supply shared by one or more interconnect devices and processing devices, wherein the power consumption limit is associated with an amount of power consumed by the system from the power supply.
In the analogous art, Khatri teaches wherein the system receives power from a power supply shared by one or more interconnect devices and processing devices, wherein the power consumption limit is associated with an amount of power consumed by the system from the power supply (“PSUs 130A-D supply power to each of the processing nodes and other components within IHS 100 that require power via either one or more bus bars or power cables (not shown).” Par 0040 and “The power capability data includes data such as a total available system power of the IHS, including a peak power output capacity and a sustained output power capacity.” Par 0055) [the power supply units provide power to the processing nodes and other components (which also include interconnect devices, see par 45); the total available power from the PSUs is identified, which is used for calculating the power consumption limits].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Khatri before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Khatri to have a power supply shared by all components of the system to improve efficiency and have easier power regulation and distribution in the system.
Claims 4, 12, 13, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Scott and Anubolu in view of Trivedi et al. (US 2014/0019654 A1).
Regarding claim 4, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein the one or more circuits are further to update one or more of the first power threshold and the first bandwidth threshold based on a correlation of the monitored data traversing the system with the power consumption of the system.
In the analogous art, Trivedi teaches wherein the one or more circuits are further to update one or more of the first power threshold and the first bandwidth threshold based on a correlation of the monitored data traversing the system with the power consumption of the system (“An embodiment implements a policy that enables energy-efficient I/O operation by delivering a performance-power loadline for PCIe traffic.” Par 0046 and “Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement and intelligent decision making on the opportunistic down configuration and immediate up configuration of a link to provide power savings without impacting performance.” Par 0042) [the policy establishes a correlation between performance and power consumption via a loadline, affecting adjustment of thresholds].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Trivedi before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Trivedi to update the power and bandwidth thresholds based on data traversing the system and power consumption to improve system performance and efficiency.
Regarding claim 12, Scott, Anubolu and Benisty teach the system of claim 11. However, do not explicitly teach wherein the first threshold is greater than the second threshold.
In the analogous art, Trivedi teaches wherein the first threshold is greater than the second threshold (“In block 310 if the accumulated bandwidth requirement exceeds an upper threshold (Upth) then an up configuration takes place relatively immediately (block 315) (e.g., in less than 5 or 10 microseconds so as to minimize latency)… in block 325 it is determined if the accumulated bandwidth requirement is greater than a lower threshold (DnTh)” Par 0034 and Figure 5).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Trivedi before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Trivedi to have a lower second power and bandwidth thresholds to reduce leakage power without increasing latency. (Trivedi, paragraph 37)
Regarding claim 13, Scott, Anubolu and Benisty teach the system of claim 11. However, do not explicitly teach wherein the first time period is of a lesser duration than the second time period.
In the analogous art, Trivedi teaches wherein the first time period is of a lesser duration than the second time period (“the second time period being longer than the first time period.” Par 0048).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu, Benisty and Trivedi before him before the effective filing date of the claimed invention, to have modified Scott, Anubolu and Benisty to incorporate the teachings of Trivedi to have the second predetermined time period being longer than the first predetermined time period to have stable threshold detection and prevent unnecessary power state switches or data limiting.
Regarding claim 18, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein the power profile is one of a plurality of power profiles and each of the plurality of power profiles is associated with a respective application, wherein the one or more circuits are further to aggregate the plurality of power profiles and determine of the first threshold based on the aggregated plurality of power profiles.
In the analogous art, Trivedi teaches wherein the power profile is one of a plurality of power profiles and each of the plurality of power profiles is associated with a respective application, wherein the one or more circuits are further to aggregate the plurality of power profiles and determine of the first threshold based on the aggregated plurality of power profiles (“PCIe controller 130 receives inputs from integrated endpoints (e.g., device 140) and downstream ports (e.g., 160) about their respective maximum bandwidth requirement. Controller 130 then aggregates the individual inputs to compute the net uplink bandwidth requirement.” Par 0022 and “Once the required bandwidth is known, controller 130 may determine the appropriate link 125 width.” Par 0027 and “the PCIe controller may dynamically increase the width of the link when the determined bandwidth is greater than a first threshold (e.g., the present width LW)” par 0050) [the bandwidth requirements make up the power profile; the controller determines the appropriate link width which corresponds to setting a first threshold based on aggregated data; the thermal monitor information in the policy suggests the determination of power thresholds are also based on the aggregated data, under BRI].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Trivedi before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Trivedi to have individual power profiles for each application to simplify power management and optimize power distribution.
Claims 5, 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Scott and Anubolu in view of Matthews et al. (US 2024/0094798 A1).
Regarding claim 5, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein limiting the one or more of the data traversing the system and the power consumption of the system comprises limiting one or more of an ingress bandwidth and an egress bandwidth until the first time period lapses.
In the analogous art, Matthews teaches wherein limiting the one or more of the data traversing the system and the power consumption of the system comprises limiting one or more of an ingress bandwidth and an egress bandwidth until the first time period lapses (“the throughput is managed by controlling rates at which a combination of one or more ingress arbiters and one or more egress arbiters forward packets to respective ingress packet processors and egress packet processors, using a power credit management process” par 0009 and “upon computing a negative value for the updated_credit_balance as described previously, the ingress arbiter 203 a holds the packet in the queue until the next refresh period,” par 0100 and paragraph 92) [the ingress and egress bandwidth corresponds to the throughput/data forwarding rates regulated by the arbiters; the system manages the throttling data across its ingress/egress paths, pausing processing whenever power credits are exhausted until next refresh period].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Matthews before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Matthews to limit the ingress and egress bandwidths until the time period lapses and determine which packets are transmission eligible to ensure throughput does not exceed the threshold for the power profile. This helps maintain the device current at safe levels while maximizing performance. (Matthews, paragraph 10)
Regarding claim 15, Scott, Anubolu and Benisty teach the system of claim 11. However, Scott, Anubolu and Benisty do not explicitly teach wherein limiting egress of packets comprises one or more of throttling traffic and dropping packets until the second time period lapses.
In the analogous art, Matthews teaches wherein limiting egress of packets comprises one or more of throttling traffic and dropping packets until the second time period lapses (“if the updated_credit_balance is a negative value, the credit update controller 420 operations determine that not enough power credits are available to the ingress arbiter to forward the packets. In such cases, the packets are not deemed to be transmission_eligible. The logic instructs the scheduler to not schedule any packets, and the ingress arbiter holds the packets in the queue until the next refresh period,” par 0092 and “if the traffic manager determines that the total amount of data to be written exceeds the threshold level, then the traffic manager decides to drop some of the cells it could write to buffers managed by the traffic manager.” Par 0032).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu, Benisty and Matthews before him before the effective filing date of the claimed invention, to have modified Scott, Anubolu and Benisty to incorporate the teachings of Matthews to drop packets until the second time period ends to ensure throughput does not exceed the threshold for the power profile. This helps maintain the device current at safe levels while maximizing performance. (Matthews, paragraph 10)
Regarding claim 17, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein the one or more circuits are further to monitor a temperature and adjust one or more of the first threshold based on the temperature until the first time period lapses.
In the analogous art, Matthews teaches wherein the one or more circuits are further to monitor a temperature and adjust one or more of the first threshold based on the temperature until the first time period lapses (“The environmental factors for data collection include the device temperature (such as junction temperature, Tj, and/or ambient temperature),” par 0056 and “When the operating state changes from one ORE to a different ORE, the device adjusts the data forwarding rate to address the throughput specified by the new ORE. For example, the electronic device 200 may be operating in ORE1 at a point in time when the temperature and/or the device current are measured. The electronic device may determine, upon comparing the measured values to ranges as described above, that at least one of the temperature or the device current has increased, such that the measured value is in the respective range corresponding to ORE2 (or ORE3).” Par 0068) [the system monitors junction temperature to transition between OREs which includes adjusting thresholds used to regulate traffic until the current refresh period interval lapses, see paragraphs 52-58, 64, 65, 92, 100].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Matthews before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Matthews to adjust the threshold based on the temperature to prevent system overheating. By controlling the data throughput rate, a maximum pipeline throughput for packets processing unit can be achieved. (Matthews, paragraph 10)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Scott and Anubolu in view of Eckert et al. (US 2012/0130657 A1).
Regarding claim 10, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein the one or more circuits are further to measure one or more of a current and a voltage and calculate a moving average power consumption.
In the analogous art, Eckert teaches wherein the one or more circuits are further to measure one or more of a current and a voltage and calculate a moving average power consumption (“Power consumption in a part of an electronic circuit can be measured directly by simultaneously measuring time domain voltage U and current I within this part of the electronic circuit and calculating P=U*I. In particular, average power consumption can be evaluated based on measurements of average voltage and average current during specific hardware operation in a steady state system environment. ” par 0007).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Eckert before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Eckert to calculate a moving average power consumption to provide a more accurate and direct measurement of power consumption for enhanced energy-efficient dynamic system adjustments.
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Scott and Anubolu in view of Benisty (US 2021/0174883 A1).
Regarding claim 11, Scott and Anubolu teach the system of claim 1. However, Scott and Anubolu do not explicitly teach wherein the one or more circuits are further to: determine at least one of the data traversing the system and the power consumption of the system exceeds the second threshold within the second time period; and in response to determining the at least one of the data traversing the system and the power consumption of the system exceeds the second threshold within the second time period, limit egress of packets until the second time period lapses and the first time period restarts.
In the analogous art, Benisty teaches wherein the one or more circuits are further to:
determine at least one of the data traversing the system and the power consumption of the system exceeds the second threshold within the second time period (“A query is run at 306 to determine if the pre-configured bandwidth threshold allows to send a request to the host 302.” Par 0038 and “Typically, the time for peak power may extend for a short interval of one (1) second [second time period], while the average power for a device connected to a laptop computer may extend for greater than six (6) seconds [first time period].” Par 0004 and Figure 3); and
in response to determining the at least one of the data traversing the system and the power consumption of the system exceeds the second threshold within the second time period, limit egress of packets until the second time period lapses and the first time period restarts (“If the sending of the request to the host is not allowed according to the bandwidth threshold, then, at 308, an amount of time may be waited until the bandwidth allows the sending of the request.” Par 0038 and “In a like instance, during activities such as those of peak power usage, throttling of activities may occur, reducing power consumption and evening out power consumption.” Par 0040 and Figure 3) [during peak activity during second time period, system detects if egress bandwidth threshold is exceeded; in response, the controller throttles activities by waiting some time at step 308; this stops transmission of egress packets, holding traffic until second time period ends and data transfer can resume across first time period].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Scott, Anubolu and Benisty before him before the effective filing date of the claimed invention, to have modified Scott and Anubolu to incorporate the teachings of Benisty limit egress packets during a second time period to adequately control power consumption while providing a memory arrangement that can be connected to a computer that also has high speed and low speed interfaces. (Benisty, paragraphs 5-7)
Regarding claim 14, Scott, Anubolu and Benisty teach the system of claim 11. Benisty further teaches wherein a shaper circuit determines the at least one of the data traversing the system and the power consumption of the system exceeds the first threshold (“wherein the device controller is configured to shape power usage, and a data transfer throttling arrangement … the device controller is configured to shape power usage, and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.” Par 0013 and “The data-transfer throttling arrangement is responsible for shaping the performance” par 0042) [the controller may correspond to a shaper circuit which throttles arrangement to shape power usage and performance].
Anubolu further teaches determines the at least one of the data traversing the system and the power consumption of the system exceeds the first threshold and determines the at least one of the data traversing the system and the power consumption of the system exceeds the second threshold (“if the buffer fill rate of cell buffer 250 exceeds a upwards threshold, as indicated by the IS metadata, then the “ThrottleFactor” may be set to the maximum possible, or “ConfiguredHiClock”. Similarly, if the buffer fill rate of cell buffer 250 falls below a downwards threshold, then the “ThrottleFactor” may be set to the minimum possible, or “ConfiguredLoClock”.” Par 0032) [this shows dual-threshold logic].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Anand et al. (US 2014/0105218 A1) teaches a system for dynamic queue threshold management in shared buffers which uses a feedback control loop to adapt to real-time network dynamics.
Dumitrescu et al. (US 2017/0070356 A1) teaches a programmable network device for efficiently managing and prioritizing network traffic via a hierarchical scheduler, traffic shaping and accurate metering to satisfy service level agreements.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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