DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 03/02/2026 for application number 18/581,839.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 8, 11, 15, 17, 19, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Matthews et al. (US 2024/0094798 A1).
Regarding claim 1, Matthews teaches a system comprising one or more circuits to:
receive a power profile (“power consumption stays within the configured power expenditure profile for the present ORE” par 0010);
monitor one or more of data traversing the system and power consumption of the system (“the device attributes for data collection include the device current (Idd),” par 0055 and “the raw activity caused by packets traversing the electronic device 100,” par 0030);
determine at least one of an ingress bandwidth exceeds a first bandwidth threshold within a first predetermined time period and the power consumption exceeds a first power threshold within the first predetermined time period (“The measurement data for each device attribute and/or environmental factor is compared to respective range thresholds in various OREs specified for the electronic device 200, to select one of the OREs as the present ORE for the device.” Par 0061 and “the ingress arbiter generates power credits at a periodic interval of a refresh period [first predetermined time period].” Par 0074 and “Each traffic manager compares the total amount of data to be written [ingress bandwidth] … to a predetermined threshold level, e.g., a preselected number of write operations; if the traffic manager determines that the total amount of data to be written exceeds the threshold level, then the traffic manager decides to drop some of the cells” par 0032) [the device monitors performance attributes like throughput and current, evaluating them against thresholds in the operating regions (ORE) within a set periodic refresh interval], wherein at least one of the first bandwidth threshold and the first power threshold is defined in the power profile (“each ORE specifies a range of values for each device attribute and/or environmental factor for which data is collected, with a range limited by an upper threshold and a lower threshold.” Par 0061 and “target rate represents the target throughput for the present ORE of the electronic device 200.” Par 0076 and Figures 1, 2, 6) [the operating regions correspond to power profiles as they define specific current (power) and throughput (bandwidth) thresholds]; and
in response to determining the at least one of the ingress bandwidth exceeds the first bandwidth threshold within the first predetermined time period and the power consumption exceeds the first power threshold within the first predetermined time period, limit one or more of the data traversing the system and the power consumption of the system until the first predetermined time period lapses (“if the traffic manager determines that the total amount of data to be written exceeds the threshold level, then the traffic manager decides to drop some of the cells it could write to buffers managed by the traffic manager.” Par 0032 and “The ingress arbiter is allocated a number of power credits…representative of an amount of power to be consumed by the electronic device to process packet(s) corresponding to the amount of data” Par 0008 and “if the updated_credit_balance is a negative value, the credit update controller 420 operations determine that not enough power credits are available to the ingress arbiter to forward the packets. In such cases, the packets are not deemed to be transmission_eligible. The logic instructs the scheduler to not schedule any packets, and the ingress arbiter holds the packets in the queue until the next refresh period,” par 0092) [when the threshold is exceeded, the system drops data transmission (limits data traversal) until the current periodic refresh interval is completed].
Claim 19 corresponds to claim 1 and is rejected accordingly.
Regarding claim 2, Matthews teaches the system of claim 1, wherein monitoring the data traversing the system comprises monitoring one or more of a bandwidth, a packet rate, a buffer utilization, and a queue length (“The device attributes can also include packet processing rate (for example, in units of million packets processed per second, MPPS), the cell processing rate (for example, in units of million cells processed per second, MCPS), throughput (for example, in units of gigabits per second, Gbps), or utilization (for example, ratio of throughput to capacity,” par 0055 and “This factors include … current drop state of the packet queue to which the cell will be linked” par 0033).
Regarding claim 5, Matthews teaches the system of claim 1, wherein limiting the one or more of the data traversing the system and the power consumption of the system comprises limiting one or more of an ingress bandwidth and an egress bandwidth until the first predetermined time period lapses (“the throughput is managed by controlling rates at which a combination of one or more ingress arbiters and one or more egress arbiters forward packets to respective ingress packet processors and egress packet processors, using a power credit management process” par 0009 and “upon computing a negative value for the updated_credit_balance as described previously, the ingress arbiter 203 a holds the packet in the queue until the next refresh period,” par 0100 and paragraph 92) [the ingress and egress bandwidth corresponds to the throughput/data forwarding rates regulated by the arbiters; the system manages the throttling data across its ingress/egress paths, pausing processing whenever power credits are exhausted until next refresh period].
Regarding claim 6, Matthews teaches the system of claim 1, wherein the first power threshold indicates a user-defined power consumption limit (“the one or more threshold levels can be set by a user, e.g., by an operator who configures the electronic device and sets the threshold levels in accordance with targeted limits of power consumption by the electronic device.” Par 0038).
Regarding claim 8, Matthews teaches the system of claim 1, wherein the first bandwidth threshold indicates a user-defined bandwidth limit (“the one or more threshold levels can be set by a user, e.g., by an operator who configures the electronic device and sets the threshold levels in accordance with targeted limits of power consumption by the electronic device.” Par 0038).
Regarding claim 11, Matthews teaches the system of claim 1, wherein the one or more circuits are further to:
determine at least one of the ingress bandwidth exceeds a second bandwidth threshold within a second predetermined time period and the power consumption exceeds a second power threshold within the second predetermined time period, wherein at least one of the second bandwidth threshold and the second power threshold is defined in the power profile (“The measurement data for each device attribute and/or environmental factor is compared to respective range thresholds in various OREs … to select one of the OREs as the present ORE for the device.” par 0061 and “device attributes can also include packet processing rate … throughput” par 0055 and “upon computing a negative value for the updated_ credit_balance as described previously, the ingress arbiter 203 a holds the packet in the queue until the next refresh period,” par 0100 and paragraphs 63, 92 and Figure 3); and
in response to determining the at least one of the ingress bandwidth exceeds the second bandwidth threshold within the second predetermined time period and the power consumption exceeds the second power threshold within the second predetermined time period, limit egress of packets until the second predetermined time period lapses (“the throughput is managed by controlling rates at which egress arbiters forward packets received from traffic managers to respective egress packet processors connected to the egress arbiters, using a power credit management process” par 0009 and “upon computing a negative value for the updated_ credit_balance as described previously, the ingress arbiter 203 a holds the packet in the queue until the next refresh period,” par 0100) [the uses the OREs as power profiles to evaluate power (current) and bandwidth (throughput) against thresholds; when thresholds are exceeded, packet transmissions are paused (limited) until the periodic interval (second predetermined time period) finishes].
Regarding claim 15, Matthews teaches the system of claim 11, wherein limiting egress of packets comprises one or more of throttling traffic and dropping packets until the second predetermined time period lapses (“if the updated_credit_balance is a negative value, the credit update controller 420 operations determine that not enough power credits are available to the ingress arbiter to forward the packets. In such cases, the packets are not deemed to be transmission_eligible. The logic instructs the scheduler to not schedule any packets, and the ingress arbiter holds the packets in the queue until the next refresh period,” par 0092 and “if the traffic manager determines that the total amount of data to be written exceeds the threshold level, then the traffic manager decides to drop some of the cells it could write to buffers managed by the traffic manager.” Par 0032).
Regarding claim 17, Matthews teaches the system of claim 1, wherein the one or more circuits are further to monitor a temperature and adjust one or more of the first bandwidth threshold and the first power threshold based on the temperature until the first predetermined time period lapses (“The environmental factors for data collection include the device temperature (such as junction temperature, Tj, and/or ambient temperature),” par 0056 and “When the operating state changes from one ORE to a different ORE, the device adjusts the data forwarding rate to address the throughput specified by the new ORE. For example, the electronic device 200 may be operating in ORE1 at a point in time when the temperature and/or the device current are measured. The electronic device may determine, upon comparing the measured values to ranges as described above, that at least one of the temperature or the device current has increased, such that the measured value is in the respective range corresponding to ORE2 (or ORE3).” Par 0068) [the system monitors junction temperature to transition between OREs which includes adjusting thresholds used to regulate traffic until the current refresh period interval lapses, see paragraphs 52-58, 64, 65, 92, 100].
Regarding claim 20, Matthews teaches a switch (“the electronic device 200 can be a network switch in a server in a data center” par 0052 and Figure 2) comprising:
one or more ports (Figure 2, ports 208a-c); and
a power profile controller (Figure 2, traffic manager 206 and Figure 4, credit update controller 420).
The remainder of claim 20 corresponds to claim 1 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Matthews in view of Khatri et al. (US 2017/0031431 A1).
Regarding claim 3, Matthews teaches the system of claim 1. However, Matthews does not explicitly teach wherein the one or more circuits are further to correlate the monitored data traversing the system with the power consumption of the system and to adjust one or more of the first power threshold and the first bandwidth threshold based on the correlation to account for leakage of power until the first predetermined time period lapses.
In the analogous art, Khatri teaches wherein the one or more circuits are further to correlate the monitored data traversing the system with the power consumption of the system and to adjust one or more of the first power threshold and the first bandwidth threshold based on the correlation to account for leakage of power until the first predetermined time period lapses (“Micro-controller 122 determines the node peak power limits or thresholds 230 (i.e. node peak limits 166, 232, 234 and 236) and the node average power limits or thresholds 240 (i.e. node average limits 168, 242, 244 and 246) for each of the processing nodes based on the power-usage data and workload data,” par 0074 and “PMM 120 (FIG. 1) dynamically allocates peak and sustained node power limits for several processing nodes during operation of IHS 100 based on power-usage and workload data.” Par 0067 and “The node controllers are triggered to determine and set, based on the node peak power threshold, a device peak power limit for at least one variable performance device … dynamically adjusts a respective performance metric value based on the device peak power limit.” par 0008) [the PMM correlates real time monitored workload data with measured power usage (power leakage) to recalculate and reallocate (adjust) node and device thresholds that regulate both system power and bandwidth during each periodic monitoring (first predetermined time period)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Khatri before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Khatri to adjust the threshold based on monitored power to adapt power limits to real time node demands, optimizing power usage in the system.
Regarding claim 7, Matthews teaches the system of claim 6. However, Matthews does not explicitly teach wherein the system receives power from a power supply shared by one or more interconnect devices and processing devices, wherein the power consumption limit is associated with an amount of power consumed by the system from the power supply.
In the analogous art, Khatri teaches wherein the system receives power from a power supply shared by one or more interconnect devices and processing devices, wherein the power consumption limit is associated with an amount of power consumed by the system from the power supply (“PSUs 130A-D supply power to each of the processing nodes and other components within IHS 100 that require power via either one or more bus bars or power cables (not shown).” Par 0040 and “The power capability data includes data such as a total available system power of the IHS, including a peak power output capacity and a sustained output power capacity.” Par 0055) [the power supply units provide power to the processing nodes and other components (which also include interconnect devices, see par 45); the total available power from the PSUs is identified, which is used for calculating the power consumption limits].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Khatri before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Khatri to have a power supply shared by all components of the system to improve efficiency and have easier power regulation and distribution in the system.
Regarding claim 16, Matthews teaches the system of claim 1, However, Matthews does not explicitly teach wherein the power profile specifies two or more time periods, wherein the first predetermined time period is associated with one or more of the first bandwidth threshold and the first power threshold and a second predetermined time period is associated with one or more of a second bandwidth threshold and a second power threshold.
In the analogous art, Khatri teaches wherein the power profile specifies two or more time periods, wherein the first predetermined time period is associated with one or more of the first bandwidth threshold and the first power threshold and a second predetermined time period is associated with one or more of a second bandwidth threshold and a second power threshold (“PMM memory 220 further contains node peak power limits or thresholds 230 and node average power limits or thresholds 240 for each of the processing nodes 150A-D.” par 0055 and “CPU 1 180 and CPU 2 182 can be selectively operated for short time periods at operating frequencies and power consumption well above the thermal design power (TDP) level.” Par 0044 and “A total available system power of the IHS is identified including a peak power output capacity and a sustained output power capacity.” Par 0032 and Figures 1A-3C) [the PMM corresponds to power profile as it stores peak (short term) and average/sustained (longer term) thresholds for both power and bandwidth (data throughput) metrics, also see paragraph 55].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Khatri before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Khatri to have different time periods associated with different thresholds to improve power state transitions and data throttling efficiency and have easier power regulation in the system.
Claims 4, 9, 12-14, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Matthews in view of Trivedi et al. (US 2014/0019654 A1).
Regarding claim 4, Matthews teaches the system of claim 1. However, Matthews does not explicitly teach wherein the one or more circuits are further to update one or more of the first power threshold and the first bandwidth threshold based on a correlation of the monitored data traversing the system with the power consumption of the system.
In the analogous art, Trivedi teaches wherein the one or more circuits are further to update one or more of the first power threshold and the first bandwidth threshold based on a correlation of the monitored data traversing the system with the power consumption of the system (“An embodiment implements a policy that enables energy-efficient I/O operation by delivering a performance-power loadline for PCIe traffic.” Par 0046 and “Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement and intelligent decision making on the opportunistic down configuration and immediate up configuration of a link to provide power savings without impacting performance.” Par 0042) [the policy establishes a correlations between performance and power consumption via a loadline, affecting adjustment of thresholds].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Trivedi before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Trivedi to update the power and bandwidth thresholds based on data traversing the system and power consumption to improve system performance and efficiency.
Regarding claim 9, Matthews teaches the system of claim 8. However, Matthews does not explicitly teach wherein the one or more circuits are further to determine a power requirement based on the bandwidth limit.
In the analogous art, Trivedi teaches wherein the one or more circuits are further to determine a power requirement based on the bandwidth limit (“An embodiment includes a policy, implemented via hardware and/or software modules, for dynamically adjusting the width of links (e.g., PCIe links) based on runtime tracking of I/O bandwidth requirements and/or thermal monitors. Such an embodiment provides power savings when the bandwidth utilization is below the native link width and speed.” Par 0010 and “An embodiment implements a policy that enables energy-efficient I/O operation by delivering a performance-power loadline for PCIe traffic.” Par 0046 and “If both endpoints of the PCIe link support up configuration, then the PCIe uplink controller 130 of the downstream device 120 may initiate transition to the new width determined by the dynamic link policy.” Par 0029) [the performance power loadline, under BRI, allows determination of power requirement based on a given performance/bandwidth level].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Trivedi before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Trivedi to determine a power requirement based on the bandwidth limit to optimize energy efficiency and avoid providing excess power to components.
Regarding claim 12, Matthews teaches the system of claim 11. However, Matthews does not explicitly teach wherein at least one of the first bandwidth threshold is greater than the second bandwidth threshold and the at least one of the first power threshold is greater than the second power threshold.
In the analogous art, Trivedi teaches wherein at least one of the first bandwidth threshold is greater than the second bandwidth threshold and the at least one of the first power threshold is greater than the second power threshold (“In block 310 if the accumulated bandwidth requirement exceeds an upper threshold (Upth) then an up configuration takes place relatively immediately (block 315) (e.g., in less than 5 or 10 microseconds so as to minimize latency)… in block 325 it is determined if the accumulated bandwidth requirement is greater than a lower threshold (DnTh)” Par 0034 and Figure 5).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Trivedi before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Trivedi to have a lower second power and bandwidth thresholds to reduce leakage power without increasing latency. (Trivedi, paragraph 37)
Regarding claim 13, Matthews teaches the system of claim 11. However, Matthews does not explicitly tach wherein the first predetermined time period is of a lesser duration than the second predetermined time period.
In the analogous art, Trivedi teaches wherein the first predetermined time period is of a lesser duration than the second predetermined time period (“the second time period being longer than the first time period.” Par 0048).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Trivedi before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Trivedi to have the second predetermined time period being longer than the first predetermined time period to have stable threshold detection and prevent unnecessary power state switches or data limiting.
Regarding claim 14, Matthews teaches the system of claim 11. However, Matthews does not explicitly teach wherein a shaper circuit determines the at least one of the ingress bandwidth exceeds the first bandwidth threshold and the power consumption exceeds the first power threshold and determines the at least one of the ingress bandwidth exceeds the second bandwidth threshold and the power consumption exceeds the second power threshold.
In the analogous art, Trivedi teaches wherein a shaper circuit determines the at least one of the ingress bandwidth exceeds the first bandwidth threshold and the power consumption exceeds the first power threshold and determines the at least one of the ingress bandwidth exceeds the second bandwidth threshold and the power consumption exceeds the second power threshold (“PCIe controller 130 monitors runtime bandwidth” par 0016 and “In block 310 if the accumulated bandwidth requirement exceeds an upper threshold (Upth) then an up configuration takes place relatively immediately (block 315)… it is determined if the accumulated bandwidth requirement is greater than a lower threshold (DnTh).” par 0034 and “uplink 125 width may be limited based on thermal sensors (instead of or in addition to bandwidth factors discussed above). For example, if the temperature exceeds predetermined thresholds, the link may be limited to a narrower width in order to save power,” par 0040) [controller 130 corresponds to a shaper circuit].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Trivedi before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Trivedi to include a shaper circuit to check if power or bandwidth thresholds are exceeded to prevent system congestion by reducing network traffic.
Regarding claim 18, Matthews teaches the system of claim 1. However, Matthews does not explicitly teach wherein the power profile is one of a plurality of power profiles and each of the plurality of power profiles is associated with a respective application, wherein the one or more circuits are further to aggregate the plurality of power profiles and determine one or more of the first bandwidth threshold and the first power threshold based on the aggregated plurality of power profiles.
In the analogous art, Trivedi teaches wherein the power profile is one of a plurality of power profiles and each of the plurality of power profiles is associated with a respective application, wherein the one or more circuits are further to aggregate the plurality of power profiles and determine one or more of the first bandwidth threshold and the first power threshold based on the aggregated plurality of power profiles (“PCIe controller 130 receives inputs from integrated endpoints (e.g., device 140) and downstream ports (e.g., 160) about their respective maximum bandwidth requirement. Controller 130 then aggregates the individual inputs to compute the net uplink bandwidth requirement.” Par 0022 and “Once the required bandwidth is known, controller 130 may determine the appropriate link 125 width.” Par 0027 and “the PCIe controller may dynamically increase the width of the link when the determined bandwidth is greater than a first threshold (e.g., the present width LW)” par 0050) [the bandwidth requirements make up the power profile; the controller determines the appropriate link width which corresponds to setting a first threshold based on aggregated data; the thermal monitor information in the policy implies the determination of power thresholds are also based on the aggregated data].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Trivedi before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Trivedi to have individual power profiles for each application to simplify power management and optimize power distribution.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Matthews in view of Eckert et al. (US 2012/0130657 A1).
Regarding claim 10, Matthews teaches the system of claim 1. However, Matthews does not explicitly teach wherein the one or more circuits are further to measure one or more of a current and a voltage and calculate a moving average power consumption.
In the analogous art, Eckert teaches wherein the one or more circuits are further to measure one or more of a current and a voltage and calculate a moving average power consumption (“Power consumption in a part of an electronic circuit can be measured directly by simultaneously measuring time domain voltage U and current I within this part of the electronic circuit and calculating P=U*I. In particular, average power consumption can be evaluated based on measurements of average voltage and average current during specific hardware operation in a steady state system environment. ” par 0007).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Matthews and Eckert before him before the effective filing date of the claimed invention, to have modified Matthews to incorporate the teachings of Eckert to calculate a moving average power consumption to provide a more accurate and direct measurement of power consumption for enhanced energy-efficient dynamic system adjustments.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYMAN FATIMA whose telephone number is (571)270-0830. The examiner can normally be reached M to Fri between 8am and 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
Prosecution Insights