DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
On page 3 of Remarks filed 01/05/2026 applicant argues
Kouroussis fails to explicitly disclose a relationship between an overcurrent protection threshold for the solid-state switching device 202 and the current flowing through the solid-state switching device 202, or that the pulse mode applied to the solid- state switching device 202 operates to current-limit the fault current to less than the overcurrent protection threshold for the solid-state switching device 202.
Prior art Kouroussis (US 20190341213 A1) teaches the amended claim limitations in specification paragraph [0045]. Kouroussis recites in paragraph [0040], “Decision 524 queries whether the surge protection devices 404 are operating within their SOA, which in one embodiment of the invention is defined and set based on some predefined maximum number of times (counts) that a current pulse is allowed to be generated in the method 500. Each time a current pulse is generated at step 530, the microcontroller 204 increments an internal “inductive pulse counter.” Accordingly, if at decision 524 the microcontroller 204 determines that the number of counts recorded in the inductive pulse counter has exceeded the maximum allowable count defining the SOA of the protection devices (“NO” at decision 524), at step 522 the SSCB 202 is switched OFF permanently until an engineer or electrician can be dispatched to investigate and correct the problem. Otherwise, steps 526 and 528 are performed prior to pulsing the current back ON at step 530.”. Hence, Kouroussis teaches current-limiting based on threshold of solid-state switching device.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 8-9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kouroussis (US 20190341213 A1).
Regarding claim 1, Kouroussis teaches a solid-state circuit breaker (abstract, a solid-state circuit breaker (SSCB)) configured to current-limit a fault current during an electrical fault (abstract, SSCB is repeatedly switched ON and OFF during a short circuit event), the solid-state circuit breaker comprising:
an input (i.e. power bus bars 108 and neutral bars 110) (fig.1) configured to connect to a source ([0024], receive three-phase alternating current (AC) electrical power from an AC source);
an output (e.g. power hot bus bars 108 out of SCCB to breakers 104) (fig.1) configured to couple with at least a first load ([0024], plurality of loads) via a first electromechanical breaker ([0024], plurality of downstream mechanical CBs 104) and a second load ([0024], plurality of loads) via a second electromechanical breaker ([0024], plurality of downstream mechanical CBs 104);
a solid-state switch (i.e. solid-state circuit breaker (SSCB) 102) (fig.1) selectively coupling the input with the output ([0024], The received AC power is passed through a utility meter 106, through the SSCB102, and then distributed to a plurality of loads via the plurality of downstream mechanical CBs 104);
a protection circuit (e.g. circuit comprising current/voltage sensors 218, sense and drive circuit 206) (fig.2) communicatively coupled with the solid-state switch ([0031], the solid-state switching device 202 and operates in cooperation with the microcontroller 204 to react to line current and/or line voltage information measured or sensed by current/voltage sensors 218) and configured to open the solid-state switch in response to the fault current exceeding an overcurrent protection threshold ([0031], controlling the ON/OFF statuses of the power FETs 402 in the solid-state switching device 202 … during short circuit events) for the solid-state switch ([0045], To prevent irreversible damage to the surge protection devices 404 … predefined maximum number of times (counts) that a current pulse is allowed … at step 522 the SSCB 202 is switched OFF permanently); and
a control circuit (e.g. circuit comprising microcontroller 204) (fig.2) communicatively coupled with the solid-state switch ([0030], microcontroller 204 is responsible for directing and controlling the ON/OFF statuses of the power FETs 402 in the solid-state switching device 202) and configured to:
determine whether the electrical fault is present ([0031], during short-circuit events) ([0035], microcontroller 204 determines, based on line currents sensed by current/voltage sensors 218 (see FIG. 2), whether a short circuit is present); and
in response to determining that the electrical fault is present, operate the solid-state switch in a pulse conduction mode during the electrical fault to current-limit the fault current to less than the overcurrent protection threshold ([0031], “pulse” the voltage thereby controlling the current flowing through the power FETs 402 in the solid-state switching device 202) for the solid-state switch ([0045], To prevent irreversible damage to the surge protection devices 404 … predefined maximum number of times (counts) that a current pulse is allowed … at step 522 the SSCB 202 is switched OFF permanently) and enable one of the first and second electromechanical breakers to trip and isolate the electrical fault ([0040], allow one of the downstream mechanical CBs 104 to naturally trip).
Regarding claim 2, Kouroussis teaches the solid-state circuit breaker of claim 1, wherein: the control circuit is further configured to:
determine whether one of the first and second electromechanical breakers have tripped to isolate the electrical fault ([0046], determine whether the one of the downstream mechanical CBs 104 has been able to isolate the short circuit); and
maintain the solid-state switch closed in response to one of the first and second electromechanical breakers tripping to isolate the electrical fault ([0046], If one of the downstream mechanical CBs 104 does in fact trip and isolate the short circuit … enters a standby state).
Regarding claim 8, the method is rejected for the same reasons as stated above for claim 1.
Regarding claim 9, the method is rejected for the same reasons as stated above for claim 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kouroussis (US 20190341213 A1), and further in view of Kenan (GB 2617604 A).
Regarding claim 3, Kouroussis teaches the solid-state circuit breaker of claim 1.
Kouroussis does not teach, wherein: the solid-state switch comprises a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET).
Kenan teaches in a similar field of endeavor of power semiconductor switches, a solid-state switch (abstract, bidirectional power semiconductor switch 1) comprises a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) (abstract, a first silicon (Si) or silicon carbide (SiC) MOSFET 8).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the solid-state switch comprises a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) in Kouroussis, as taught by Kenan, as it provides the advantage of operating at higher voltages, handle greater power densities, switch faster with lower losses, and perform reliably in higher temperature environments.
Regarding claim 4, Kouroussis teaches the solid-state circuit breaker of claim 1.
Kouroussis does not teach, wherein: the solid-state switch comprises an insulated-gate bipolar transistor (IGBT).
Kenan teaches in a similar field of endeavor of power semiconductor switch, a solid-state switch (abstract, bidirectional power semiconductor switch 1) comprises an insulated-gate bipolar transistor (IGBT) (abstract, first IGBT 9).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the solid-state switch comprises an insulated-gate bipolar transistor (IGBT) in Kouroussis, as taught by Kenan, as it provides the advantage of low power losses and reacts against overvoltage during switching process.
Regarding claim 5, Kouroussis teaches the solid-state circuit breaker of claim 1.
Kouroussis does not teach, wherein: the protection circuit comprises a desaturation detection circuit.
Kenan teaches in a similar field of endeavor of power semiconductor switch, a protection circuit (page 6, desaturation of the IGBT 9 can be caused by a fault current, which can be easily detected) comprises a desaturation detection circuit (page 6, bidirectional power semiconductor switch 1 has a desaturation detection function).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the desaturation detection circuit in Kouroussis, as taught by Kenan, as it provides the advantage of protecting circuit from switching on under fault condition.
Regarding claim 6, Kouroussis teaches the solid-state circuit breaker of claim 1.
Kouroussis does not teach, wherein: the solid-state switch comprises a plurality of solid-state switches coupled in parallel with each other.
Kenan teaches in a similar field of endeavor of power semiconductor switch, a solid-state switch (abstract, bidirectional power semiconductor switch 1) comprises a plurality of solid-state switches coupled in parallel with each other (abstract, a first silicon (Si) or silicon carbide (SiC) MOSFET 8 and a parallel connected first IGBT 9).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the solid-state switch comprises a plurality of solid-state switches coupled in parallel with each other in Kouroussis, as taught by Kenan, as it provides the advantage of low power losses and reacts against overvoltage during switching process.
Regarding claim 10, the method is rejected for the same reasons as stated above for claim 3.
Regarding claim 11, the method is rejected for the same reasons as stated above for claim 4.
Regarding claim 12, the method is rejected for the same reasons as stated above for claim 5.
Regarding claim 13, the method is rejected for the same reasons as stated above for claim 6.
Claims 7 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Waldron (US 20170141558 A1), and further in view of Kouroussis (US 20190341213 A1).
Regarding claim 7, Waldron teaches a static transfer switch ([0002], static transfer switch).
Waldron does not teach, comprising: the solid-state circuit breaker of claim 1.
Kouroussis teaches in a similar field of endeavor of solid state circuit breaker, a solid-state circuit breaker of claim 1 (please see rejection of claim 1 above).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the solid-state circuit breaker of claim 1 in Waldron, as taught by Kouroussis, as it provides the advantage of quick response, while avoiding damaging arc formation.
Regarding claim 14, Waldron teaches a static transfer switch ([0031], circuit 100 … circuit 200, 300 is configured for switching the source 110 to the load 120, and the circuit 200A, 300A is configured for switching the source 115 to the load 120) configured to current-limit a fault current during an electrical fault ([0044], breaking the fault current or overvoltage), the static transfer switch comprising:
first and second inputs (e.g. inputs to 200, 300 and 200A, 300A) (fig.1B) configured to couple with first and second power sources (i.e. source 110, 115) (fig.1B), respectively;
first and second power stages (e.g. stages comprising 200, 300 and 200A, 300A) (fig.1B) configured to conduct electrical power when active ([0031], The circuit 200, 300 is configured for switching the source 110 to the load 120, and the circuit 200A, 300A is configured for switching the source 115 to the load 120), wherein the first power stage is configured to selectively couple the first input with the output, and wherein the second power stage is configured to selectively couple the second input with the output ([0031], The circuit 200, 300 is configured for switching the source 110 to the load 120, and the circuit 200A, 300A is configured for switching the source 115 to the load 120);
at least one protection circuit ([0044], controller 130 detects a fault) configured to deactivate one of the first and second power stages in response to the fault current exceeding an overcurrent protection threshold ([0044], controller 130 commands the IGBTs 210, 310 to turn OFF. Therefore, the circuit 200, 300 is opened) for the first and second power stages ([0047], the expected di/dt should be taken into account when establishing the predetermined or programmable delay);
and a control circuit communicatively coupled with the first and second power stages (i.e. controller 130’) (fig.1B).
Waldron does not teach, an output configured to couple with at least a first load via a first electromechanical breaker and a second load via a second electromechanical breaker;
and a control circuit configured to: determine whether the electrical fault is present; and in response to determining that the electrical fault is present, operate one of the first and second power stages in a pulse active mode during the electrical fault to current-limit the fault current to less than the overcurrent protection threshold for the first and second power stages until one of the first and second electromechanical breakers trips and isolates the electrical fault.
Kouroussis teaches in a similar field of endeavor of solid state circuit breaker, an output (e.g. power hot bus bars 108 out of SCCB to breakers 104) (fig.1) configured to couple with at least a first load ([0024], plurality of loads) via a first electromechanical breaker ([0024], plurality of downstream mechanical CBs 104) and a second load ([0024], plurality of loads) via a second electromechanical breaker ([0024], plurality of downstream mechanical CBs 104);
and a control circuit (e.g. circuit comprising microcontroller 204) (fig.2) configured to: determine whether the electrical fault is present ([0031], during short-circuit events) ([0035], microcontroller 204 determines, based on line currents sensed by current/voltage sensors 218 (see FIG. 2); and in response to determining that the electrical fault is present, operate one of solid-state switch ([0031], power FETs 402) in a pulse active mode during the electrical fault to current-limit the fault current to less than the overcurrent protection threshold ([0031], “pulse” the voltage thereby controlling the current flowing through the power FETs 402 in the solid-state switching device 202) for power stages ([0045], To prevent irreversible damage to the surge protection devices 404 … predefined maximum number of times (counts) that a current pulse is allowed … at step 522 the SSCB 202 is switched OFF permanently) until one of the first and second electromechanical breakers trips and isolates the electrical fault ([0040], allow one of the downstream mechanical CBs 104 to naturally trip).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the output configuration and control circuit configuration in Waldron, as taught by Kouroussis, as it provides the advantage of quick response, while avoiding damaging arc formation.
Regarding claim 15, it is rejected for the same reasons as stated above for claim 2.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Waldron (US 20170141558 A1) and Kouroussis (US 20190341213 A1), and further in view of Kenan (GB 2617604 A).
Regarding claim 16, it is rejected for the same reasons as stated above for claim 3.
Regarding claim 17, it is rejected for the same reasons as stated above for claim 4.
Regarding claim 18, it is rejected for the same reasons as stated above for claim 5.
Regarding claim 19, it is rejected for the same reasons as stated above for claims 3 and 5.
Regarding claim 20, it is rejected for the same reasons as stated above for claims 4 and 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 01/27/2026