DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 3-16 and 18 of US 12,591,326 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because they both claim a touch panel with wirings of conductive and metal layers formed around input region.
For example:
12,591,326 B2 claims 1 and 16
18/582,014 claim 1
1. A display comprising: a cover layer defining a first plane and positioned as a topmost layer; an array of pixels defining a second plane parallel to the first plane and disposed underneath the cover layer,
the array of pixels having a first area along the second plane,
1. A display comprising: a cover layer defining a first plane and positioned as a topmost layer; an array of pixels defining a second plane parallel to the first plane and disposed underneath the cover layer,
the array of pixels having a first area along the second plane;
one or more pixels of the array of pixels comprising at least one diode, the array of pixels having an inner region and an outer region, the outer region surrounding at least a portion of a perimeter of the inner region and comprising an extended emitting area;
the plurality of transistors comprising an internal region and an external region, the external region surrounding at least a portion of a perimeter of the internal region, the internal region comprising a first transistor density and the external region comprising a second transistor density; a touch sensor configured to detect user input; and one or more touch trace routings operatively coupled to the touch sensor, the one or more touch trace routings disposed between the cover layer and one or more pixels of the array of pixels in the extended emitting area.
a plurality of transistors defining a third plane substantially parallel to the second plane and positioned underneath the array of pixels, the plurality of transistors configured to control an electrical activation of one or more pixels within the array of pixels, the plurality of transistors having a second area along the third plane, the first area having an area larger than the second area, at least a portion of a difference in the areas including at least a portion of the extended emitting area,
a plurality of transistors defining a third plane substantially parallel to the second plane and positioned underneath the array of pixels, the plurality of transistors configured to control an electrical activation of one or more pixels within the array of pixels, the plurality of transistors having a second area along the third plane, the first area having an area larger than the second area, at least a portion of a difference in the areas being an extended emitting area;
13. further comprising: driving circuitry positioned at least partially within the third plane and at least partially underneath the extended emitting area, the driving circuitry configured to control one or more transistors of the plurality of transistors; and a plurality of routing metals operatively coupling one or more pixels of the array of pixels to the plurality of transistors, at least one routing metal of the plurality of routing metals extending from the third plane to the second plane into the extended emitting area such that at least one pixel of the one or more pixels is disposed above at least portions of the driving circuitry.
driving circuitry positioned at least partially within the third plane and at least partially underneath the extended emitting area, the driving circuitry configured to control one or more transistors of the plurality of transistors; and a plurality of routing metals operatively coupling one or more pixels of the array of pixels to the plurality of transistors, at least one routing metal of the plurality of routing metals extending from the third plane to the second plane into the extended emitting area such that at least one pixel of the one or more pixels is disposed above at least portions of the driving circuitry.
Claim(s) 1, 16
Claim(s) 1, 15
Claim(s) 3-15, 18
Claim(s) 2-20
It is clear that all the elements of the application claims 1-20 are to be found in patent claims 1, 3-16 and 18 (as the application claims 1-20 fully encompasses patent claims 1, 3-16 and 18). The difference between the application claims 1-20 and the patent claims 1, 3-16 and 18 lie in the fact that the patent claim includes many more elements and is thus much more specific. Thus the invention of claims 1, 3-16 and 18 of the patent is in effect a “species” of the “generic” invention of the application claims 1-20. It has been held that the generic invention is “anticipated” by the “species”. See In re Goodman, 29USPQ2d 2010 (Fed. Cir. 1993). Since application claims 1-20 are anticipated by claims 1, 3-16 and 18 of the patent, it is not patentably distinct from claims 1, 3-16 and 18 of the patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, and 13-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2022/0328590 A1 to Kim et al. (Kim).
As to claim 1, Kim (Fig. 2C and 8A-8B) discloses a display (1 or 10) comprising: a cover layer (CW) defining a first plane and positioned as a topmost layer (Fig. 2C, Pars. 30, 67); an array of pixels defining a second plane parallel to the first plane and disposed underneath the cover layer (CW) (Fig. 2C), the array of pixels having a first area along the second plane (Fig. 2C, note: the array of pixels in display panel 10 has a first area along the second curved plane of display panel 10 that includes FDA, MDA, and CDA);
a plurality of transistors (Fig. 8B; DC-TFT) defining a third plane substantially parallel to the second plane and positioned underneath the array of pixels (i.e. , DC-TFT positioned underneath of the array pixel LE); plurality of transistors configured to control an electrical activation of one or more pixels within the array of pixels [0091], the plurality of transistors having a second area (DC-TFT area) along the third plane (bottom plane), the first area having an area larger than the second area (i.e. each of LE areas having area larger than each of DC-TFT areas as shown in Fig.8B) , at least a portion of a difference in the areas being an extended emitting area (emitting area EA) (Notice plural transistors (pixel circuits in MDA) in a third plane below and parallel to the plane of the pixels of display panel 10 (pixels in CDA and those not shown in MDA).
driving circuitry (driving circuit DC) positioned at least partially within the third plane and at least partially underneath the extended emitting area (EA; see Fig. 8B), the driving circuitry configured to control one or more transistors of the plurality of transistors (i.e. a driving circuit DC for providing an electrical signal [0111]; this electrical signal is for turning ON/OFF transistor. Fig. 8B, driving circuitry DC is provided at least partially in the third plane as described above and at least partially underneath the extend emitting area including EA (in the CDA area); and
a plurality of routing metals operatively coupling one or more pixels of the array of pixels to the plurality of transistors, at least one routing metal of the plurality of routing metals extending from the third plane to the second plane into the extended emitting area such that at least one pixel of the one or more pixels is disposed above at least portions of the driving circuitry (Fig. 8B, the pixel electrodes 211 plurality of conductive routing metal the couple or more pixels of the array in CDA to the plural of transistors in MDA. Also, at least one routing metal 211 extends from the top of the third plane to the second plane of pixel COLED so that at least one pixel is above a portion of driving circuity DC-TFT).
As to claim 15, Kim teaches a wearable device of the display of claim 1 above. The limitation of claim 15 is substantially similar to claim 1. Accordingly, claim 15 is rejected based on same analysis as claim 1. Kim further discloses a wearable device (Par. 63) comprising: a housing (PA of 1) (Fig. 4A, Pars. 63, 101); one or more processors disposed within the housing (Fig. 4A, Pars. 63, 101); and a display operatively coupled to the one or more processors and at least partially disposed within the housing (Fig. 4A, Pars. 63, 101).
As to claim 4, Kim discloses one or more pixels of the array of pixels comprise at least one diode; and the array of pixels comprises an inner region and an outer region, the outer region surrounding at least portions of a perimeter of the inner region and comprising the extended emitting area (Fig. 8E, each pixel of FDA, MDA, and CDA provides a least one diode for light emission and that the array comprises an inner region of MDA and FDA combined and outer region of CDA. Also, the outer region of CDA surrounds at least a portion of the perimeter of the described inner region and provided the extended emitting area EA).
As to claim 16, Kim teaches a wearable device of the display of claim 4 above. The limitation of claim 16 is substantially similar to claim 4. Accordingly, claim 16 is rejected based on same analysis as claim 4.
As to claim 5, Kim discloses the inner region and the outer region each comprise a uniform distribution of pixels(Figs. 8A-8B and 8E, inner region MDA and outer region CDA have uniform distribution of pixels); and the plurality of transistors within the third plane (bottom plane) are uniformly distributed (Figs. 8A-8B and 8E, the plural transistors (DC-TFT) in the third plane of the pixel circuits area uniformly distributed).
As to claim 17, Kim teaches a wearable device of the display of claim 5 above. The limitation of claim 17 is substantially similar to claim 5. Accordingly, claim 17 is rejected based on same analysis as claim 5.
As to claim 13, Kim discloses each pixel of the array of pixels comprises one or more diodes [0261], and wherein each transistor of the plurality of transistors is operatively coupled to a respective diode of the one or more diodes. (Fig. 8A and Fig.3, each pixel PX2 of the array comprises one or more diodes (additional diode for subpixels) and that each transistor is operatively couple to at least a respective diode of the one or more diodes as shown in Fig.3 that each pixel PC comprises OLED and each transistor T1, T2 is operatively coupled to diode OLED).
As to claim 14, Kim discloses the display comprises an elliptical form factor. (Fig. 4A, the surface transition from FDA to MDA and from MDA to CDA with elliptical arcs provides a display of an elliptical form factor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0328590 A1 to Kim et al. (Kim) and US 2022/0310761 A1 to Kim et al. (Kim761).
As to claim 6, Kim discloses and the plurality of transistors within the third plane are uniformly distributed (Figs. 8A-8B and 8E, the plural transistors (DC-TFT) in the third plane of the pixel circuits area uniformly distributed).
Kim does not expressly disclose the inner region comprises a first pixel density and the outer region comprises a second pixel density, the first pixel density greater than the second pixel density.
Kim761 discloses the inner region (DA1) comprises a first pixel density and the outer region (DA2) comprises a second pixel density (Fig. 1, Par. 229), the first pixel density (in DA1) greater than the second pixel density (in DA2) (Fig. 1, Par. 229).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Kim with the teaching of Kim761 to clearly display the boundary between the first area and the second area as suggested by Kim761 (Par. 229).
Claims 7-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0328590 A1 to Kim et al. (Kim) and US 2024/0169947 A1 to Lin et al. (Lin).
As to claim 7, Kim does not expressly disclose the plurality of transistors comprise an internal region and an external region, the external region surrounding at least portions of a perimeter of the internal region.
Lin discloses the plurality of transistors comprise an internal region (10) and an external region (201) (Figs. 1-2, Par. 85), the external region (201) surrounding at least portions of a perimeter of the internal region (10) (Figs. 1-2, Par. 85).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Kim with the teaching of Lin to provide an improved photo sensitive area without increasing the size of the peripheral region as suggested by Lin (Par. 85)
As to claim 8, Kim as modified discloses the internal region (10) comprises a first transistor density (lower) and the external region (201) comprises a second transistor density (higher) (Lin’s Figs. 1-2, Par. 85). See claim 7 motivation above.
As to claim 18, Kim teaches a wearable device of the display of claims 7-8 above. The limitation of claim 18 is substantially similar to claim 7-8. Accordingly, claim 18 is rejected based on same analysis as claims 7-8.
As to claim 9, Kim as modified discloses: the first transistor density is smaller than the second transistor density (Lin’s Figs. 1-2, Par. 85); and the inner region and outer region comprise equivalent and uniform densities of pixels (Kim’s Figs. 8A-8B and 8E, inner region MDA and outer region CDA have uniform distribution of pixels (Figure 8E).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0328590 A1 to Kim et al. (Kim) and US 2024/0169947 A1 to Lin et al. (Lin); in view of US 2022/0310761 A1 to Kim et al. (Kim761).
As to claim 11, Kim as modified discloses the first transistor density is smaller than the second transistor density (Lin’s Figs. 1-2, Par. 85), and the inner region comprises a first pixel density and the outer region comprises a second pixel density (Kim’s Figs. 8A-8B and 8E, inner region MDA and outer region CDA have uniform distribution of pixels (Figure 8E).
Kim as modified does not expressly disclose the first pixel density greater than the second pixel density.
Kim761 discloses the inner region (DA1) comprises a first pixel density and the outer region (DA2) comprises a second pixel density (Fig. 1, Par. 229), the first pixel density (in DA1) greater than the second pixel density (in DA2) (Fig. 1, Par. 229).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Kim with the teaching of Kim761 to clearly display the boundary between the first area and the second area as suggested by Kim761 (Par. 229).
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0328590 A1 to Kim et al. (Kim) and US 2024/0169947 A1 to Lin et al. (Lin); in view of US 2020/0020274 A1 to Yue.
As to claim 10, Kim does not expressly disclose density of diodes in the inner region is equivalent to the first transistor density.
Kim discloses density of diodes in the inner region is equivalent to the first transistor density (Fig. 5, Par. 63).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Kim with the teaching of Yue to reduce the difference among the driving currents of the light-emitting diodes (Par. 63).
As to claim 19, Kim teaches a wearable device of the display of claims 9-10 above. The limitation of claim 19 is substantially similar to claim 9-10. Accordingly, claim 19 is rejected based on same analysis as claims 9-10.
Claims 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0328590 A1 to Kim et al. (Kim) and US 2024/0169947 A1 to Lin et al. (Lin); in view of US 2022/0310761 A1 to Kim et al. (Kim761); further in view of US 2020/0020274 A1 to Yue et al. (Yue).
As to claim 12, Kim does not expressly disclose a density of diodes in the inner region is equivalent to the first transistor density.
Kim discloses density of diodes in the inner region is equivalent to the first transistor density (Fig. 5, Par. 63).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to have modified Kim with the teaching of Yue to reduce the difference among the driving currents of the light-emitting diodes (Par. 63).
As to claim 20, Kim teaches a wearable device of the display of claims 11-12 above. The limitation of claim 20 is substantially similar to claim 11-12. Accordingly, claim 20 is rejected based on same analysis as claims 11-12.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARURAT SUTEERAWONGSA whose telephone number is (571)270-7361. The examiner can normally be reached Monday thru Thursday, 8:30AM to 4:00PM, EST.
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/JARURAT SUTEERAWONGSA/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623
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