DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Response to Arguments
Regarding: Prior Art Rejections:
Applicant’s amendments and arguments regarding the rejection of claims 1-17 and 19-20 under 35 U.S.C. 103 have been fully considered and are found to be not persuasive. The rejections of claims 1-17 and 19-20 under 35 U.S.C. 103 are maintained.
Applicant’s remarks recite:
executing a thread that accesses shared memory segments in a memory region
Dheap fails to teach or suggest this element of claim 1. In fact, a review of Dheap did not reveal one mention of a shared memory segment in a memory region. Rather, 11 [0026] and [0028] of Dheap disclose consuming memory resources in general, which does not equate to a thread accessing shared memory segments in a memory region, as recited in claim 1.
Dheap discloses multiple applications with memory allocations of the same region of memory ([0027] The memory management system 106 is configured to provide runtime configuration for the application server 102 and the one or more applications 104A-N to define a granular level of resource usage allotment; [0028] the resource can be memory or other objects, which are required for execution of the request threads or the applications 104A-N). Within the same region, each application and thread’s memory reservations may be allocated, deallocated, and reallocated ([0026] a memory management system 106 that is configured to manage memory allocation and de-allocation for various applications 104A-N). The memory allocations are shared as the objective of Dheap is to prevent memory leaks and crashes by gracefully terminating problematic zombie threads by the memory management system triggering garbage collection to free up memory and allow other threads/applications to utilize the problematic thread’s memory ([0028] The memory management system 106 is also configured to monitor the execution of the at least one request thread associated with the applications 104A-N; [0029] The memory management system may monitor the execution of the applications 104A-N and identify one or more applications 104A-N that should be terminated to avoid any memory related issue. The memory related issue can be such as, a memory leak, memory crash, and so forth … The memory management system 106 is further configured to trigger a garbage collection to perform clean up operation for the interrupted or terminated request thread).
deallocating shared memory segments from the memory region
Dheap further fails to teach or suggest deallocating shared memory segments from the memory region, as recited in claim 1. Dheap discloses triggering garbage collection to perform cleanup after a request thread is interrupted or terminated. 11 [0029] and [0038]. However, the garbage collection as disclosed in Dheap does not necessarily include deallocating shared memory segments from a memory region, as recited in claim 1.
Garbage collection in the context of a memory management system includes the deallocation of memory from the problematic request thread ([0038] garbage collection is performed to free memory for the problematic request thread. Request threads operate independently and are usable to service requests and create responses in an application server. For example, if there are 100 request threads, then each of those threads can be serviced concurrently. In an embodiment, the garbage collection may be performed using a Java garbage collection module).
causing a thread to execute, upon resuming execution, a thread-terminating instruction that terminates the thread
Clift fails to disclose this element of claim 1. Rather,1 [0033] of Clift discloses that an interrupt handler aborts thread execution or terminates a thread. In contrast with claim 1, the interrupt handler does not cause a thread that has been suspended to execute a thread-terminating instruction upon resuming execution. Rather, in Clift, the thread is aborted or terminated by the interrupt handler. As such, the thread does not resume execution then execute a thread-terminating instruction, as recited in claim 1.
Clift discloses thread termination within the context of a Windows Operating system ([0015] Once an interrupt is detected, the occurrence of the interrupt may be passed on to an application, such as an operating system, that takes the appropriate remedial action. For instance, an operating system may abort the execution of the instructions (e.g., via an exception). In other instances, the operating system may terminate a process thread that includes the instructions; [0024] In illustrative embodiments where the operating system is a Windows.RTM. operating system running in native 32 bit mode). Within the operating system art, threads self-terminate with the use of either ExitThread() or return microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-exitthread.
marking a memory region as closed
Eidelman fails to teach or suggest this claim element. Rather, col. 11, lines 40-54 of Eidelman discloses a method for updating a page status as being unavailable. However, the Office has not established that the prior art recognizes updating a page status to unavailable as being equivalent to marking a memory region as closed, as recited in claim 1.
Examiner’s interpretation of marking the memory region as closed includes indicating using some variable/flag that a chunk of memory is to not be used in any event where memory is deallocated and reclaimed. Eidelman discloses designation of memory pages as being unavailable in deallocation and freeing of memory (handles the memory controller 204 IRQ that notifies on page transition to available state (PAGE_VALID) … handles the memory controller 204 IRQ that notifies on page transition to unavailable state (PAGE.sub.— INVALID), in col 8 15-20).
the Office has not established that the prior art recognizes a page as being equivalent to a memory region, as recited in claim 1.
A memory page in the art is synonymous with a memory region as a page represents a common fixed block of memory (geeksforgeeks.org/operating-systems/paging-in-operating-system/).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-14, 16, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dheap et al. US 20140137131 A1 in view of Clift et al. US 20100017581 A1 in view of Eidelman US 10162665 B1.
Regarding claim 1, Dheap teaches the invention substantially as claimed including:
One or more non-transitory computer-readable media storing instructions that, when executed by one or more hardware processors, cause performance of operations ([0015] Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium) comprising:
executing a first thread ([0026] The application server 102 may execute at least one request thread for the at least one of the applications 104A-N based on the received query), wherein the first thread accesses at least one shared memory segment of a set of shared memory segments in a memory region ([0026] a memory management system 106 that is configured to manage memory allocation and de-allocation for various applications 104A-N; [0028] the resource can be memory or other objects, which are required for execution of the request threads or the applications 104A-N);
instructing the first thread to suspend execution ([0008] The monitoring further includes sending at least one notification to the at least one request thread to interrupt or terminate it based on a memory related issue);
subsequent to the first thread being terminated, deallocating the at least one shared memory segment from the memory region; reclaiming the memory region ([0029] The memory management system 106 is configured to terminate any runaway or problematic request threads (or zombie threads), which may not respond to the notifications sent by the memory management system 106. The memory management system 106 is further configured to trigger a garbage collection to perform clean up operation for the interrupted or terminated request thread).
Dheap does not explicitly teach responsive to determining that the first thread was suspended during execution of a function comprising a memory access operation: causing the first thread to execute, upon resuming execution, a thread-terminating instruction that terminates the first thread, wherein the thread-terminating instruction prevents the first thread from further executing at least a portion of the function comprising the memory access operation;
However, Clift teaches responsive to determining that the first thread was suspended during execution of a function comprising a memory access operation: causing the first thread to execute, upon resuming execution, a thread-terminating instruction that terminates the first thread ([0033] as the instruction 308 of the process thread 302 is being processed by the processor, the interrupt handler 118 may note that the instruction 308 is marked by a software flag 316. The software flag 316 may indicate that instruction 308 is in the critical region 314. Subsequently, in the event that the execution of the process thread 302 is disputed by an interrupt 322 caused by the executing of instruction 324, the interrupt handler 118 may generate an exception because software flag 316 is present. The interrupt handler 118 may then reflect the exception to the processor to cause an abort of thread execution and/or termination of the process thread 302 … once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction), wherein the thread-terminating instruction prevents the first thread from further executing at least a portion of the function comprising the memory access operation ([0040] the interrupt handler module 414 may cause an immediate abort of execution and/or termination of the process thread in response to an exception; Examiner notes: immediate termination of the process thread prevents any remaining instruction from finishing);
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Clift’s termination of suspended threads in critical sections with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of minimizing conflict in memory issues within shared memory (see Clift [0002] However, the use of process memory heaps still does not guarantee that a particular heap associated with a first processor will not have to be accessed by a second processor. Such heap accesses may occur due to quantum end events or other rescheduling events. Thus, computer codes that employ process memory heaps nevertheless also use process thread locks or thread interlocked sequences during memory manipulation by multiple processors. These locks can create a relatively large processing overhead for a multi-processor computer system in order to deal with generally rare situations. Moreover, in certain instances, the use of interlocked sequences or lock free sequences on memory heaps or stacks may result in bad memory references and errors).
Dheap and Clift do not explicitly teach marking the memory region as closed;
However, Eidelman teaches marking the memory region as closed (FIG. 9 shows a method 400 for updating the page status as being unavailable before evicting a page … At 410, control updates the page status as being unavailable using the hypervisor. For example, the hypervisor 206 updates the page status as being unavailable, Col 11 40-54);
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Eidelman’s updating of memory as unavailable with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of disallowing access to memory to be deallocated to prevent memory leaks (see Eidelman Col 11 64 - Col 12 5, The systems and methods prevent CPU's from directly accessing the pages that are unavailable. Instead, the pages are requested from the memory controller via control channel, which eliminates stalling of the CPU's on such accesses. The systems and methods allow the OS kernel to suspend threads that issued an access to an unavailable page until the page becomes available. The systems and methods ensure that no CPU caches have dirty content that map to unavailable pages).
Regarding claim 2, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Clift further teaches wherein causing the first thread to execute the thread-terminating instruction is further responsive to determining that the memory access operation is for accessing the memory region ([0033] once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction).
Regarding claim 7, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Clift further teaches wherein the memory access operation comprises an atomic operation ([0013] This disclosure is directed to embodiments that enable low overhead atomic memory operations. Atomic memory operations are a set of operations performed in memory such that they appear to the rest of the computing system as a single memory operation), wherein the atomic operation comprises either:
determining that the memory region is active and accessing the memory region; or determining that the memory region is closed and refraining from accessing the memory region ([0013] Atomic memory operations typically generate two outcomes: (1) successful execution of the operation; or (2) failure to execute the operation. In order to accomplish an atomic memory operation, no other process can change the atomic memory operation. Further, if any step that is part of the atomic operation fails, then the entire operation will fail and the data affected by the atomic operation will be restored to its original state; [0014] the interrupt may occur as result of an operating system context switch. In another instance where the processor is part of a multi-processor system, the data processed by a first processor may be a global variable, and therefore an interrupt may occur when a second processor of the multi-processor system carries out a process that concurrently modifies the global variable).
Regarding claim 8, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Dheap further teaches wherein causing the first thread to execute, upon resuming execution, the thread-terminating instruction comprises: instructing the first thread to evaluate a set of one or more thread-terminating criteria, and executing the thread-terminating instruction in response to determining that the set of one or more thread-terminating criteria is satisfied ([0040] As the request thread continues it's execution, the monitoring engine 208 determines that the resource usage of the request thread has become critically close to the defined limits i.e. system threshold value(s) or resource threshold value(s) and may send a notification to the request thread to halt processing if possible. If after receiving the notification, the application associated with or servicing the problematic request thread can terminate and clean up the action, then the monitoring engine 208 will be able to monitor stabilization in the resource consumption. Thereafter, the monitoring engine 208 may attempt to trigger garbage collection such as Java garbage collection to try and cleanup as necessary. If after receiving the notification, the application servicing the problematic request thread either does not or cannot stop or clean up the action, then the monitoring engine 208 may attempt to sacrifice this request thread and interrupt or terminate the request thread based on the severity of the memory related issue).
Regarding claim 9, Dheap, Clift, and Eidelman teach the one or more non-transitory computer-readable media of claim 8.
Dheap further teaches wherein the set of one or more thread-terminating criteria comprises at least one of:
upon resuming execution, the first thread will not terminate execution prior to executing the memory access operation without executing the thread-terminating instruction ([0029] The memory management system 106 is configured to terminate any runaway or problematic request threads (or zombie threads), which may not respond to the notifications sent by the memory management system 106); or
upon resuming execution, the first thread will not terminate execution within a specified time limit without executing the thread-terminating instruction.
Clift further teaches upon resuming execution, the first thread will execute the function comprising the memory access operation ([0040] the interrupt handler module 414 may be configured to permit the execution of one or more additional instructions in a process thread following an exception, before aborting the execution and/or terminating the process thread);
Regarding claim 10, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Clift further teaches wherein the first thread executes the thread-terminating instruction in response to determining that the first thread, upon resuming execution, (a) will execute the function comprising the memory access operation ([0033] It will be appreciated that once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction; [0040] terminate a process thread that includes one or more instructions in a critical region) and (b) will not terminate execution prior to executing the memory access operation without executing the thread-terminating instruction ([0040] the interrupt handler module 414 may be configured to permit the execution of one or more additional instructions in a process thread following an exception, before aborting the execution and/or terminating the process thread).
Regarding claim 11, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Clift further teaches wherein determining that the first thread was suspended during execution of the function comprising the memory access operation comprises: determining the function being executed by the first thread when execution of the first thread was suspended ([0033] It will be appreciated that once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt), and determining whether the function comprises the memory access operation ([0031] As used herein, a critical region includes instructions of a process thread that manipulate shared data. Shared data are data that may are capable of being manipulated by multiple process threads. For example, in a multi-process computer system, the system may be configured to execute multiple threads running on different processors that can manipulate the same global variable).
Regarding claim 12, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Clift further teaches wherein the operations further comprise: prior to marking the memory region as closed, executing a second thread, wherein the second thread accesses at least one shared memory segment of the set of shared memory segments in the memory region; wherein subsequent to marking the memory region as closed, the second thread terminates execution in response to determining that the memory region is marked as closed ([0020] Accordingly, the interrupt 114 may be caused by a second processor that accesses the data concurrently in order to modify the global variable with the instruction 116. Such an access by the second processor may cause a race condition to occur; [0031] in a multi-process computer system, the system may be configured to execute multiple threads running on different processors that can manipulate the same global variable; [0033] It will be appreciated that once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction; Examiner notes: multiple threads are able to access the modified global variable and require termination due to lost atomicity).
Regarding claim 13, Dheap, Clift, and Eidelman teach the one or more non-transitory computer-readable media of claim 12.
Clift further teaches wherein the second thread was suspended during execution of a function that does not include a memory access operation, or wherein the second thread was suspended subsequent to execution of the function comprising the memory access operation (([0020] Accordingly, the interrupt 114 may be caused by a second processor that accesses the data concurrently in order to modify the global variable with the instruction 116. Such an access by the second processor may cause a race condition to occur; [0031] in a multi-process computer system, the system may be configured to execute multiple threads running on different processors that can manipulate the same global variable; [0033] It will be appreciated that once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction; Examiner notes: multiple threads are able to access the modified global variable and require suspension due to lost atomicity).
Regarding claim 14, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Clift further teaches wherein the operations further comprise: subsequent to marking the memory region as closed, executing a second thread, wherein the second thread determines that the memory region is marked as closed, and wherein the second thread terminates execution in response to determining that the memory region is marked as closed ([0020] Accordingly, the interrupt 114 may be caused by a second processor that accesses the data concurrently in order to modify the global variable with the instruction 116. Such an access by the second processor may cause a race condition to occur; [0031] in a multi-process computer system, the system may be configured to execute multiple threads running on different processors that can manipulate the same global variable; [0033] It will be appreciated that once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction; Examiner notes: multiple threads are able to access the modified global variable and require termination due to lost atomicity).
Regarding claim 16, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Dheap further teaches a set of threads, including the first thread ([0029] The memory management system 106 is configured to terminate any runaway or problematic request threads (or zombie threads).
Eidelman further teaches wherein deallocating the at least one shared memory segment from the memory region is executed in response to determining that a set of threads, including the first thread, have terminated execution (Fig 6; An IRQ handler in the OS kernel 210 invokes a hypervisor call (HVC) while the page eviction is on hold. The hypervisor 206 handles the hypervisor call as follows. The cache/fib operations are described below in terms of ARMv8 instructions for example only. The hypervisor 206 reads the page address (PA) from a register in the memory controller 204. The hypervisor 206 sets the stage-2 table entries for the PA to indicate that the page is not present (not available). The hypervisor 206 invalidates the translation lookaside buffer (TLB) to ensure that the stage-2 table entries modified above take effect for all processors 203. The hypervisor 206 cleans/invalidates processor caches that may subsequently require the PA. The hypervisor 206 acknowledges the event by writing to a register of the memory controller 204. At this point, the memory controller 204 can proceed with evicting the page as no more accesses from any processor 203 to this page are possible).
Regarding claim 19, it is the method of claim 1. Therefore, it is rejected for the same reasons as claim 1.
Regarding claim 20, it is the system of claim 1. Therefore, it is rejected for the same reasons as claim 1.
Claims 3, 4, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Dheap et al. US 20140137131 A1 in view of Clift et al. US 20100017581 A1 in view of Eidelman US 10162665 B1 in view of Ingegneri US 10649790 B1.
Regarding claim 3, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Dheap further teaches wherein initiating the synchronous handshake comprises transmitting an instruction to suspend execution ([0028] The memory management system 106 is also configured to send at least one notification to the at least one request thread to interrupt or terminate the request thread based on a memory related issue or the received notification; [0040] send a notification to the request thread to halt processing if possible); and
wherein the first thread executes the instruction to suspend execution ([0040] If after receiving the notification, the application associated with or servicing the problematic request thread can terminate and clean up the action).
Dheap, Clift, and Eidelman do not explicitly teach wherein instructing the first thread to suspend execution comprises initiating a synchronous handshake.
However, Ingegneri teaches wherein instructing the first thread to suspend execution comprises initiating a synchronous handshake (A termination handshake may close the TCP connection, and the client/server threads may be terminated, Col 24 24-25).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Ingegneri’s TCP termination handshake with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of direct client-server connection with network synchronization via TCP (see Ingegneri Col 18 26-40, a single network connection (e.g., TCP connection) may be used for sending the commands and data associated with the calls. As shown in the example of FIG. 6A and FIG. 6B, the single connection may use a socket 659 on the client side and a corresponding socket 671 on the server side. In one embodiment, multiple network connections (e.g., TCP connections) may be used for sending the commands and data, e.g., using one connection per application thread. The use of multiple network connections for commands and data may prevent one application thread from obstructing other threads by clogging a single connection with a large quantity of data. In this manner, the various application threads may generate and send commands (e.g., graphics commands) to the GPU server over the network for execution using the virtual GPU.).
Regarding claim 4, Dheap, Clift, and Eidelman teach the one or more non-transitory computer-readable media of claim 3.
Clift further teaches wherein instructing the first thread to suspend execution comprises instructing the first thread to suspend execution at a safepoint ([0020] Such an access by the second processor may cause a race condition to occur. The race condition may alter the data being manipulated by the instructions 104-110, so that the instructions 104-110 may produce an unexpected result; [0033] It will be appreciated that once the interrupt handler 118 has recognized that the processing of an instruction in a critical region, such as instruction 308 in critical 316, is followed by an interrupt, the interrupt handler 118 may be configured to abort thread execution and/or terminate the corresponding process thread, such as process thread 302, at any point subsequent to the instruction and prior to a commitment instruction; Examiner notes: terminating the thread processing a critical region of memory with interrupt is considered a safepoint as no further processing is performed utilizing corrupt memory values).
Regarding claim 17, Dheap, Clift, and Eidelman teach the one or more non-transitory computer-readable media of claim 16.
Dheap further teaches instructing each thread, of the set of threads, to suspend execution at least by initiating a synchronous handshake with each thread, wherein initiating the synchronous handshake comprises transmitting an instruction to suspend execution ([0028] The memory management system 106 is also configured to send at least one notification to the at least one request thread to interrupt or terminate the request thread based on a memory related issue or the received notification; [0040] send a notification to the request thread to halt processing if possible),
wherein initiating the synchronous handshake with each thread directly or indirectly causes each thread to terminate upon resuming execution ([0040] If after receiving the notification, the application associated with or servicing the problematic request thread can terminate and clean up the action).
Dheap, Clift, and Eidelman do not explicitly teach the handshake to be synchronous.
However, Ingegneri teaches wherein instructing the first thread to suspend execution comprises initiating a synchronous handshake (A termination handshake may close the TCP connection, and the client/server threads may be terminated, Col 24 24-25).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Ingegneri’s TCP termination handshake with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of direct client-server connection with network synchronization via TCP (see Ingegneri Col 18 26-40, a single network connection (e.g., TCP connection) may be used for sending the commands and data associated with the calls. As shown in the example of FIG. 6A and FIG. 6B, the single connection may use a socket 659 on the client side and a corresponding socket 671 on the server side. In one embodiment, multiple network connections (e.g., TCP connections) may be used for sending the commands and data, e.g., using one connection per application thread. The use of multiple network connections for commands and data may prevent one application thread from obstructing other threads by clogging a single connection with a large quantity of data. In this manner, the various application threads may generate and send commands (e.g., graphics commands) to the GPU server over the network for execution using the virtual GPU.).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Dheap et al. US 20140137131 A1 in view of Clift et al. US 20100017581 A1 in view of Eidelman US 10162665 B1 in view of Collins US 11586467 B1.
Regarding claim 5, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Dheap, Clift, and Eidelman do not explicitly teach wherein causing the first thread to execute the thread-terminating instruction comprises initiating an asynchronous handshake, wherein initiating the asynchronous handshake comprises transmitting the thread- terminating instruction; and wherein the first thread executes the thread-terminating instruction upon resuming execution.
However, Collins teaches wherein causing the first thread to execute the thread-terminating instruction comprises initiating an asynchronous handshake, wherein initiating the asynchronous handshake comprises transmitting the thread- terminating instruction (When user process 118A receives the request to invoke a termination procedure at processing coordinator 116A, processing coordinator 116A and user process 118A can perform a termination handshake procedure to determine when the worker 114A can be terminated. To prevent data loss from occurring as a consequence of the termination procedure, processing coordinator 116A can halt message acceptance from external data sources. Meanwhile, user process 118A can continue to process any pending messages, Col 7 18-26); and wherein the first thread executes the thread-terminating instruction upon resuming execution (When the user process has both completed processing pending messages and determined that processing coordinator 116A has halted acceptance of any new messages, user process 118A can determine that worker 114A is in condition for termination on compute resources 100, Col 7 26-31).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Collins’ asynchronous worker termination handshake procedure with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of preventing data loss resulting from termination (see Collins Col 7 44-48, By terminating a worker 114 using termination commands processed by both a processing coordinator 116 and a user process 118 of the worker 114, the data processing pipeline may be scaled down reliably such that data is not lost during the termination process).
Regarding claim 6, Dheap, Clift, Eidelman, and Collins teach the one or more non-transitory computer-readable media of claim 5.
Collins wherein the asynchronous handshake is executed by the first thread chronologically first upon resuming execution (When user process 118A receives the request to invoke a termination procedure at processing coordinator 116A, processing coordinator 116A and user process 118A can perform a termination handshake procedure to determine when the worker 114A can be terminated, Col 7 18-; Examiner notes: termination handshake is initialized but other processes may wrap up while waiting to terminate i.e., asynchronous).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Dheap et al. US 20140137131 A1 in view of Clift et al. US 20100017581 A1 in view of Eidelman US 10162665 B1 in view of Fang et al. US 20190205250 A1.
Regarding claim 15, Dheap, Clift and Eidelman teach the one or more non-transitory computer-readable media of claim 1.
Dheap, Clift, and Eidelman do not explicitly teach wherein the operations further comprise: determining that the memory region is no longer being utilized; and marking the memory region as closed in response to determining that the memory region is no longer being utilized.
However, Fang teaches wherein the operations further comprise: determining that the memory region is no longer being utilized; and marking the memory region as closed in response to determining that the memory region is no longer being utilized ([0140] the idle duration of the memory page represents a duration that the data stored in the memory page is in a non-used state after being used recently after the system allocates a memory to the application to be processed. The electronic device updates the idle duration of each memory page in real time according to the data using situation of each memory page, and when it is prepared to reclaim the memory page occupied by the application to be processed, the idle duration of each reclaimable memory page recently recorded may be determined; [0141] The reclaiming proportion of 40% is taken as an example, and reclaimable memory pages of which the idle durations are within the first 40% may be reclaimed. By reclaiming memory pages according to the idle duration, reclaimable memory pages occupied for a long time may be immediately reclaimed, thereby reducing the influence on the application to be processed).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Fang’s idle based memory reclamation with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of reclaiming the limited unused memory (see Fang [0003] Since the memory capacity of the electronic device is limited, when the memory occupied by background applications is excessive, the operation efficiency of a foreground application may be affected. Therefore, it is necessary to reclaim the memory, so as to improve the operation efficiency of the foreground application.).
Allowable Subject Matter
Claim 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
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examiner can normally be reached Monday-Friday 9:00am-5:30pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing
using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is
encouraged to use the USPTO Automated Interview Request (AIR) at
http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Aimee Li can be reached on (571) 272-4169. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.L./
Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
Prosecution Insights