Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Amendment filed 3/23/2026.
Claims 1-24 are pending for this examination.
Claims 1, 11, 13, and 18 were amended.
Claim Rejections - 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coteus et al. (US 2001/0038106), herein referred to as Coteus ‘106.
Referring to claim 1, Coteus ‘106 teaches a memory system (see Fig. 6, computer system with DIMMs 650 comprising multiple DRAM 640, and memory controller 620) comprising:
a memory controller (see Fig. 6, memory controller 620); and
a memory apparatus coupled to the memory controller (see Fig. 6, DIMMs 650) through a data bus (see Fig. 6, data bus 660) and a command address bus (see Fig. 6, command/address bus 670, see Paragraph 0036), and configured to receive a command address signal through the command address bus (see Paragraph 0036, wherein separate command/address busses may go to each DIMM or made common, in which addresses, commands, and data are transmitted, i.e. address signals, command signals, and data signals),
wherein one of the memory controller and the memory apparatus is configured to transmit, through the command address bus, data to the other one of the memory controller and the memory apparatus (see Paragraph 0036, where memory controller receives or sends data to the memory through data bus 660 and tells RAM to read or be written to through command/address bus 670; Examiner notes that “data” as written here in the claim language is highly generic and can be interpreted as just information, which would include command/address signals which are used to control RAM, and data to be stored, i.e. both command/address and data are all considered “data” that is transmitted between a memory and memory controller as both parts are information needed for any memory transaction to occur, hence under the currently claim language “data” being transmitted through the command address bus can be interpreted as information needed to perform a memory transaction).
As to claim 2, Coteus ‘106 teaches the memory system of claim 1, wherein the data which the memory controller transmits to the memory apparatus is data to be programmed into the memory apparatus, and the data which the memory apparatus transmits to the memory controller is data to be read from the memory apparatus (see Paragraph 0036, wherein memory controller sends write data to memory or receives read data from memory, i.e. write data being data to be programmed into memory, and read data being data read from the memory).
As to claim 3, Coteus ‘106 teaches the memory system of claim 1, wherein the one of the memory controller and the memory apparatus is configured to transmit, through the data bus, a first portion of the data to the other one of the memory controller and the memory apparatus and configured to transmit, through the command address bus, a second portion of the data to the other one of the memory controller and the memory apparatus (see Paragraph 0036, where memory controller receives or sends data to the memory through data bus 660 and tells RAM to read or be written to through command/address bus 670; Examiner notes that “data” as written here in the claim language is highly generic and can be interpreted as just information, which would include command/address signals which are used to control RAM, and data to be stored, i.e. both command/address and data are all considered “data” that is transmitted between a memory and memory controller as both parts are information needed for any memory transaction to occur, hence under the currently claim language a first portion of “data” being transmitted across data bus and a second portion of “data” being transmitted through the command address bus can be interpreted as normal operation for a memory transaction as command/address signals and data are being transmitted).
As to claim 4, Coteus ‘106 teaches the memory system of claim 3, wherein the first portion of the data, which is transmitted through the data bus, is synchronized with a data strobe signal (see Fig. 2B, data strobe generator 214; see Paragraph 0024, wherein the data strobe generator synchronizes the output data (for a read) through the output buffer 216 such that clock and output data are in phase) and the second portion of the data, which is transmitted through the command address bus, is synchronized with a command clock signal (see Paragraph 0036, wherein a clock can come from a separate chip which synchronizes all components where the clock is sent with address, command, and data with clock bus 680).
Referring to claim 5, Coteus ‘106 teaches an operating method (see Paragraph 0036) of a memory system (see Fig. 6, computer system with DIMMs 650 comprising multiple DRAM 640, and memory controller 620) including a memory controller (see Fig. 6, memory controller 620) and a memory apparatus (see Fig. 6, DIMMs 650), the operating method comprising:
transmitting, by one of the memory controller and the memory apparatus, a first portion of data to the other one of the memory controller and the memory apparatus through a data bus (see Paragraph 0036, where memory controller receives or sends data to the memory through data bus 660 and tells RAM to read or be written to through command/address bus 670; Examiner notes that “data” as written here in the claim language is highly generic and can be interpreted as just information, which would include command/address signals which are used to control RAM, and data to be stored, i.e. both command/address and data are all considered “data” that is transmitted between a memory and memory controller as both parts are information needed for any memory transaction to occur, hence under the currently claim language “data” being transmitted through the command address bus can be interpreted as information needed to perform a memory transaction), and transmitting, by the memory controller, a mode command signal to the memory apparatus through the command address bus (see Fig. 2B, mode register 272; see Paragraph 0028, wherein the memory controller or other external device can use special command (mode register write) by proper selection of CKE, CS, RAS, CAS, and WE signals where the command is contained in the address field and directed to a mode register 272 on the SDRAM-DDR memory assembly, see Fig. 2); and
transmitting, by the one of the memory controller and the memory apparatus, a second portion of the data to the other one of the memory controller and the memory apparatus through the command address bus (see Paragraph 0036, where memory controller receives or sends data to the memory through data bus 660 and tells RAM to read or be written to through command/address bus 670; Examiner notes that “data” as written here in the claim language is highly generic and can be interpreted as just information, which would include command/address signals which are used to control RAM, and data to be stored, i.e. both command/address and data are all considered “data” that is transmitted between a memory and memory controller as both parts are information needed for any memory transaction to occur, hence under the currently claim language “data” being transmitted through the command address bus can be interpreted as information needed to perform a memory transaction).
As to claim 6, Coteus ‘106 teaches the operating method of claim 5, wherein the transmitting of the first portion of the data includes transmitting, by the one of the memory controller and the memory apparatus, a data strobe signal to the other one of the memory controller and the memory apparatus, the data strobe signal being synchronized with the first portion of the data (see Fig. 2B, data strobe generator 214; see Paragraph 0024, wherein the data strobe generator synchronizes the output data (for a read) through the output buffer 216 such that clock and output data are in phase).
As to claim 7, Coteus ‘106 teaches the operating method of claim 5, wherein the transmitting of the second portion of the data includes transmitting, by the one of the memory controller and the memory apparatus, a command clock signal to the other one of the memory controller and the memory apparatus, the command clock signal being synchronized with the second portion of the data (see Paragraph 0036, wherein a clock can come from a separate chip which synchronizes all components where the clock is sent with address, command, and data with clock bus 680).
Referring to claim 11, Coteus ‘106 teaches a memory system (see Fig. 6, computer system with DIMMs 650 comprising multiple DRAM 640, and memory controller 620) comprising:
a memory controller (see Fig. 6, memory controller 620); and
a memory apparatus coupled to the memory controller (see Fig. 6, DIMMs 650) through a data bus (see Fig. 6, data bus 660) and a command address bus (see Fig. 6, command/address bus 670, see Paragraph 0036), and configured to receive a command address signal through the command address bus (see Paragraph 0036, wherein separate command/address busses may go to each DIMM or made common, in which addresses, commands, and data are transmitted, i.e. address signals, command signals, and data signals),
where the memory controller is configured to transmit, during a data input operation (Examiner points out data input operation can be interpreted as a data write operation), a first portion of data to the memory apparatus through the data bus and a second portion of data to the memory apparatus through the command address bus (see Paragraph 0036, where memory controller receives or sends data to the memory through data bus 660 and tells RAM to read or be written to through command/address bus 670; Examiner notes that “data” as written here in the claim language is highly generic and can be interpreted as just information, which would include command/address signals which are used to control RAM, and data to be stored, i.e. both command/address and data are all considered “data” that is transmitted between a memory and memory controller as both parts are information needed for any memory transaction to occur, hence under the currently claim language a first portion of “data” being transmitted across data bus and a second portion of “data” being transmitted through the command address bus can be interpreted as normal operation for a memory transaction as command/address signals and data are being transmitted), and
wherein the memory apparatus is configured to transmit, during a data output operation (Examiner points out that a data output operation can be interpreted as a read operation), the first portion of data to the memory controller through the data bus and the second portion of data to the memory controller through the command address bus (see Paragraph 0036, where memory controller receives or sends data to the memory through data bus 660 and tells RAM to read or be written to through command/address bus 670; Examiner notes that “data” as written here in the claim language is highly generic and can be interpreted as just information, which would include command/address signals which are used to control RAM, and data to be stored, i.e. both command/address and data are all considered “data” that is transmitted between a memory and memory controller as both parts are information needed for any memory transaction to occur, hence under the currently claim language a first portion of “data” being transmitted across data bus and a second portion of “data” being transmitted through the command address bus can be interpreted as normal operation for a memory transaction as command/address signals and data are being transmitted).
Allowable Subject Matter
Claims 8-10 and 12-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 8, Examiner finds that prior art does not specifically teach the operating method of claim 5, further comprising, after the transmitting of the mode command signal, activating a data input and output mode, and wherein the second portion of the data is transmitted after the data input and output mode is activated.
As to claim 12, Examiner finds that prior art teaches the memory system of claim 11, wherein the memory apparatus includes: a command address buffer configured to generate an internal command address signal from a signal transferred through the command address bus or configured to output the internal command address signal through the command address bus (with arts such as Lee (US 2009/0303802) and Lee (US 2010/0226185), both of which teach a memory controller connected to a CA buffer, which then generates internal CA signals from the combination of outputs from the memory controller and CA buffer).
However, Examiner finds that prior art does not specifically teach a command control circuit configured to generate a first data mode signal and a second data mode signal based on the internal command address signal; and a first data input and output circuit configured to generate based on the first data mode signal, a first memory data signal from the internal command address signal and configured to generate, based on the second data mode signal, the internal command address signal from the first memory data signal.
More specifically, Examiner finds prior arts that teach a mode signal implemented outside of the memory module and directed to the memory controller, and mode selection units in the memory module but selecting mode with input from the memory controller, i.e. not selecting the mode using internal CA signals as claimed.
Response to Arguments
Applicant’s arguments, mailed 3/23/2026, have been fully considered but they are not deemed to be persuasive.
Applicant’s arguments that Coteus ‘106 fails to teach that signals with different information, i.e. data and command address signals, to be transmitted through the same bus, more specifically that Coteus ‘106 discloses that the memory controller receives and sends data to the memory through data bus 660 and tells the memory to read or be written to through the command/address bus 670 but fails to disclose that the data is receive or sent through the command/address bus 670 and the read or write commands are sent through the data bus 660, as applicable to independent claims 1 and 11 (see Pages 10-12) are deemed to be unpersuasive. Examiner points out that “data” as written here in the claim language is generic term and can be interpreted to mean the information being transmitted between the memory controller and memory devices, in which a person of ordinary skill in the art would recognize that two pieces of information are needed, a data portion and a command/address portion, for any read/write operation to memory devices, where Coteus ‘106 in Paragraph 0036 indicates that the “memory controller receives (reads) or sends (writes) data to the memory through data bus 660” and “tells the RAM to read or be written to through command/address bus 670” without specifically indicating which portions are being sent across which buses. Hence under the current claim language “data” is being transmitted through the command address bus as the interpretation of “data” can simply mean that command address data is being transmitted across the command address bus as part of initiating a memory transaction.
Although the current claim amendments attempt to address this by indicating that the memory apparatus is configured to receive command address signals through the command address bus, Examiner finds that this is still insufficient in addressing the fact that “data” can still be interpreted using a generic definition that is inclusive of command/address signals as both a data portion and command/address portion are needed for a read/write operation to occur. Thereby Examiner finds the current amendments to independent claims 1 and 11 to be unpersuasive.
Applicant’s arguments to independent claim 5, where it specifically discloses that “the data as well as the command address signals can be transmitted through the command address bus” (see Pages 12-13) are deemed to be unpersuasive. The specific claim language of claim 5 indicates that the memory controller transmits “one of a data input command signal and a data output command signal to the memory apparatus through a command address bus”; transmitting “a first portion of data … through a data bus”; transmitting “a mode command signal…through the command address bus”; and transmitting “a second portion of data…through the command address bus”. Examiner points out that the claim language in independent claim 5 talks about command signals specifically being sent using the command address bus and portions of data which are transmitted through the data bus and the command address bus, but Examiner specifically points out that “first portion of data” and the “second portion of data” being talked about here still does not differentiate from a generic “data” where the definition of data is inclusive of command/address portions of a read/write operation as both data and command/address data are needed for any read/write operation to occur. As such Examiner finds these arguments to also be unpersuasive.
Overall, Examiner believes that the claim language in Applicant’s amendment are not persuasive enough to separate out that “data” is not a generic recitation where read/write operations need both data and command/addresses, i.e. transmitting “data” meaning that data and command/address data are sent. Although the arguments are arguing the technical feature of the invention being the allowing of signals with different information (data and command address signals) transmitted through the same bus (i.e. command address bus) (see Applicant’s Arguments Page 10), Examiner finds that the current claim language does not accurately represent this facet.
In summary, Coteus ‘106 teaches the claimed invention as set forth above.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2009/0303802) teaches a memory system where memory controller communicates with a memory module, with a mode selection unit and command address buffer in the memory module and the command address buffer output being used to generate internal command address signals for the memory devices on the memory module.
Gans (US 2020/0272567) teaches a stacked memory device with an external memory controller communicating with a memory device comprising local memory controllers and memory arrays and memory dies, where local memory controllers causes memory dies and arrays to communicate using C/A interfaces based on read/write commands data and in response transmit the sets of data via I/O interfaces back to the memory controller.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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