DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Talbot et al. (US 7,135,884).
In regards to claim 1, Talbot discloses of a device, comprising: a voltage driver including: first and second outputs (for example DT, DF), the first output is a positive terminal and the second output is a negative terminal, a difference between signals on the first and second outputs configured to generate a differential voltage swing (see Fig 2); first (for example ZIT) and second (for example ZIF) output resistors directly coupled together in series between the first (DT) and second outputs (DF, see Fig 9 and Column 8 Lines 20-29), the first output resistor (ZIT) having a first resistance and the second output resistor (ZIF) having the first resistance (the common mode connection will have equal resistances for ZIT and ZIF as a well-known principle in the art; also see reference to Nagulapalli, Johnson and Van Brunt below); a first branch having a first resistor and a first switch, the first resistor is coupled to an input voltage by the first switch, the first resistor is coupled to the first output, the first branch having a second resistor and a second switch, the second resistor is coupled to ground by the second switch, the second resistor is coupled to the first output (see Fig 3), the first output (DT, at 18a) is coupled between the first branch and the first output resistor (for example ZIT, see Figs 3, 5 and 9, the output DT at 18a is connected between the first branch equivalent impedance ZOT and ZIT; also there is a resistance load associated as seen within Fig 5); a second branch having a third resistor and a third switch, the third resistor is coupled to ground by the third switch, the third resistor is coupled to the first output (see Fig 3); and a voltage sensor (within 16, see Figs 1, 8) configured to detect the input voltage, and generate a code based on the detected input voltage, resistance values of the first and third resistors configured to be calibrated based on the code to maintain a constant summation of the first and third resistors (for example see Figs 1-3, 5, 8-9, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 20 – Column 10 Line 20).
In regards to claim 2, Talbot discloses of the device of claim 1, wherein the voltage driver further includes: a third branch having a fourth resistor and a fourth switch, the fourth resistor is coupled to the input voltage by the fourth switch, the fourth resistor is coupled to the second output, the third branch having a fifth resistor and a fifth switch, the fifth resistor is coupled to ground by the fifth switch, the fifth resistor is coupled to the second output; and a fourth branch having a sixth resistor and a sixth switch, the sixth resistor is coupled to ground by the sixth switch, the sixth resistor is coupled to the second output, and the fourth and sixth switches are configured to be closed concurrently or opened concurrently (for example see Fig 3, various respective branches, switches, resistors and switching possibilities).
In regards to claim 3, Talbot discloses of the device of claim 2, wherein the second switch has an open state in response to the first and third switches having closed states and the fourth switch having an open state, and the second switch has a closed state in response to the first and third switches having open states and the fourth switch having a closed state (for example see Fig 3, various respective branches, switches, resistors and switching possibilities).
In regards to claim 4, Talbot discloses of the device of claim 1, wherein the voltage driver further includes: a third branch having a fourth resistor and a fourth switch, the fourth resistor is coupled to the input voltage by the fourth switch, the fourth resistor is coupled to the first output, the third branch having a fifth resistor and a fifth switch, the fifth resistor is coupled to ground by the fifth switch, the fifth resistor is coupled to the first output; and a fourth branch having a sixth resistor and a sixth switch, the sixth resistor is coupled to the input voltage by the sixth switch, the sixth resistor is coupled to the first output, the fourth branch having a seventh resistor and a seventh switch, the seventh resistor is coupled to ground by the seventh switch, the seventh resistor is coupled to the first output (for example see Fig 3, various respective branches, switches, resistors and switching possibilities).
In regards to claim 5, Talbot disclose of the device of claim 1, wherein the device is a high-speed point-to-point communications system operating in a physical layer (PHY) protocol (for example see Fig 2, physical connection between transmitter/receiver).
In regards to claim 6, Talbot disclose of the device of claim 5, wherein the first (DT) and second (DF) outputs of the voltage driver are coupled to a receiver load including the first (ZIT) and second (ZIF) output resistors (see Fig 9 and Column 8 Lines 20-29).
In regards to claim 7, Talbot discloses of the device of claim 1, wherein the resistance values of the first and third resistors are calibrated to compensate for the differential voltage swing between the first and second outputs (see Fig 3).
In regards to claim 8, Talbot discloses of the device of claim 1, further comprising: a digital-to-analog converter (120) coupled between the voltage sensor and the voltage driver, the digital-to-analog converter (120) configured to receive the code from the voltage sensor, and transmit an analog signal to the voltage driver corresponding to the code, the analog signal calibrates the resistance values of the first and third resistors (for example see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 9, Talbot discloses of the device of claim 1, further comprising: a logic circuit coupled between the voltage sensor and the voltage driver (see Fig 8), the logic circuit configured to receive the code from the voltage sensor, and transmit a logical code to the voltage driver corresponding to the received code, the logical code calibrates the resistance values of the first and third resistors (for example see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 10, Talbot discloses of the device of claim 1, further comprising: a controller (for example 37, see Fig 2) coupled between the voltage sensor and the voltage driver, the controller (37) configured to receive the code from the voltage sensor, and transmit a logical code to the voltage driver corresponding to the received code, the logical code calibrates the resistance values of the first and third resistors (see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 11, Talbot discloses of a method, comprising: measuring, by a voltage sensor (within 16, see Figs 1, 8), an input voltage of a voltage driver (12), the voltage driver (12) including a first resistance block and a second resistance block (see Fig 3); performing a comparison between the measured input voltage and a threshold voltage (see Figs 1-3, 8); generating, by the voltage sensor, a code based on the comparison; transmitting the code to the voltage driver (see Figs 2-3, 8); generating a differential voltage swing based on a difference between signals in a first and second output (for example DT, DF at 18a-b, see Figs 2-3, 5, 9), the first output (DT at 18a) being coupled between a receiver load (see Fig 5) and the first resistance block (see Fig 3), the receiver load including first (for example ZIT) and second (for example ZIF) output resistors directly coupled together in series between the first and second outputs (DT, DF, see Fig 9 and Column 8 Lines 20-29), the first (ZIT) and second (ZIF) output resistors having a same resistance (the common mode connection will have equal resistances for ZIT and ZIF as a well-known principle in the art; also see reference to Nagulapalli, Johnson and Van Brunt below); and the second output (DF at 18b) being coupled between the receiver load (see Figs 5, 9) and the second resistor block (see Figs 2-3, 5); and altering resistances of the voltage driver based on the code, the altering resistances compensates for the differential voltage swing, wherein an output impedance of the voltage driver remains substantially constant (for example see Figs 1-3, 8-9, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 20 – Column 10 Line 20).
In regards to claim 12, Talbot discloses of the method of claim 11, wherein the altering of the resistances includes: increasing a first resistance and reducing a second resistance (see Fig 3) in response to the measured input voltage being less than the threshold voltage; and reducing the first resistance and increasing the second resistance in response to the measured input voltage being greater than the threshold voltage (see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 13, Talbot disclose of the method of claim 12, wherein the altering of the resistances causes a summation of the first and second resistances (see Fig 3) remaining a substantially constant value (see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 14, Talbot discloses of the method of claim 13, wherein the output impedance of the voltage driver (12) is substantially the same as the constant value, and a load (at 14) is coupled to an output of the voltage driver, impedance of the load being the same as the constant value (see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 15, Talbot discloses of the method of claim 11, comprising: generating a binary code based on the code; transmitting the binary code to a digital-to-analog converter (120, see Fig 8 and Column 8 Line 30 – Column 10 Line 20); and transmitting an analog signal corresponding to the binary code to the voltage driver (12), the analog signal changes the resistances of the voltage driver (see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 16, Talbot discloses of the method of claim 12, wherein the generating of the code includes: generating a binary code; transmitting the binary code to a logic module; transmitting a calibration code corresponding to the binary code to a multiplexer of the voltage driver (see 112 in Fig 8, also see Column 10 Lines 12-20); and coupling a logical voltage level to the first and second resistance blocks (see Figs 2-3, 8), the logical voltage level changes the first and second resistances corresponding to the binary code (see Figs 1-3, 8, Column 4 Line 53 - Column 7 Line 7 and Column 8 Line 30 – Column 10 Line 20).
In regards to claim 17, Talbot discloses of a system, comprising: a receiver (for example 10’) having a load (for example see 14 in Fig 5); a transmitter (for example 10) having serial inputs and differential outputs, the differential outputs include a first output and a second output (for example DT, DF respectively), the load (14 in Fig 5) being coupled to the first and second outputs (see Fig 2), the transmitter including: a voltage driver (12) having first and second resistance blocks (see Fig 3), the first output (DT at 18a) being coupled between the first resistance block and the load (see Figs 2-3, 5), the second output (DF at 18b, see Figs 2-3) being coupled between the second resistance block and the load (see Figs 2-3, 5, 9), the load including a first output resistor (for example ZIT) and a second output resistor (for example ZIF) coupled directly together in series (see Fig 9 and Column 8 Lines 20-29); a voltage sensor (within 16, see Figs 1, 8) configured to detect variations of an input voltage of the voltage driver; and a controller (37) configured to change equivalent resistances of the first and second resistance blocks based on the detected variations, the equivalent resistances remaining substantially the same as the load (for example see Figs 1-3, 5, 8-9 and Column 4 Line 53 - Column 7 Line 7, Column 8 Lines 20-29).
In regards to claim 18, Talbot disclose of the system of claim 17, wherein the system is a high-speed point-to-point communications system operating in a physical layer (PHY) protocol (for example see Fig 2, physical connection between transmitter/receiver).
In regards to claim 19, Talbot discloses of the system of claim 17, wherein the changing equivalent resistances of the first and second resistance blocks causes to compensate for a differential voltage swing between the first and second outputs (see Figs 1-3 and Column 4 Line 53 - Column 7 Line 7).
In regards to claim 20, Talbot discloses of the system of claim 17, wherein the transmitter further includes: a digital-to-analog converter (120, see Fig 8 and Column 8 Line 30 – Column 10 Line 20) configured to receive a binary code from the voltage sensor and transmit an analog signal to the voltage driver, the analog signal causes the change of the first and second resistance blocks (see Figs 1-3, 8).
Response to Arguments
Applicant's arguments filed 3/25/26 have been fully considered but they are not persuasive. The Applicant argues the prior art of Talbot fails to disclose of first and second output resistors connected to each other in series having the same resistance, however, the Examiner respectfully disagrees. The common mode connection of the resistors ZIT and ZIF will have the same resistance as is a known principle in the art, however, for reference purposes only, see listed references to Nagulapalli, Johnson and Van Brunt which more explicitly illustrate common mode connected resistors across the differential outputs having the same resistances such as RT, RL/2 and Rt/2 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nagulapalli (US 2024/0275377) Fig 2
Johnson et al. (US 7,535,258) Fig 2
Van Brunt et al. (US 5,418,478) Fig 4
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2845
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