DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed on February 21st 2026. Claims 1-15 are pending in the case. Claim 1 is the independent claim.
Information Disclosure Statement
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. The information disclosure statement (IDS) submitted on February 21st 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 5, 6, and 10 are objected to because of the following informalities:
In claim 5, "wherein number of references allowed to be simultaneously processed…" should be "wherein a number of references allowed to be simultaneously processed…".
In claim 6, "wherein reference operation is processed…" should be "wherein a reference operation is processed…".
In claim 10, "when frequency of calibration…" should be "when a frequency of calibration…".
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Such claim limitations are:
“the control device includes means that selects…” in claim 11.
“the control device includes means that sets…” in claim 15.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are:
“a calibration control section that calibrates…” in claim 2.
Because this claim limitation is being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-7 and 9-15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, “…a bit width of a control parameter allowed to be stored in each entry of the parameter memory is equal to or larger than….” renders the claim indefinite because it merely states a function (the bit width of a control parameter allowed to be stored) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 4, “…a plurality of adjacent entries in the parameter memory are simultaneously referenced when a bit width of a control parameter allowed to be stored in each entry of the parameter memory is smaller than….” renders the claim indefinite because it merely states a function (a plurality of adjacent entries in the parameter memory are simultaneously referenced) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 5, “…number of references allowed to be simultaneously processed by the parameter memory is equal to or larger than….” renders the claim indefinite because it merely states a function (the number of references allowed to be processed) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 6, “…reference operation is processed in a time-sharing manner when number of references allowed to be simultaneously processed by the parameter memory is smaller….” renders the claim indefinite because it merely states a function (reference operation is processed in a time-sharing manner) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 7, “…at least part of the parameter memory is configured as a read-only area….” renders the claim indefinite because it merely states a function (the parameter memory is configured as a read-only) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 9, “…a calibration support command obtained by selectively acquiring contents of one of output signals from the quantum bit array is supported….” renders the claim indefinite because it merely states a function (selectively acquiring contents of one of output signals) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 10, “…when…the immediate value is employed as the control parameter, and if not, a reference destination in the parameter memory regarding the control parameter is set in the command….” renders the claim indefinite because it merely states a function (setting a control parameter) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 10, the limitation "…and if not, a reference destination…" is unclear. It is unclear what the “if not” is referring to. For examination purposes, this limitation has been interpreted as “…and when a bit width of a control parameter referenced by a command is not equal to or smaller than a bit width defined in the command format of the command, when frequency of calibration demanded for the control parameter is not low to a certain extent, or when calibration of the control parameter is not deterred, a reference destination in the parameter memory regarding the control parameter is set in the command.”
Regarding claim 10, the term “when frequency of calibration demanded for the control parameter is low” is a relative term which renders the claim indefinite. The term “demanded” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what constitutes “a demand” for frequency of calibration, and what performs the demand.
Regarding claim 10, the term “low to a certain extent” is a relative term which renders the claim indefinite. The term “a certain extent” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what value of frequency of calibration demanded for the control parameter would be considered low.
Regarding claim 10, the term “when calibration of the control parameter is deterred” is a relative term which renders the claim indefinite. The term “deterred” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what would cause calibration of the control parameter to be “deterred” and what the deterring entails.
Regarding claim 11, the term “sure to a certain extent” is a relative term which renders the claim indefinite. The terms “sure” and “a certain extent” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what values of the control parameter referenced by the command would make the control device “sure to a certain extent” that they are any of the candidate values.
Regarding claim 11, the term “any of a small number of candidate values” is a relative term which renders the claim indefinite. The term “a small number” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear how many of the candidate values would be considered “a small number”.
Regarding claim 12, “…a control parameter referenced by a command is calculated as a sum of an offset value set in an offset register….” renders the claim indefinite because it merely states a function (a control parameter referenced by a command is calculated as a sum) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 13, “…a bit width of the offset register is equal to or larger than a maximum bit width in all of the control parameters...” renders the claim indefinite because it merely states a function (the bit width of the offset register) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 14, “…a difference in the offset value between before and after calibration is limited to be equal to or smaller than a maximum variation width ….” renders the claim indefinite because it merely states a function (a difference in the offset value between before and after calibration is limited) without providing any indication about how the function is performed. The recited function does not follow from the structure recited in the claim, i.e., the quantum bit array, command memory, and parameter memory, so it is unclear whether the function requires some other structure or is simply a result of operating the control device in a certain manner.
Regarding claim 14, the term “a maximum variation width permitted in one time of calibration” is a relative term which renders the claim indefinite. The term “permitted in one time of calibration” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what width would be considered “a maximum variation”.
Regarding claim 15, it is rejected for being dependent on a rejected base claim without curing any of the deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-12 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Khammassi (US 2021/0182071 A1).
Regarding claim 1:
Khammassi teaches [a] control device that controls quantum operation in a quantum bit array in which a plurality of quantum bits are arranged one-dimensionally or two-dimensionally (Khammassi, ¶27 “Generally, the quantum dot devices 100 disclosed herein may further include a source of magnetic fields (not shown) that may be used to create an energy difference in the states of a quantum dot (e.g., the spin states of an electron spin-based quantum dot) that are normally degenerate, and the states of the quantum dots (e.g., the spin states) may be manipulated by applying electromagnetic energy to the gates lines to create quantum bits capable of computation.” Further, Khammassi ¶29 “Together, the first gate lines 102 and the second gate lines 104 may form a grid, as depicted in FIG. 1.” Here, the grid of qubits can be considered the quantum bits are arranged two-dimensionally. It is noted the claim recites alternative language, and Khammassi teaches at least one of the alternatives.), the control device comprising:
a command memory that stores a plurality of control commands (Khammassi, ¶39 “Quantum and non-quantum instructions 201A-B are fetched from memory 205 at the front end of the instruction pipeline and stored in a Level 1 (L1) instruction cache 201.” Here, the instructions in the instruction cache can be considered the control commands in the command memory); and
a parameter memory that stores part or all of control parameters accompanying the control commands (Khammassi, ¶67 “For example, some values may be encoded directly within the instruction 600 (e.g., as immediate values) while other values may be specified via opcodes which map to registers or memory locations where the actual input values are stored (e.g., having been calculated by prior instructions and/or loaded from memory).” Here the registers or memory locations where the actual input values are stored can be considered the parameter memory. Further, Khammassi ¶66 “As described herein, a quantum instruction may include fields/opcodes to specify one or more of: a frequency 740, a phase shift value 741, an amplitude value 742, an arbitrary wave generator codeword 743, and an envelope codeword 744.” Here the fields for frequency, phase, amplitude etc. can be considered the control parameters), wherein
a command format of the control commands includes one or more parameter specifying fields to specify either an immediate value of a control parameter or reference to the control parameter stored in the parameter memory (Khammassi, ¶67 “For example, some values may be encoded directly within the instruction 600 (e.g., as immediate values) while other values may be specified via opcodes which map to registers or memory locations where the actual input values are stored (e.g., having been calculated by prior instructions and/or loaded from memory).” Here, the opcodes which map to registers or memory location can be considered reference to the control parameter stored in the parameter memory. It is noted the claim recites alternative language, and Khammassi teaches at least one of the alternatives.).
Regarding claim 2:
Khammassi teaches [t]he control device according to claim 1, further comprising:
a calibration control section that calibrates the control parameter on a basis of output signals from the quantum bit array (Khammassi, ¶77 “To address these problems, one embodiment of the invention comprises a qubit measurement unit capable of auto-calibration. When in calibration mode, the measurement unit digitizes readout signals with known measurement outcomes (e.g., ground state and excited state) and unknown outcomes (e.g., random measurements covering both ground and exited states with equal probabilities due to qubit state superposition) and performs the required signal processing and statistical sampling to determine the threshold automatically. Once determined, it configures the threshold in the measurement discrimination unit.”).
Regarding claim 5:
Khammassi teaches [t]he control device according to claim 1, wherein
number of references allowed to be simultaneously processed by the parameter memory is equal to or larger than a maximum number of number of control parameters that each command supported by the control device has (Khammassi, ¶65-66 “FIG. 7 illustrates an embodiment with three independently operable quantum cores 790A-C which perform quantum operations using the techniques described herein. In operation, quantum instructions 700 from multiple threads are decoded and (potentially partially) executed by quantum decode and execution functional units 202A, 204E. The resulting quantum microoperations are dispatched to the various cores 790A-C by dispatch/timing control circuitry 706. In one embodiment, the dispatch/timing control circuitry 706 distributes the quantum uops 720A-C to the different cores 790A-C based on uop data and/or resource dependencies. For example, to maximize parallelization, the dispatch/timing control circuitry 706 may maintain a first quantum operation on the same core as a second quantum operation which is dependent on the results of the first quantum operation. In contrast, quantum operations which are not dependent may be distributed to different cores, to allow for parallel execution.
In one embodiment, each core 790A-C includes a queue of dispatched quantum uops 720A-C. A parallel processing interface 730A-C may process at least some of these quantum operations in parallel based on the opcode and data fields of each quantum instruction 600.”).
Regarding claim 6:
Khammassi teaches [t]he control device according to claim 1, wherein
reference operation is processed in a time-sharing manner when number of references allowed to be simultaneously processed by the parameter memory is smaller than a maximum number of number of control parameters that each command supported by the control device has (Khammassi, ¶66 “A parallel processing interface 730A-C may process at least some of these quantum operations in parallel based on the opcode and data fields of each quantum instruction 600.”).
Regarding claim 7:
Khammassi teaches [t]he control device according to claim 1, wherein
at least part of the parameter memory is configured as a read-only area (Khammassi, ¶139 “Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals—such as carrier waves, infrared signals, digital signals, etc.).”).
Regarding claim 8:
Khammassi teaches [t]he control device according to claim 1, wherein
output signals from the quantum bit array include part of a signal to control the quantum bit array (Khammassi, ¶55 “In certain quantum circuits requiring fast feedback control such as error correction circuits and active qubit reset (pairs of measurements and binary-controlled pauli-X gate to reset the qubit to the ground state), slow feedback due to high latency results in inefficient control.” Here, a feedback control can be considered to involve signals to control the quantum bit array).
Regarding claim 9:
Khammassi teaches [t]he control device according to claim 1, wherein
a calibration support command obtained by selectively acquiring contents of one of output signals from the quantum bit array is supported (Khammassi, ¶77 “In particular, the MU 1100 may enter into an auto-calibration mode periodically and/or in response to a command.” Further, Khammassi, ¶75, “
RDO CH, MR, T, COND
Readout Qubit on channel
Channel, Measurement
CH for a duration T, and
Register ID, Duration,
save measurement
Condition, On/Off
outcome to register MR if
COND == 1.
” here, RDO can be considered a calibration support command and the CH field selects contents of one of output signals).
Regarding claim 10:
Khammassi teaches [t]he control device according to claim 1, wherein
when a bit width of a control parameter referenced by a command is equal to or smaller than a bit width defined in the command format of the command, when frequency of calibration demanded for the control parameter is low to a certain extent, or when calibration of the control parameter is deterred, the immediate value is employed as the control parameter, and if not, a reference destination in the parameter memory regarding the control parameter is set in the command (Khammassi, ¶67 “For example, some values may be encoded directly within the instruction 600 (e.g., as immediate values) while other values may be specified via opcodes which map to registers or memory locations where the actual input values are stored (e.g., having been calculated by prior instructions and/or loaded from memory).” It is noted the claim recites alternative language, and Khammassi teaches at least one of the alternatives.).
Regarding claim 11:
Khammassi teaches [t]he control device according to claim 1, wherein
the control device includes means that selects any of a small number of candidate values on a basis of the immediate value set in a command before execution of the command when it is sure to a certain extent that a control parameter referenced by the command is any of the candidate values (Khammassi, ¶69 “One or both the AWG codeword 743 and envelope codeword 744 may be used to specify the shape of the envelope to be applied.” Further, Khammassi, ¶66 “As described herein, a quantum instruction may include fields/opcodes to specify one or more of: a frequency 740, a phase shift value 741, an amplitude value 742, an arbitrary wave generator codeword 743, and an envelope codeword 744.” Here, the codewords selecting a shape for an envelope can be considered the means that selects any of a small number of candidate values on a basis of the immediate value set in a command).
Regarding claim 12:
Khammassi teaches [t]he control device according to claim 1, wherein
a control parameter referenced by a command is calculated as a sum of an offset value set in an offset register and a parameter difference value with respect to the offset value, the parameter difference value being set in a difference parameter memory (Khammassi, ¶88 “The input of the pulse generator is composed of the starting value of the parameter, the increment step and the number of steps.” Here the increment step can be considered a parameter difference value).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. § 103 as being unpatentable over Khammassi in further view of Ciacci (US 4,872,138 A).
Regarding claim 3:
Khammassi teaches [t]he control device according to claim 1,
Khammassi does not teach "wherein a bit width of a control parameter allowed to be stored in each entry of the parameter memory is equal to or larger than a maximum bit width in all of the control parameters referenced from each command supported by the control device"
However, Ciacci teaches wherein a bit width of a control parameter allowed to be stored in each entry of the parameter memory is equal to or larger than a maximum bit width in all of the control parameters referenced from each command supported by the control device (Ciacci, col 4, lines 42-63 “Memory 7 is organized in 4 byte blocks, each addressed by the most significant address bits, with the exclusion of the least significant address bits, A0, A1. Each memory access operation may therefore refer to a word operand, identified by an address A2-31 and located in memory block MB1 or MB2 depending on the state of bit A1, or to a double word operand, which must be aligned with the memory structure and therefore is identified by an address where bit A1 is equal to 0….For sake of simplicity it is assumed that the operand length is defined by a single signal DW, which at level 0 indicates a single word operand and at level indicates a double word operand.”).
Khammassi and Ciacci are analogous art because both references concern methods for memories for data processing systems. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Khammassi ’s flexible qubit control with low memory overhead system to incorporate the bit width taught by Ciacci. The motivation for doing so would have been a better utilization of the information stored as stated in Ciacci, col 1, lines 61-67 “The structure of such caches is complex and expensive, in that they require logical control circuits which supervise the updating of the cache contents when required, both for a better utilization of the information stored therein, and also to assume that the information stored in cache is the same information that is stored in working memory.”
Claim 4 is rejected under 35 U.S.C. § 103 as being unpatentable over Khammassi in further view of Perets et al. (US 6,407,961 B1) (hereinafter “Perets”).
Regarding claim 4:
Khammassi teaches [t]he control device according to claim 1,
Khammassi does not teach "wherein a plurality of adjacent entries in the parameter memory are simultaneously referenced when a bit width of a control parameter allowed to be stored in each entry of the parameter memory is smaller than a maximum bit width in all of the control parameters referenced from each command supported by the control device"
However, Perets teaches wherein a plurality of adjacent entries in the parameter memory are simultaneously referenced when a bit width of a control parameter allowed to be stored in each entry of the parameter memory is smaller than a maximum bit width in all of the control parameters referenced from each command supported by the control device (Perets, col 2, lines 27-43 “It is an object of the present invention to provide a memory array which enables any two consecutive words to be read in a single read operation.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a memory array which includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found.” The adjacent entries pulled in one operation can be considered the adjacent entries in the parameter memory are simultaneously referenced when a bit width of a control parameter…is smaller than a maximum bit width).
Khammassi and perets are analogous art because both references concern methods for memories for data processing systems. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Khammassi ’s flexible qubit control with low memory overhead system to incorporate the reference of multiple parameters in one read taught by Perets. The motivation for doing so would have been to enable any two consecutive words to be read in a single read operation as stated in Perets, col 2, lines 27-28 “It is an object of the present invention to provide a memory array which enables any two consecutive words to be read in a single read operation.”
Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Khammassi in view of Shin et al. (US 8,362,935 B2) (hereinafter “Shin”) in further view of Mayes et al. (US 5,218,362 A) (hereinafter “Mayes”).
Regarding claim 13:
Khammassi teaches [t]he control device according to claim 12,
Khammassi does not teach "wherein a bit width of the offset register is equal to or larger than a maximum bit width in all of the control parameters referenced from each command supported by the control device"
However, Shin teaches wherein a bit width of the offset register is equal to or larger than a maximum bit width in all of the control parameters referenced from each command supported by the control device (Shin, col 5-6, lines 66-15 “Therefore, if the reference voltage adjusting value AdjVal is divided by the coarse TRIM value CoarseTRIMStep preset thus, the primary coarse TRIM adjusting value CoarseTRIMAdjStep will be 10/5=2 (12S).
Then, the primary coarse TRIM adjusting value CoarseTRIMAdjStep is rounded off to trim a value below a decimal point to produce the coarse TRIM value CoarseTRIMStep of “2”. Then, by subtracting the value CoarseTRIM*CoarseTRIMStep 5*2 obtained by multiplying the coarse TRIM value CoarseTRIM produced thus to the coarse TRIM value CoarseTRIMStep from the reference voltage adjusting value AdjVal “10 mV”, the fine TRIM value FineTRIMStep of “0” is produced (13S).
The code value which is the coarse TRIM value and the fine TRIM value produced by above method is stored at a designated address of the internal memory 2 of the internal chip 1.”), and
Khammassi and Shin are analogous art because both references concern methods for memories for data processing systems. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Khammassi ’s flexible qubit control with low memory overhead system to incorporate the bit width taught by Shin. The motivation for doing so would have been, as stated in Shin, col 6, lines 43-57 “As has been described, the device and method for controlling a reference voltage of a digital-to-analog converter have the following advantages.
Since the device and method for controlling a reference voltage of a digital-to-analog converter of the present invention measures the voltage from the digital-to-analog converter to each of channels to provide the minimum value and the maximum value, estimates the reference voltage adjusting value which can minimize variation among the channels with reference to the reference voltage based on the minimum value and the maximum value, generating two code values of the coarse TRIM value which corrects the reference voltage in a great scale and the fine TRIM value which corrects the reference voltage in a small scale based on the reference voltage adjusting value estimated thus, and controls the reference voltage, the variation of the output voltage can be minimized.”
Khammassi in view of Shin does not teach "a bit width of a parameter difference value stored in each entry of the difference parameter memory is smaller than a bit width of a control parameter stored in each entry of the parameter memory"
However, Mayes teaches a bit width of a parameter difference value stored in each entry of the difference parameter memory is smaller than a bit width of a control parameter stored in each entry of the parameter memory (Mayes, col 10, lines 64-67 “To accomplish this, DAC-F is set equal to the integer portion of -4·Error, but if the fractional part of -4·Error is greater than 0.5, then DAC-F is rounded up to the next largest value.”).
Khammassi in view of Shin and Mayes are analogous art because both references concern methods for memories for data processing systems. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Khammassi /Shin’s flexible qubit control with low memory overhead system to incorporate the bit width taught by Mayes. The motivation for doing so would have been correcting for any non-uniformities in the resistances of the resistor ladder, as stated in Mayes, abstract “In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC's embedded memory, corresponding to the estimated conversion value from the first conversion cycle, thereby correcting for any non-uniformities in the resistances of the resistor ladder.”
Claims 14-15 are rejected under 35 U.S.C. § 103 as being unpatentable over Khammassi in further view of Jang (US 2022/0140818 A1).
Regarding claim 14:
Khammassi teaches [t]he control device according to claim 12,
Khammassi does not teach "wherein a difference in the offset value between before and after calibration is limited to be equal to or smaller than a maximum variation width permitted in one time of calibration in calibration control of the control parameter"
However, Jang teaches wherein a difference in the offset value between before and after calibration is limited to be equal to or smaller than a maximum variation width permitted in one time of calibration in calibration control of the control parameter (Jang, ¶81 “On the contrary, when any of the fine codes FI<0:2> and FR<0:2> reaches again the maximum count value in a state that the output signal OUT has a voltage level out of the target range (“YES” at S860), the offset control circuit 125 may reset again the fine codes FI<0:2> and FR<0:2>, and may adjust again the coarse codes CI<0:2> and CR<0:2>, according to the first and second judge signals COMP_OUT1 and COMP_OUT2 (at S870).”).
Khammassi and Jang are analogous art because both references concern methods for control devices. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Khammassi ’s flexible qubit control with low memory overhead system to incorporate the difference offset taught by Jang. The motivation for doing so would have been to prevent deterioration of characteristics of the differential input circuit and allow a normal operation as stated in Jang, ¶83 “the semiconductor memory device may prevent deterioration of characteristics of the differential input circuit and allow a normal operation thereof.”
Regarding claim 15:
Khammassi teaches [t]he control device according to claim 12,
Khammassi does not teach "wherein the control device includes means that sets a policy for executing calibration in such a manner that a difference in a control parameter value between before and after the calibration is divided into a calibration amount for the offset value and a calibration amount for the parameter difference value in calibration control of the control parameter"
However, Jang teaches wherein the control device includes means that sets a policy for executing calibration in such a manner that a difference in a control parameter value between before and after the calibration is divided into a calibration amount for the offset value and a calibration amount for the parameter difference value in calibration control of the control parameter (Jang, ¶81 “On the contrary, when any of the fine codes FI<0:2> and FR<0:2> reaches again the maximum count value in a state that the output signal OUT has a voltage level out of the target range (“YES” at S860), the offset control circuit 125 may reset again the fine codes FI<0:2> and FR<0:2>, and may adjust again the coarse codes CI<0:2> and CR<0:2>, according to the first and second judge signals COMP_OUT1 and COMP_OUT2 (at S870).”).
Khammassi and Jang are analogous art because both references concern methods for control devices. Accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Khammassi ’s flexible qubit control with low memory overhead system to incorporate the difference offset taught by Jang. The motivation for doing so would have been to prevent deterioration of characteristics of the differential input circuit and allow a normal operation as stated in Jang, ¶83 “the semiconductor memory device may prevent deterioration of characteristics of the differential input circuit and allow a normal operation thereof.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xu et al. ("QubiC: An open source FPGA-based control and measurement system for superconducting quantum information processors", Xu et al., 27 Oct 2021) discloses a modular FPGA (field programmable gate array) based system called QubiC to control and measure a superconducting quantum processing unit. The system includes room temperature electronics hardware, FPGA gateware, and engineering software.
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/J.S.M./Examiner, Art Unit 2122
/MICHAEL H HOANG/PRIMARY EXAMINER, Art Unit 2122
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