DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hayashi (US 20240036419).
Regarding claim 1: Hayashi teaches an array substrate (Fig. 1 and paragraph [0033] teaches an array substrate 10), comprising: a display region comprising a plurality of pixel regions; and a substrate, pixel driving circuits, and scanning signal lines, wherein at least part of a pixel driving circuit among the pixel driving circuits and at least part of a scanning signal line among the scanning signal lines are located in the display region and on a same side of the substrate, and the scanning signal line extends in a first direction; wherein at least part of the pixel driving circuit is located in a pixel region among the plurality of pixel regions and comprises thin-film transistors (Figs. 1-2, 14, 16-17 and paragraph [0033-0036, 0044-0046] teach a display region AA comprising a plurality of pixel regions Pix; a substrate 10, pixel driving circuits of pixels Pix including thin-film transistors and scanning signal lines GL extends in a first direction as claimed), a thin-film transistor among the thin-film transistors comprises a gate and a channel layer, and the gate is a portion where the scanning signal line overlaps the channel layer transistors (Figs. 1-2, 14, 16-17 and paragraph [0033-0036, 0044-0046, 0124-0126, 0134-0147] teach a thin-film transistor Tr among a plurality of transistors comprises a gate GE and a channel layer SC, and the gate is a portion where the scanning line GL overlaps the channel layer SC as shown in Fig. 14); and wherein the array substrate further comprises auxiliary signal lines, an auxiliary signal line among the auxiliary signal lines is located in the display region and extends in the first direction, a resistance of the auxiliary signal line is smaller than a resistance of the scanning signal line, the auxiliary signal line and the scanning signal line are disposed in different layers, and the auxiliary signal line is electrically connected to the scanning signal line through a line exchanging through hole (Figs. 1-2, 14, 16-18 and paragraph [0033-0036, 0044-0046, 0148-0157] teach auxiliary signal lines GLs located in the display region and extends in the first direction same as scanning line GL, a resistance of the auxiliary signal line GLs is smaller than a resistance of the scanning signal line GL, the auxiliary signal line GLs and the scanning signal line GL are disposed in different layers, and the auxiliary signal line GLs is electrically connected to the scanning signal line GL through a line exchanging through hole such as CH13).
Regarding claim 2: Hayashi teaches wherein a layer where the auxiliary signal line is located is disposed on one side of a layer where the scanning signal line is located facing away from the substrate; wherein the thin-film transistor comprises a source and a drain; and the auxiliary signal line, the source, and the drain are disposed in a same layer (Figs. 14, 17-18 and paragraph [0124, 0145-0154] teach the auxiliary signal line GLs is located in same layer as signal lines SL is located is disposed on one side of a layer where the scanning signal line is located facing away from the substrate 10; the transistor Tr comprises a source SE and a drain DE; and the auxiliary signal line GLs, the source SE, and the drain DE are disposed in a same layer as signal lines SL).
Regarding claim 4: Hayashi teaches wherein in a direction perpendicular to the substrate, the scanning signal line overlaps the auxiliary signal line in a region other than a region where the line exchanging through hole is located (Fig. 17 and paragraph [0148-0157] teach the scanning lines GL, the auxiliary signal line GLs, and exchanging through hole CH# as claimed).
Regarding claim 16: Hayashi teaches wherein the plurality of pixel regions comprise a first pixel region and a second pixel region that are disposed adjacent to each other in the first direction, and a junction line is formed between the first pixel region and the second pixel region; and a portion of the auxiliary signal line in the first pixel region is axially symmetric with a portion of the auxiliary signal line in the second pixel region about the junction line; wherein a pixel driving circuit located in the first pixel region is a first pixel driving circuit, and a pixel driving circuit located in the second pixel region is a second pixel driving circuit; and at least a portion of the first pixel driving circuit is axially symmetric with the second pixel driving circuit about the junction line (Figs. 16-20 and paragraph [0134-0154, 0160-0165] teach wherein the plurality of pixel regions comprising a first pixel Pix-1 and a second pixel region adjacent in the first direction or horizontal direction, and a junction line formed between the both pixel regions separating the two pixels in same row as shown in Fig. 16 or 20; the auxiliary signal line GLs and a pixel driving circuit Tr located as claimed).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 20240036419).
Regarding claim 3: Hayashi does not explicitly disclose wherein in the first direction, a length of the scanning signal line is smaller than a length of the auxiliary signal line.
However, Hayashi in Figs. 14, 17-18 and paragraph [0124, 0145-0154] teach a length of the auxiliary signal line GLs is smaller than a length of the scanning signal line GL in the first direction. It would have been obvious matter of design choice to modify Hayashi’s invention by designing the scanning signal line GL as the auxiliary signal lines GLs, and interchanging placement of both will result in same functions and will result in a length of the scanning signal line is smaller than a length of the auxiliary signal line. Further since such a configuration, absent any criticality (i.e., unobvious and/or unexpected result(s), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable configuration, where the general conditions of a claim are disclosed in the prior art, involves only routine skill in the art. Moreover, in the absence of any criticality (i.e., unobvious and/or unexpected result(s)), the configuration set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Claims 15, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi (US 20240036419) in the view of Deng (US 20240251622).
Regarding claim 15: Hayashi teaches the array substrate further comprises a light-shielding line; the light-shielding line is disposed between the substrate and the transistor; and in a second direction, the second direction intersects the first direction; and in a direction perpendicular to the substrate, the light-shielding line overlaps the line exchanging through hole (Figs. 11, 18, and paragraph [0089-0090, 0113-0114, 0155, 0175] teach a light-shielding line LS disposed as claimed).
Hayashi does not explicitly disclose wherein the thin-film transistors comprise a drive transistor used for supplying a drive current to a light-emitting element.
However, Deng teaches wherein the thin-film transistors comprise a drive transistor used for supplying a drive current to a light-emitting element (Fig. 3 and paragraph [0106-0109] teach the thin-film transistors comprise a drive transistor T3 used for supplying a drive current to a light-emitting element OLED). It would have been obvious for a person skilled in the art to modify Hayashi’s invention by including Deng’s pixel circuit, because utilizing OLED pixel circuit as defined by Deng is very well-known and widely used in the art to achieve better picture quality, similar pixel circuit can be utilized in Hayashi’s invention. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 17: Combination of Hayashi and Deng teach wherein the pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate, and the first plate is disposed between the second plate and the substrate (Deng in Figs. 3, 5-6 and paragraph [0115-0117, 0129, 0136-0141] teach a storage capacitor C comprising a first plate C1 and a second place C2 disposed on substrate SU as claimed); the array substrate further comprises a semiconductor wire, a connection through hole, and a connection line; at least part of the semiconductor wire extends in a second direction, the channel layer is a portion where the semiconductor wire overlaps the gate, and the channel layer comprises an oxide semiconductor material; and the semiconductor wire is electrically connected to the connection line through the connection through hole, and the connection line is disposed in a same layer as the first plate (Figs. 5-8 and paragraph [0112-0114, 0132-0149] teach a semiconductor wire SE1, through hole, connecting line as claimed). See claim 15 rejection for combination reasoning of Hayashi and Deng, same rationale applies here.
Regarding claim 19: Hayashi teaches a display panel (Fig. 1 teach a display panel 2), comprising an array substrate (Fig. 1 and paragraph [0033] teaches an array substrate 10); wherein the array substrate comprises: a display region comprising a plurality of pixel regions; and a substrate, pixel driving circuits, and scanning signal lines, wherein at least part of a pixel driving circuit among the pixel driving circuits and at least part of a scanning signal line among the scanning signal lines are located in the display region and on a same side of the substrate, and the scanning signal line extends in a first direction; wherein at least part of the pixel driving circuit is located in a pixel region among the plurality of pixel regions and comprises thin-film transistors (Figs. 1-2, 14, 16-17 and paragraph [0033-0036, 0044-0046] teach a display region AA comprising a plurality of pixel regions Pix; a substrate 10, pixel driving circuits of pixels Pix including thin-film transistors and scanning signal lines GL extends in a first direction as claimed), a thin-film transistor among the thin-film transistors comprises a gate and a channel layer, and the gate is a portion where the scanning signal line overlaps the channel layer (Figs. 1-2, 14, 16-17 and paragraph [0033-0036, 0044-0046, 0124-0126, 0134-0147] teach a thin-film transistor Tr among a plurality of transistors comprises a gate GE and a channel layer SC, and the gate is a portion where the scanning line GL overlaps the channel layer SC as shown in Fig. 14); wherein the array substrate further comprises auxiliary signal lines, an auxiliary signal line among the auxiliary signal lines is located in the display region and extends in the first direction, a resistance of the auxiliary signal line is smaller than a resistance of the scanning signal line, the auxiliary signal line and the scanning signal line are disposed in different layers, and the auxiliary signal line is electrically connected to the scanning signal line through a line exchanging through hole (Figs. 1-2, 14, 16-18 and paragraph [0033-0036, 0044-0046, 0148-0157] teach auxiliary signal lines GLs located in the display region and extends in the first direction same as scanning line GL, a resistance of the auxiliary signal line GLs is smaller than a resistance of the scanning signal line GL, the auxiliary signal line GLs and the scanning signal line GL are disposed in different layers, and the auxiliary signal line GLs is electrically connected to the scanning signal line GL through a line exchanging through hole such as CH13).
Hayashi does not explicitly disclose a plurality of light-emitting elements and a light-emitting element among the plurality of light-emitting elements is electrically connected to a pixel driving circuit and is configured to be driven by the pixel driving circuit to emit light.
However, Deng teaches a plurality of light-emitting elements and a light-emitting element among the plurality of light-emitting elements is electrically connected to a pixel driving circuit and is configured to be driven by the pixel driving circuit to emit light (Fig. 3 and paragraph [0106-0109] teach the thin-film transistors comprise a drive transistor T3 used for supplying a drive current to a light-emitting element OLED, and a plurality of pixels and each comprising driving transistor and OLED). It would have been obvious for a person skilled in the art to modify Hayashi’s invention by including Deng’s pixel circuit, because utilizing OLED pixel circuit as defined by Deng is very well-known and widely used in the art to achieve better picture quality, similar pixel circuit can be utilized in Hayashi’s invention. The rationale would have been to use a known method or technique to achieve predictable results.
Regarding claim 20: Combination of Hayashi and Deng teach a display apparatus, comprising the display panel according to claim 19 (Fig. 1 teach a display panel apparatus 2 and see claim 19 rejection).
Allowable Subject Matter
Claims 5-14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/AMIT CHATLY/Primary Examiner, Art Unit 2624
