Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 line 4 discloses “a third thin-oxide M”. It is unclear if this is the same “a third thin oxide M” in line 3 or a new “a third thing-oxide M”.
Claim 15 line 4 discloses “a third thin-oxide M”. It is unclear if this is the same “a third thin oxide M” in line 3 or a new “a third thing-oxide M”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. (20230308101) in view of Shetty (US 10911047).
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With respect to claim 1, Sung et al. (US 20230308101) discloses an apparatus, comprising: an input node (at SIN) to receive a signal (SIN) at a pre-defined voltage; an output node (at VO) ; and a plurality of Metal Oxide-Semiconductor Field Effect Transistors (MOSFETs) (P5-P8 and N1-N2) coupled to the input node and to the output node, the plurality of thin-oxide MOSFETs configured to form a regenerative feedback loop to reduce the signal at the pre-defined voltage to a lower level voltage (switching from high to low level shown in figure 3A), wherein the signal at the lower level voltage is outputted through the output node (VO) wherein the plurality of thin-oxide MOSFETs (Ms) comprises a first input thin-oxide M (i.e. N1), and wherein a drain of the first input thin-oxide M is coupled to the input node (here each of the MoSFETs have a drain coupled to the SIN input (i.e N1 drain is coupled through N1 and 112, P5-P8 are also coupled through intervening circuits ) but fails to disclose the MOSFETS are thin gate.
Shetty (US 10911047) teaches the use of both thick and thin gate MOSFETs, (thin gate for pull down transistors) in level shifting devices as to increase device reliability due to overvoltage stresses of the transistor voltage may be reduced (col. 3 lines 30-40).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use thin gate MOSFETs teaching in Shetty in the structure of Sung for the purpose of improving the input operating voltage range. (Note: coupled is merely defined refers to the connection between circuits or components that allows for energy transfer or signal interaction. This allows for intervening circuits. For direct coupling the circuits are considered directly coupled if there is no intervening circuit. )
With respect to claim 2, the combination above produces the apparatus of claim 1, wherein the plurality of thin-oxide Ms (P1-P8 and N1-N4)to create the regenerative feedback loop comprises a second thin-oxide M that turns partially on (N2) coupled to a third (P5-P8 )thin-oxide M that turns partially off (i.e. P6) that causes a third thin-oxide M (i.e. P5) to charge a node (O1) to turn on the output node (VO) to output the signal at the lower level voltage. (Note: it is unclear if a third is the same as the other a third. See 112 rejection.)
With respect to claim 3, the combination above produces the apparatus of claim 2, wherein the output node comprises a voltage output inverter (144).
With respect to claim 4, the combination above produces the apparatus of claim 2, wherein the pre-defined voltage is approximately 1.2. Shetty teaches VDDL may range between 0.4 V to 1.5 V V for the thin oxide devices ( col 5 lines 27-29).
With respect to claim 5, the combination above produces the apparatus of claim 2, wherein the lower-level voltage is approximately .7v. Shetty teaches VDDL may range between 0.4 V to 1.5 V V for the thin oxide devices ( col 5 lines 27-29).
With respect to claim 6, the combination above produces the apparatus of claim 2, (120) first thin-oxide M (i.e. N1) and the fourth thin-oxide M (i.e. PP7), wherein, when the signal at the input node cycles back to 0 Volts (Switching from high level to low level), a push-pull current is applied to the node (O1) by the pair of thin-oxide Ms, such that the node returns back to 0 Volts and the output node (at VO) returns to 0 Volts.
With respect to claim 8, the combination above produces apparatus the of claim 1, wherein the first input thin-oxide M (N2) is further coupled to a nmos_bias portion set to the pre-defined voltage (VDDL).
With respect to claim 9, the combination above produces the apparatus of claim 8, wherein, when the input node receives the signal at 0 V (see [0023] “example, when the input signal SIN is in a logic value 0, the level of the signal S1 is the high supply voltage VDDL, and the level of the signal S2 is the low supply voltage VSSL.”), the first input thin-oxide M is passed through to the output node (VO) such that voltage output is 0 V.
With respect to claim 10, the combination above produces the apparatus of claim 9, wherein, when the input node receives the signal at the pre-defined voltage (0 or 1), the nmos bias portion coupled to a gate of the first input thin-oxide M (N2), controls a rate of the charging of the node.
With respect to claim 11, the combination above produces the apparatus 10, wherein, when the pre-defined voltage collapses to 0 V (Sin 0), the nmos_bias portion reduces to 0 V , such that the first input thin-oxide M prevents a static leakage path to the input node.
With respect to claim 12, the combination above produces the apparatus of claim 11, further comprising an output voltage collapse detector (comparator 120).
With respect to claim 13, the combination above produces the apparatus of claim 12, wherein, if the output voltage collapse detector (120) receives a collapse detected signal, another thin-oxide M of the plurality of thin-oxide Ms is turned on such that any static leakage path to the output node is cut-off (via P6 and P7).
With respect to claim 14, Sung et al. (US 20230308101) produces a method, comprising: receiving a signal (SIN) at a pre-defined voltage at an input node (at SIN); and operating a plurality of Metal Oxide-Semiconductor Field Effect Transistors (MOSFETs) (P5-P8 and N1-N2) coupled to the input node and to an output node (VO) to create a lower level voltage signal outputted through the output node, wherein, the plurality of thin-oxide MOSFETs are configured to form a regenerative feedback loop to reduce the signal at the pre-defined voltage to a lower level voltage(switching from high to low level shown in figure 3A), wherein the signal at the lower level voltage is outputted through the output node (VO), wherein the plurality of thin-oxide MOSFETs (Ms) comprises a first input thin-oxide M (i.e. N1), and wherein a drain of the first input thin-oxide M is coupled to the input node.(Note: via intervening circuits) but fails to disclose the MOSFETS are thin gate.
Shetty (US 10911047) teaches the use of both thick and thin gate MOSFETs, (thin gate for pull down transistors) in level shifting devices as to increase device reliability due to overvoltage stresses of the transistor voltage may be reduced. (col. 3 lines 30-40).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use thin gate MOSFETs teaching in Shetty in the structure of Sung for the purpose of improving the input operating voltage range.
With respect to claim 15, the combination above produces the method of claim 14, wherein the plurality of thin-oxide MOSFETs (Ms) (P1-P8 and N1-N4)to create the regenerative feedback loop comprises a second thin-oxide M that turns partially on (N2) coupled to a third thin-oxide M that turns partially off (P6) that causes a third thin-oxide M (P5) to charge a node (O1) to turn on the output node (VO) to output the signal at the lower level voltage
With respect to claim 16, the combination above produces the method of claim 15, wherein the output node comprises a voltage output inverter (144).
With respect to claim 17, the combination above produces the method of claim 15, wherein the pre-defined voltage is approximately 1.2 V. Shetty teaches VDDL may range between 0.4 V to 1.5 V V for the thin oxide devices ( col 5 lines 27-29).
With respect to claim 18, the combination above produces the method of claim 15, wherein the lower level voltage is approximately 0.7 V. Shetty teaches VDDL may range between 0.4 V to 1.5 V V for the thin oxide devices ( col 5 lines 27-29).
With respect to claim 19, Sung et al. (US 20230308101) discloses an apparatus, comprising: means for receiving a signal at a pre-defined voltage at an input node (at SIN); and means for configuring a plurality of Metal Oxide-Semiconductor Field Effect Transistors (MOSFETs) (P5-P8 and N1-N2) coupled to the input node and an output node to form a regenerative feedback loop to reduce the signal at the pre-defined voltage to a lower level voltage(switching from high to low level shown in figure 3A),, wherein the signal at the lower level voltage is outputted through the output node (VO), wherein the plurality of thin-oxide MOSFETs (MS) comprises a first input thin-oxide M, (i.e. N1) and wherein a drain of the first input thin-oxide M is coupled to the input node. but fails to disclose the MOSFETS are thin gate.
Shetty (US 10911047) teaches the use of both thick and thin gate MOSFETs, (thin gate for pull down transistors) in level shifting devices as to increase device reliability due to overvoltage stresses of the transistor voltage may be reduced. (col. 3 lines 30-40).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use thin gate MOSFETs teaching in Shetty in the structure of Sung for the purpose of improving the input operating voltage range.
With respect to claim 20, the combination above produces the apparatus of claim 19, further comprising means for providing an output voltage collapse detector (120), wherein, if the output voltage collapse detector receives a collapse detected signal, another thin-oxide M of the plurality of thin-oxide Msi is turned on such that any static leakage path to the output node is cut-off (via P6 and P7).
Response to Arguments
Applicant's arguments filed 12/9/2025 have been fully considered but they are not persuasive.
With respect to Applicant’s argument the cited references do not teach “wherein the plurality of thin-oxide MOSFETs (Ms) comprises a first input thin- oxide M, and wherein a drain of the first input thin-oxide M is coupled to the input node, the Examiner disagrees. Here, for example N1 drain at drain of P4 is coupled to the input node at Sin via N1 and 112) (N2 drain would also be coupled via N2, 114 and 112).
With respect to claims 2-6, 8-13, 15-18 and 20, because Applicant leaves coupled to include intervening circuits, the previous cited art is applicable to the claim language.
With respect to claim 10, Applicant argues the claim fails to disclose the nmos_bias portion coupled to a gate of the first input thin-oxide M controls a rate of the charging of the node. Here, again, because coupled can be interpreted having intervening elements, the cited prior art combination again reads on the claim language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849
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