DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ziaja et al., (PCT Patent Publn No. WO 2023/283073 A1, cited in IDS), hereinafter Ziaja in view of Bergeson et al., (U.S. Patent Num. 5,051,996), hereinafter Bergeson.
Regarding claim 1, Ziaja teaches (in bold):
A method for detecting defects in a computer chip based on accuracy of a computing unit (Ziaja, paragraphs [0010], [0056], [0084]; Figures 3, 4 and 10. “Logic BIST generates and applies a large number of pseudo-random test vectors, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors).” These differences represent defects in accuracy. In Figures 3, 4 and 10 the compressed results (signatures) of ALU 340, 440, 1080 are stored in an MISR and compared with precompiled compressed results signatures to detect differences.), the method comprising:
synchronizing, by one or more processors, a plurality of built-in self testing (BIST) instances of a BIST controller, the plurality of BIST instances for respectively generating a plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronizing” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronized).),
generating, by the one or more processors, the plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronously” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronously).);
providing, by the one or more processors, the plurality of random strings of bits to respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0056] teaches a vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
receiving, by the one or more processors, a plurality of partial calculations from the respective data columns of the computing unit based on the plurality of random strings of bits (Ziaja, paragraphs [0053] to [0056]; Figures 3, 4, and 10. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (a column) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.). While Zaija does teach comparing the one or more signatures to one or more expected signatures to determine whether the computing unit is outputting accurate results (Ziaja, paragraphs [0054], [0056], [0062], [0075]; Figures 3, 4 and 10. As noted in [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails.), he does not teach doing so with partial calculations.
Bergeson, in the same field of endeavor, does teach:
compressing, by the one or more processors, the plurality of partial calculations into respective signatures and
comparing, by the one or more processors, the respective signatures to respective expected signatures to determine whether the computing unit is outputting accurate partial calculations from the respective data columns (column 3, lines 43-47, wherein tests are run on a PCB on each individual component of the PCB, which implies each test on a component is a partial calculation of the PCB as whole; column 4, lines 16-20, wherein each circuit response of multiple streams (partial calculations) are compressed into its own respective signature and the respective signature is compared to a known good signature to determine whether the signatures match. Since the signatures are derived from the partial calculation streams, this will determine which component in the PCB is faulty, as taught in the prior column 3 citation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ziaja to incorporate the teachings of Bergeson and provide for receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures because use of partial calculations is a more efficient, simple and reliable means for determining whether there is a fault in an electronic circuit (Bergeson, col. 1, lines 18-20 and col. 2, 33-36).
Regarding dependent claim 2, Ziaja teaches:
stopping, by the one or more processors, operation of the computing unit (Ziaja, paragraph [0049], Fig. 6, [0105] “mitigate the results of a defect …by…shutting it down”).
Bergeson teaches determining, by the one or more processors, that the computing unit is outputting inaccurate partial calculations based on one or more of the respective signatures not matching their respective expected signatures (column 4, lines 16-20, see claim 1);
Regarding dependent claim 4, Ziaja teaches wherein generating each of the random strings of bits further comprises loading an initial value and scrambling the initial value or loading a pseudorandom binary sequence (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits.).
Regarding dependent claim 5, Ziaja teaches:
converting, by the one or more processors, the plurality of random strings of bits to a plurality of data streams based on predetermined data profiles (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. Paragraph [0053] “In BIST mode, the test patterns may include deterministic vectors targeted at memory testing, and pseudo-random data targeted at logic testing.” Paragraph [0054] “BIST controller 370 may generate or output a series of memory tests (test patterns optimized for detecting a memory error — such as a march algorithm, RAM sequential, zero- one, checkerboard, butterfly, sliding diagonal, etc.), … It may also generate a series of pseudo-random test vectors…”); and
providing, by the one or more processors, the plurality of data streams to the respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (columns) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.).
Regarding dependent claim 6, Ziaja teaches wherein the predetermined data profiles comprise at least one of random input values, light or heavy input values, inputs with ascending or descending values, inputs with values representing hills or valleys, or inputs toggled with low or high values (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. Paragraph [0053] “In BIST mode, the test patterns may include deterministic vectors targeted at memory testing, and pseudo-random data targeted at logic testing.” Paragraph [0054] “BIST controller 370 may generate or output a series of memory tests (test patterns optimized for detecting a memory error — such as a march algorithm, RAM sequential, zero- one, checkerboard, butterfly, sliding diagonal, etc.), … It may also generate a series of pseudo-random test vectors…”).
Regarding dependent claim 7, Ziaja teaches wherein the predetermined data profiles comprise customized profiles having a programmable data range and probability (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. Paragraph [0053] “In BIST mode, the test patterns may include deterministic vectors targeted at memory testing, and pseudo-random data targeted at logic testing.” Paragraph [0054] “BIST controller 370 may generate or output a series of memory tests (test patterns optimized for detecting a memory error — such as a march algorithm, RAM sequential, zero- one, checkerboard, butterfly, sliding diagonal, etc.), … It may also generate a series of pseudo-random test vectors…”).
Regarding dependent claim 8, Ziaja teaches wherein providing the plurality of random strings of bits to the respective data columns of the computing unit further comprises at least one of providing a specific value every cycle, providing a random value every cycle, holding a last value for one or more cycles, or operating according to a pulse mode (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0052] teaches “operation of ALU 340 can be determined by an ALU control signal … provided in each instruction cycle in a control flow setting”).
Regarding dependent claim 9, Ziaja teaches wherein the one or more expected signatures represent respective ground truth values for the partial calculations (Ziaja, paragraph [0075], Step 590 – storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature [i.e. ground truth value] to determine a test result.). (see claim for Bergeson teaching the partial calculation).
Regarding dependent claim 10, Ziaja teaches wherein comparing the respective signatures to respective expected signatures further determines a health or minimum voltage of the computer chip (Ziaja, paragraph [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails. Paragraph 0105 teaches determining related defects in a chip (i.e. health) and this “information makes it possible to mitigate the results of a defect, for example by replacing a configurable unit, shutting it down, slowing it down, speeding it up, or any other action that keeps array of configurable units 800 functioning acceptably.”).
Regarding claim 11, Ziaja teaches (in bold):
A system comprising:
one or more processors (Ziaja, paragraph [0131] “programmable processor”. Abstract and [0014] teaches a test controller that is a type of processor); and
one or more storage devices coupled to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors (Ziaja, paragraph [0014] teaches memory (i.e. storage device) and test controller manages a series of steps and generates test patterns. Paragraph [0049] teaches test instructions) to perform operations for detecting defects in a computer chip based on accuracy of a computing unit (Ziaja, paragraphs [0010], [0056], [0084]; Figures 3, 4 and 10. “Logic BIST generates and applies a large number of pseudo-random test vectors, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors).” These differences represent defects in accuracy. In Figures 3, 4 and 10 the compressed results (signatures) of ALU 340, 440, 1080 are stored in an MISR and compared with precompiled compressed results signatures to detect differences.), the operations comprising:
synchronizing a plurality of built-in self testing (BIST) instances of a BIST controller, the plurality of BIST instances for respectively generating a plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronizing” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronized).),
generating the plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronously” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronously).);
providing the plurality of random strings of bits to respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0056] teaches a vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
receiving a plurality of partial calculations from the respective data columns of the computing unit based on the plurality of random strings of bits (Ziaja, paragraphs [0053] to [0056]; Figures 3, 4, and 10. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (a column) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.);
While Zaija does teach comparing the one or more signatures to one or more expected signatures to determine whether the computing unit is outputting accurate results (Ziaja, paragraphs [0054], [0056], [0062], [0075]; Figures 3, 4 and 10. As noted in [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails.), he does not teach doing so with partial calculations.
Bergeson, in the same field of endeavor, does teach:
compressing, by the one or more processors, the plurality of partial calculations into respective signatures and
comparing, by the one or more processors, the respective signatures to respective expected signatures to determine whether the computing unit is outputting accurate partial calculations from the respective data columns (column 3, lines 43-47, wherein tests are run on a PCB on each individual component of the PCB, which implies each test on a component is a partial calculation of the PCB as whole; column 4, lines 16-20, wherein each circuit response of multiple streams (partial calculations) are compressed into its own respective signature and the respective signature is compared to a known good signature to determine whether the signatures match. Since the signatures are derived from the partial calculation streams, this will determine which component in the PCB is faulty, as taught in the prior column 3 citation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ziaja to incorporate the teachings of Bergeson and provide for receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures because use of partial calculations is a more efficient, simple and reliable means for determining whether there is a fault in an electronic circuit (Bergeson, col. 1, lines 18-20 and col. 2, 33-36).
Claims 12, 14-19, the system that implements the method of claims 2, 4-9, respectively, are rejected on the same grounds as claims 2, 4-9.
Regarding claim 20, Ziaja teaches (in bold):
A non-transitory computer readable medium for storing instructions that, when executed by one or more processors, cause the one or more processors (Ziaja, paragraph [0131] “programmable processor”. Abstract and [0014] teaches a test controller that is a type of processor. Paragraph [0014] teaches memory (i.e. computer readable medium) and test controller manages a series of steps and generates test patterns. Paragraph [0049] teaches test instructions.) to perform operations for detecting defects in a computer chip based on accuracy of a computing unit (Ziaja, paragraphs [0010], [0056], [0084]; Figures 3, 4 and 10. “Logic BIST generates and applies a large number of pseudo-random test vectors, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors).” These differences represent defects in accuracy. In Figures 3, 4 and 10 the compressed results (signatures) of ALU 340, 440, 1080 are stored in an MISR and compared with precompiled compressed results signatures to detect differences.), the operations comprising:
synchronizing a plurality of built-in self testing (BIST) instances of a BIST controller, the plurality of BIST instances for respectively generating a plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronizing” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronized).), each random string of bits corresponding to a data column of the computing unit (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
generating the plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronously” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronously).);
providing the plurality of random strings of bits to respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0056] teaches a vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
receiving a plurality of partial calculations from the respective data columns of the computing unit based on the plurality of random strings of bits (Ziaja, paragraphs [0053] to [0056]; Figures 3, 4, and 10. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (a column) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.). While Zaija does teach comparing the one or more signatures to one or more expected signatures to determine whether the computing unit is outputting accurate results (Ziaja, paragraphs [0054], [0056], [0062], [0075]; Figures 3, 4 and 10. As noted in [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails.), he does not teach doing so with partial calculations.
Bergeson, in the same field of endeavor, does teach:
compressing, by the one or more processors, the plurality of partial calculations into respective signatures and
comparing, by the one or more processors, the respective signatures to respective expected signatures to determine whether the computing unit is outputting accurate partial calculations from the respective data columns (column 3, lines 43-47, wherein tests are run on a PCB on each individual component of the PCB, which implies each test on a component is a partial calculation of the PCB as whole; column 4, lines 16-20, wherein each circuit response of multiple streams (partial calculations) are compressed into its own respective signature and the respective signature is compared to a known good signature to determine whether the signatures match. Since the signatures are derived from the partial calculation streams, this will determine which component in the PCB is faulty, as taught in the prior column 3 citation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ziaja to incorporate the teachings of Bergeson and provide for receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures because use of partial calculations is a more efficient, simple and reliable means for determining whether there is a fault in an electronic circuit (Bergeson, col. 1, lines 18-20 and col. 2, 33-36).
Response to Arguments
3. Applicant's arguments filed 7/9/26 have been fully considered but they are not persuasive.
The applicant has argued that the cited art of Bergson does not teach the amended language. The examiner respectfully disagrees. The examiner has stated his argument in the claim rejections, and as follows:
Bergeson, in the same field of endeavor, does teach:
compressing, by the one or more processors, the plurality of partial calculations into respective signatures and
comparing, by the one or more processors, the respective signatures to respective expected signatures to determine whether the computing unit is outputting accurate partial calculations from the respective data columns (column 3, lines 43-47, wherein tests are run on a PCB on each individual component of the PCB, which implies each test on a component is a partial calculation of the PCB as whole; column 4, lines 16-20, wherein each circuit response of multiple streams (partial calculations) are compressed into its own respective signature and the respective signature is compared to a known good signature to determine whether the signatures match. Since the signatures are derived from the partial calculation streams, this will determine which component in the PCB is faulty, as taught in the prior column 3 citation).
Conclusion
4. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
- US 2022/0244956A1 to Deadman et al.: BIST partial calculation in a device and comparing signatures.
5. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER S MCCARTHY whose telephone number is (571)272-3651. The examiner can normally be reached Monday-Friday 8:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113
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