DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-2, 4-12, and 14-20 are pending for examination in this application. Claims 1, 11, and 20 are independent claims. This Office Action is Non-final.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office Action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 03/17/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ziaja et al., (PCT Patent Publn No. WO 2023/283073 A1, cited in IDS), hereinafter Ziaja in view of Bergeson et al., (U.S. Patent Num. 5,051,996), hereinafter Bergeson.
Regarding claim 1, Ziaja teaches (in bold):
A method for detecting defects in a computer chip based on accuracy of a computing unit (Ziaja, paragraphs [0010], [0056], [0084]; Figures 3, 4 and 10. “Logic BIST generates and applies a large number of pseudo-random test vectors, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors).” These differences represent defects in accuracy. In Figures 3, 4 and 10 the compressed results (signatures) of ALU 340, 440, 1080 are stored in an MISR and compared with precompiled compressed results signatures to detect differences.), the method comprising:
synchronizing, by one or more processors, a plurality of built-in self testing (BIST) instances of a BIST controller, the plurality of BIST instances for respectively generating a plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronizing” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronized).), each random string of bits corresponding to a data column of the computing unit (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
synchronously generating, by the one or more processors, the plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronously” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronously).);
providing, by the one or more processors, the plurality of random strings of bits to respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0056] teaches a vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
receiving, by the one or more processors, a plurality of partial calculations from the respective data columns of the computing unit based on the plurality of random strings of bits (Ziaja, paragraphs [0053] to [0056]; Figures 3, 4, and 10. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (a column) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.);
compressing, by the one or more processors, the partial calculations into one or more signatures (Ziaja, paragraphs [0056], [0062], [0074]. Under control of BIST control unit 370, 470, 1052 the result of the SIMD ALU is compressed and stored in register 385, 485, 1057. As noted in [0074] Step 580 - compressing the test result to obtain a signature. An implementation may use any compression technique known in the art to compress the ALU output data, including cyclic redundancy check, ones count, transition count, parity checking, syndrome checking, etc.); and
comparing, by the one or more processors, the one or more signatures to one or more expected signatures to determine whether the computing unit is outputting accurate results (Ziaja, paragraphs [0054], [0056], [0062], [0075]; Figures 3, 4 and 10. As noted in [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails.).
Ziaja does not distinctly disclose receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures. Bergeson, in the same field of endeavor, teaches receiving a plurality of partial calculations (Bergeson, col. 4, lines 57-66 input data stream is of “any length”, output is generated based on the n-bit residue remaining in the shift register.) and compressing the partial calculations into a signature (Bergeson, col. 4, lines 63-65 “n-bit residue is called the signature of the input data” and the Abstract and col. 4, lines 1-23 teaches that signature is lengthy bit stream compressed into a short 10 to 20-bit signature, i.e. signature is a compressed bit stream. Thus, Bergeson teaches that the n-bit residue partial calculation is compressed into a signature.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ziaja to incorporate the teachings of Bergeson and provide for receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures because use of partial calculations is a more efficient, simple and reliable means for determining whether there is a fault in an electronic circuit (Bergeson, col. 1, lines 18-20 and col. 2, 33-36).
Regarding dependent claim 2, Ziaja teaches:
determining, by the one or more processors, the computing unit is outputting inaccurate results (Ziaja, paragraphs [0010] “detect any differences (i.e., errors)” and [0054]. Paragraph [0056] teaches “determine if they match (pass) or are different (fail)” and Fig. 5, step 590 paragraph[ 0075], [0084], [0105]); and
stopping, by the one or more processors, operation of the computing unit (Ziaja, paragraph [0049], Fig. 6, [0105] “mitigate the results of a defect …by…shutting it down”).
Regarding dependent claim 4, Ziaja teaches wherein generating each of the random strings of bits further comprises loading an initial value and scrambling the initial value or loading a pseudorandom binary sequence (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits.).
Regarding dependent claim 5, Ziaja teaches:
converting, by the one or more processors, the plurality of random strings of bits to a plurality of data streams based on predetermined data profiles (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. Paragraph [0053] “In BIST mode, the test patterns may include deterministic vectors targeted at memory testing, and pseudo-random data targeted at logic testing.” Paragraph [0054] “BIST controller 370 may generate or output a series of memory tests (test patterns optimized for detecting a memory error — such as a march algorithm, RAM sequential, zero- one, checkerboard, butterfly, sliding diagonal, etc.), … It may also generate a series of pseudo-random test vectors…”); and
providing, by the one or more processors, the plurality of data streams to the respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (columns) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.).
Regarding dependent claim 6, Ziaja teaches wherein the predetermined data profiles comprise at least one of random input values, light or heavy input values, inputs with ascending or descending values, inputs with values representing hills or valleys, or inputs toggled with low or high values (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. Paragraph [0053] “In BIST mode, the test patterns may include deterministic vectors targeted at memory testing, and pseudo-random data targeted at logic testing.” Paragraph [0054] “BIST controller 370 may generate or output a series of memory tests (test patterns optimized for detecting a memory error — such as a march algorithm, RAM sequential, zero- one, checkerboard, butterfly, sliding diagonal, etc.), … It may also generate a series of pseudo-random test vectors…”).
Regarding dependent claim 7, Ziaja teaches wherein the predetermined data profiles comprise customized profiles having a programmable data range and probability (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. Paragraph [0053] “In BIST mode, the test patterns may include deterministic vectors targeted at memory testing, and pseudo-random data targeted at logic testing.” Paragraph [0054] “BIST controller 370 may generate or output a series of memory tests (test patterns optimized for detecting a memory error — such as a march algorithm, RAM sequential, zero- one, checkerboard, butterfly, sliding diagonal, etc.), … It may also generate a series of pseudo-random test vectors…”).
Regarding dependent claim 8, Ziaja teaches wherein providing the plurality of random strings of bits to the computing unit further comprises at least one of providing a specific value every cycle, providing a random value every cycle, holding a last value for one or more cycles, or operating according to a pulse mode (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0052] teaches “operation of ALU 340 can be determined by an ALU control signal … provided in each instruction cycle in a control flow setting”).
Regarding dependent claim 9, Ziaja teaches wherein the one or more expected signatures represent one or more ground truth values (Ziaja, paragraph [0075], Step 590 – storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature [i.e. ground truth value] to determine a test result.).
Regarding dependent claim 10, Ziaja teaches wherein comparing the one or more signatures to one or more expected signatures further determines a health or minimum voltage of the computer chip (Ziaja, paragraph [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails. Paragraph 0105 teaches determining related defects in a chip (i.e. health) and this “information makes it possible to mitigate the results of a defect, for example by replacing a configurable unit, shutting it down, slowing it down, speeding it up, or any other action that keeps array of configurable units 800 functioning acceptably.”).
Regarding claim 11, Ziaja teaches (in bold):
A system comprising:
one or more processors (Ziaja, paragraph [0131] “programmable processor”. Abstract and [0014] teaches a test controller that is a type of processor); and
one or more storage devices coupled to the one or more processors and storing instructions that, when executed by the one or more processors, cause the one or more processors (Ziaja, paragraph [0014] teaches memory (i.e. storage device) and test controller manages a series of steps and generates test patterns. Paragraph [0049] teaches test instructions) to perform operations for detecting defects in a computer chip based on accuracy of a computing unit (Ziaja, paragraphs [0010], [0056], [0084]; Figures 3, 4 and 10. “Logic BIST generates and applies a large number of pseudo-random test vectors, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors).” These differences represent defects in accuracy. In Figures 3, 4 and 10 the compressed results (signatures) of ALU 340, 440, 1080 are stored in an MISR and compared with precompiled compressed results signatures to detect differences.), the operations comprising:
synchronizing a plurality of built-in self testing (BIST) instances of a BIST controller, the plurality of BIST instances for respectively generating a plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronizing” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronized).), each random string of bits corresponding to a data column of the computing unit (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
synchronously generating the plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronously” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronously).);
providing the plurality of random strings of bits to respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0056] teaches a vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
receiving a plurality of partial calculations from the respective data columns of the computing unit based on the plurality of random strings of bits (Ziaja, paragraphs [0053] to [0056]; Figures 3, 4, and 10. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (a column) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.);
compressing the partial calculations into one or more signatures (Ziaja, paragraphs [0056], [0062], [0074]. Under control of BIST control unit 370, 470, 1052 the result of the SIMD ALU is compressed and stored in register 385, 485, 1057. As noted in [0074] Step 580 - compressing the test result to obtain a signature. An implementation may use any compression technique known in the art to compress the ALU output data, including cyclic redundancy check, ones count, transition count, parity checking, syndrome checking, etc.); and
comparing the one or more signatures to one or more expected signatures to determine whether the computing unit is outputting accurate results (Ziaja, paragraphs [0054], [0056], [0062], [0075]; Figures 3, 4 and 10. As noted in [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails.).
Ziaja does not distinctly disclose receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures. Bergeson, in the same field of endeavor, teaches receiving a plurality of partial calculations (Bergeson, col. 4, lines 57-66 input data stream is of “any length”, output is generated based on the n-bit residue remaining in the shift register.) and compressing the partial calculations into a signature (Bergeson, col. 4, lines 63-65 “n-bit residue is called the signature of the input data” and the Abstract and col. 4, lines 1-23 teaches that signature is lengthy bit stream compressed into a short 10 to 20-bit signature, i.e. signature is a compressed bit stream. Thus, Bergeson teaches that the n-bit residue partial calculation is compressed into a signature.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ziaja to incorporate the teachings of Bergeson and provide for receiving a plurality of partial calculations and compressing the partial calculations into one or more signatures because use of partial calculations is a more efficient, simple and reliable means for determining whether there is a fault in an electronic circuit (Bergeson, col. 1, lines 18-20 and col. 2, 33-36).
Claims 12, 14-19, the system that implements the method of claims 2, 4-9, respectively, are rejected on the same grounds as claims 2, 4-9.
Regarding claim 20, Ziaja teaches (in bold):
A non-transitory computer readable medium for storing instructions that, when executed by one or more processors, cause the one or more processors (Ziaja, paragraph [0131] “programmable processor”. Abstract and [0014] teaches a test controller that is a type of processor. Paragraph [0014] teaches memory (i.e. computer readable medium) and test controller manages a series of steps and generates test patterns. Paragraph [0049] teaches test instructions.) to perform operations for detecting defects in a computer chip based on accuracy of a computing unit (Ziaja, paragraphs [0010], [0056], [0084]; Figures 3, 4 and 10. “Logic BIST generates and applies a large number of pseudo-random test vectors, compresses the results obtained at-speed, and compares the compressed results with precompiled compressed results to detect any differences (i.e., errors).” These differences represent defects in accuracy. In Figures 3, 4 and 10 the compressed results (signatures) of ALU 340, 440, 1080 are stored in an MISR and compared with precompiled compressed results signatures to detect differences.), the operations comprising:
synchronizing a plurality of built-in self testing (BIST) instances of a BIST controller, the plurality of BIST instances for respectively generating a plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronizing” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronized).), each random string of bits corresponding to a data column of the computing unit (Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
synchronously generating the plurality of random strings of bits (Examiner in light of applicant’s originally filed specification in paragraph 0028 interprets the claim term “synchronously” as all instances can synchronize at the start of a test and signals from all instances resume all at once. See MPEP 2111.01(V). Ziaja, paragraphs [0053], [0054], [0056]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 generates a series of pseudo-random input vectors comprising each 16 parallel 32-bit values as inputs [ i.e. plurality of BIST instances] for SIMD ALU 340, 440, 1080. A vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating (as taught in paragraph 0053 “test vectors generated by BIST controller 370”. Generating test vectors also taught in paragraphs 0054, 0056) and processing the 16 parallel lanes of data that start/resume all at once (i.e. synchronously).);
providing the plurality of random strings of bits to respective data columns of the computing unit (Ziaja, paragraph [0054]; Figures 3, 4 and 10. BIST control unit 370, 470, 1052 provides the pseudo-random test vectors to SIMD ALU 340, 400, 1080 either over memory 310, 410, 1060 or directly over logic 420 of Figure 4. Paragraph [0056] teaches a vector comprising 16 parallel 32-bit values is a column of 16 data values, each value having 32 random bits. Each generated test vector corresponds thus to a column of input values for testing the SIMD ALU. As noted in [0056], a datapath may include 16 parallel 32-bit lanes for a total width of 512 bits ... ALU 340 may include a SIMD, and may thus be capable of generating and processing the 16 parallel lanes of data that start/resume all at once.);
receiving a plurality of partial calculations from the respective data columns of the computing unit based on the plurality of random strings of bits (Ziaja, paragraphs [0053] to [0056]; Figures 3, 4, and 10. As noted in [0056], ALU 340, which processes the data it receives from intermediate bus 392. ALU 340 may include a SIMD, and may thus be capable of processing the 16 parallel lanes of data (a column) simultaneously. It outputs the results on output databus 398. The result of parallel computations of SIMD ALU 340, 400, 1080 are stored in MISR (multiple-input signature register) 380, 480, 1055.);
compressing the plurality of partial calculations into one or more signatures (Ziaja, paragraphs [0056], [0062], [0074]. Under control of BIST control unit 370, 470, 1052 the result of the SIMD ALU is compressed and stored in register 385, 485, 1057. As noted in [0074] Step 580 - compressing the test result to obtain a signature. An implementation may use any compression technique known in the art to compress the ALU output data, including cyclic redundancy check, ones count, transition count, parity checking, syndrome checking, etc.); and
comparing the one or more signatures to one or more expected signatures to determine whether the computing unit is outputting accurate results (Ziaja, paragraphs [0054], [0056], [0062], [0075]; Figures 3, 4 and 10. As noted in [0075], Step 590 - storing the signature in a register. The register may be part of a MISR. Implementations may further compare the signature with a precompiled signature to determine a test result. For example, if the signature matches the precompiled signature, the test passes, and if they don't match, the test fails.).
Ziaja does not distinctly disclose receiving a plurality of partial calculations and compressing the plurality of partial calculations into one or more signatures. Bergeson, in the same field of endeavor, teaches receiving a plurality of partial calculations (Bergeson, col. 4, lines 57-66 input data stream is of “any length”, output is generated based on the n-bit residue remaining in the shift register.) and compressing the plurality of partial calculations into a signature (Bergeson, col. 4, lines 63-65 “n-bit residue is called the signature of the input data” and the Abstract and col. 4, lines 1-23 teaches that signature is lengthy bit stream compressed into a short 10 to 20-bit signature, i.e. signature is a compressed bit stream. Thus, Bergeson teaches that the n-bit residue partial calculation is compressed into a signature.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ziaja to incorporate the teachings of Bergeson and provide for receiving a plurality of partial calculations and compressing the plurality of partial calculations into one or more signatures because use of partial calculations is a more efficient, simple and reliable means for determining whether there is a fault in an electronic circuit (Bergeson, col. 1, lines 18-20 and col. 2, 33-36).
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-12, and 14-20 have been fully considered but they are not persuasive.
Applicant argues on page 8 of the Amendment submitted 03/17/2026 that “Instead of being ‘synchronously generated’, as recited in claim 1, the pseudo-random test vectors are provided in a ‘sequence of tests that uncover memory defects’. Ziaja, [0067].” Th Examiner respectfully disagrees with this characterization of Ziaja as the claim mapping given above in independent claim 1 clearly describes synchronously generating the plurality of random strings of bits. The Applicant’s sequence of tests referred to in paragraph 0067 are different types of tests that include internal sequences in the test, paragraph 0067 states “series of memory test vectors may follow any sequence of tests that uncover memory defects, including sequences determined in a march algorithm, RAM sequential, zero-one, checkerboard…and other memory test algorithms.” Thus, Applicant’s argument is not persuasive and the rejection of independent claim 1 is respectfully maintained.
Applicant further argues on page 8 that “the simultaneous processing of data refers to the processing of the pseudo-random input vectors by the ALU and not the generation of the pseudo-random input vectors by the BIST controller. Ziaja, [0056].” The Examiner respectfully disagrees with Applicant’s argument as the claim mapping in independent claim 1 describes generation of the plurality of the random string of bits by the BIST controller. Please see updated claim mapping of claim 1. Thus, Applicant’s argument is not persuasive and the rejection of independent claim 1 is respectfully maintained.
Applicant’s arguments at the bottom of page 8 with respect to claim 1 have been fully considered but are moot because the arguments are directed to the claim amendments that are addressed in the Examiner’s new grounds of rejections given above.
Applicant relies on the same arguments for independent claims 11 and 20 as for claim 1 and provides no further arguments.
Applicant provides no other arguments for the remaining dependent claims and the Examiner respectfully maintains the rejections of these claims as given in the claim mappings above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
In the interests of compact prosecution, Applicants are invited to contact the examiner via electronic media pursuant to USPTO policy outlined MPEP § 502.03. All electronic communication must be authorized in writing. Applicants may wish to file an Internet Communications Authorization Form PTO/SB/439. Applicants may wish to request an interview using the Interview Practice website: http://www.uspto.gov/patent/laws-and-regulations/interview-practice.
Applicants are reminded Internet e-mail may not be used for communication for matters under 35 U.S.C. § 132 or which otherwise require a signature. A reply to an Office action may NOT be communicated by Applicants to the USPTO via Internet e-mail. If such a reply is submitted by Applicants via Internet e-mail, a paper copy will be placed in the appropriate patent application file with an indication that the reply is NOT ENTERED. See MPEP § 502.03(II).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to INDRANIL CHOWDHURY whose telephone number is (571)272-0446. The examiner can normally be reached Mon.-Fri. 9:30-7:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/INDRANIL CHOWDHURY/Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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