DEVICE AND CIRCUIT FOR MEASURING A DERIVATIVE

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on May 21, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 1, 2026, has been entered. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Response to Amendment The Amendment filed July 1, 2026, has been entered. Claims 1-20 remain pending in the application. Claims 1-4, 6, 8-9, 18, & 20 have been amended. Applicant’s amendments to the Claims have overcome each and every 112(a) rejection previously set forth in the Non-Final Office Action mailed April 2, 2026, hereafter referred to as the Final Office Action. Response to Arguments Applicant's arguments filed July 1, 2026, have been entered and fully considered but they are not persuasive. Applicant in their submitted response has presented the argument, please refer to pgs. 12-16 of Applicant’s remarks, that the prior art references in amended independent claims 1 & similarly amended independent claims 18, under U.S.C. § 103, Aaltonen in view of Matsuo, and amended independent claim 20, under U.S.C. § 103, Aaltonen in view of Matsuo, and further in view of Hughes, as cited by the Applicant, fail to teach, suggest, and/or disclose individually or in combination, each and every single limitation currently recited in amended independent claims 1, 18 & 20. In summary, Applicant argues that Aaltonen, Matsuo, and Hughes, fail to teach or suggest “M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential, M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first node configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node, and secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit”. The Examiner respectfully disagrees and would like to break the arguments presented into three sections. First, the Examiner would like to highlight that in light of the amendments in independent claims 1, 18, & 20, new grounds of rejection are being made in view of Aaltonen (US 2015/0226556 A1, hereinafter, Aaltonen), in view of Matsuo (US 5986599, hereinafter, Matsuo), and further in view of new prior art references, Huang (US 2022/0149861 A1, hereinafter, Huang), and Maurino (US 2022/0239308 A1, hereinafter, Maurino). Aaltonen and Matsuo lack the specific M-capacitor array and the exact primary/secondary switching topology recited in amended claims 1, 18, & 20. The updated rejections for amended independent claims 1, 18, & 20 relies on the combined teachings of the new prior art references in view of Huang, and further in view of Maurino. An Applicant cannot overcome a rejection by arguing that one or two references fail to teach a limitation when that limitation is now rejected, in light of the amendments, under new grounds of rejections. See MPEP 2145(V). Second, the Examiner would like to highlight that the updated rejections relied upon Huang to teach the M capacitive elements connected to a reference potential. Furthermore, the Examiner relied upon Maurino to teach the M primary switches coupling the elements to a first node, and the secondary switches coupling the elements to the input of the first circuit. The test for obviousness is not whether the claimed invention is expressly suggested in any one or two of the references, but whether the claimed subject matter as a whole would have been obvious to a POSITA in view of the combined teachings of all applied references. See MPEP 2144.04, 2145. 2143.02, and 2143. Due to the new prior art references incorporated to cure the deficiencies of amended independent claims 1, 18, & 20, to account for all limitations, the rejections are maintained. Third, the Examiner would like to highlight that independent claims 18 & 20 were amended to include limitations similar to those of claim 1 and relies on the identical rationale to assert their patentability. Due to the updated grounds of rejection applied in combination of Aaltonen, Matsuo, Huang, and Maurino, which fully account for the shared structural features, specifically the M-capacitor array and the primary and secondary switching topology, for the exact reasons detailed above for independent claim 1, Applicant’s arguments are similarly unpersuasive, and the rejection of independent claims 18 & 20 are maintained. Please see below for updated rejections for amended independent claims 1, 18, & 20. The Examiner respectfully disagrees with the Applicant’s contentions that Aaltonen, in view of Matsuo, in view of Huang, and further in view of Maurino, fail to disclose, teach, and/or suggest individually or in combination, the above stated amendments in independent claim 1, and similarly amended independent claims 18 & 20. Independent claim 20 is rejected further in view of Hurwitz et al. (US 2019/0081604 A1, hereinafter, Hurwitz). The addition of the new prior art references further disclose the additional limitations that have been amended and included in independent claims 1, 18, & 20, and meet these requirements. Therefore, the Applicant’s arguments are unconvincing and the rejections of independent claims 1, 18, & 20, and dependent claims 2-17 & 19, which depend from and incorporate the limitations of amended independent claims 1 & 18, are respectively maintained. Updated rejections based on the amended features follow. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 11, & 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Aaltonen (US 2015/0226556 A1, Pub. Date Aug. 13, 2025, hereinafter Aaltonen), in view of Huang et al. (US 2022/0149861 A1, Pub. Date May 12, 2022, hereinafter, Huang), in view of Maurino (US 2022/0239308 A1, Pub. Date Jul. 28, 2022, hereinafter, Maurino), and further in view of Matsuo (US 5986599, Pat. Date Nov. 16, 1999, hereinafter Matsuo). Regarding independent claim 1, Aaltonen, teaches: A derivative measurement circuit, comprising (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal): a control circuit configured to (Figs. 2-3 & 5; [0030] & [0042]-[0043]: clock circuitry and controller function as a control circuit receiving a first clock (PLL reference) to generate derived secondary clock phases (C and XC) that implement successive sampling cycles): receive a first clock signal available at a third input of the measurement circuit (Figs. 2-3 & 5; [0030] &[0042]-[0043]: operation is controlled by clock signals C and XC, which are derived from a master clock signal synchronized with the resonator’s oscillation frequency f0, “The SC derivator circuit may be clocked at the same frequency as the input signal coming into the sampling amplifier from the HPF…”); implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal (Figs. 2-3 & 5; [0042]-[0043]: circuit operates in successive cycles corresponding to the sampling period of the input signal, each cycle involving two non-overlapping clock phases C and XC, which can be considered M=2 periods, and the “clock circuitry (23)” and “START UNIT (500)” generate and use clock signals (C, XC, CLK SIGNALS) to control the sampling amplifier switches in successive cycles and periods); and PNG media_image1.png 681 826 media_image1.png Greyscale PNG media_image2.png 763 462 media_image2.png Greyscale PNG media_image3.png 599 740 media_image3.png Greyscale Aaltonen, is silent in regard to: M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential; However, Huang, further teaches: M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential (Fig. 1; [0021]-[0022] & [0026]: demonstrates an array of M capacitors (where M = N) with bottom terminals connected to reference potentials (VR/GND)); It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the derivator of Aaltonen with the M capacitive elements of Huang. It is known in the art from Aaltonen to utilize a switched capacitor derivator circuit with input capacitances to extract amplitude data. Aaltonen, however, does not detail M capacitive elements, where M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential. Huang teaches a sample and hold circuit comprising M capacitive elements, specifically capacitor array 140 with capacitors C1_1 to C1_N, each having a bottom electrode connected to a reference potential such as VR or GND. The motivation to combine these teaches would be to increase the charge storage capacity and enable multi-stage charge redistribution, which predictably improves signal amplification efficiency. This combination represents a substitution of single capacitors with a multi-capacitor array to yield the predictable variation of enhanced dynamic range in a switched-capacitor network (KSR). Aaltonen, and Huang, are silent in regard to: M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first diode configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node; secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit; control the switches such that, at each period of each cycle: the first voltage is memorized on a respective one of the M capacitive elements; and the first input of the first circuit receives the first voltage memorized at a first instant on the respective one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant. However, Maurino, further teaches: M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first diode configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node (Fig. 4; [0003], [0032]-[0033], [0053]-[0054], & [0067]: teaches multiple primary switches (ps1/ps2) that directly connect to respective multi-sampling capacitors to the first node receiving the input voltage (Vin)); secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit (Fig. 4; [0034]-[0035], [0049], & [0055]-[0056]: uses secondary switches (p1/p2) to connect the capacitors to the amplifier’s input node (154) once sampling is complete); and control the switches such that, at each period of each cycle: the first voltage is memorized on a respective one of the M capacitive elements ([0018], [0032], & [0053]: switches are controlled such that the respective capacitors accumulate and hold (memorize) the input voltage during their specific clock period); and the first input of the first circuit receives the first voltage memorized at a first instant on the respective one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant ([0018], [0034]-[0035], [0051], [0055]-[0056], [0061], [0109], & [Claim 19]: topology systematically feeds the voltages sampled at different time instants (e.g., T1 vs. T2) into the differential inputs of the amplifier during separate phases). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined circuit of Aaltonen and Huang to include the primary and secondary switching topology of Maurino. The combination of Aaltonen and Huang discloses a derivator with M capacitive elements but lacks M primary switches coupling the elements to a first node, secondary switches coupling the elements to a first circuit, and controlling the switches to memorize voltages at distinct instants. Maurino teaches M primary switches ps1 and ps2 coupling a second terminal of M capacitive elements C1 and C2 to a first node 152 receiving a first voltage Vin. Maurino further teaches secondary switches p1 and p2 coupling the capacitive elements to the input 154 of a first circuit amplifier120 and controlling the switches such that the first voltage is memorized and the first circuit receives the memorized voltage at different instants T1 through T4. The motivation would be to decouple the charging and discharging phases of the M capacitive elements to maintain a short, consistent time delay between sampling intervals. This modification constitutes the use of a known technique to improve similar devices by predictably rejecting flicker noise and reducing jitter in the sampling phases (KSR). Aaltonen, Huang, and Maurino, are silent in regard to: a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between the first and second inputs of the first circuit; a control circuit configured to: receive a first clock signal available at a third input of the measurement circuit; implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal; and However, Matsuo, further teaches: a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between the first and second inputs of the first circuit (Fig. 7; [Col. 1, ll. 11-44 & 63-67], [Col. 2, ll. 23-31], [Col. 3, ll. 7-21, 42-53, & 62-67], [Col. 4, ll. 1-44], [Col. 6, ll. 1-63], [Col. 7, ll. 13-30], [Col. 14, ll. 10-18], [Col. 15, ll. 59-67], [Col. 16, ll. 1-7 & 15-37], [Claim 1], & [Claim 12]: provides the core difference amplifier (first circuit) that processes the sampled inputs and outputs the resultant voltage difference); It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Matsuo’s difference amplifier into the modified primary device in place of a standard comparator. The preceding combination discloses a multi-capacitor switching topology but does not detail a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between first and second inputs of the first circuit. Matsuo teaches a first circuit, specifically an operational amplifier 10, that receives sampled inputs as nodes ND5 and ND6. Matsuo’s operational amplifier 10 is configured to amplify the differential voltage and deliver a second voltage comprising output signal D and inverted signal XD indicating the voltage difference. The motivation for this incorporation is to accurately compute the differential voltage across the sampled instants while preventing the operation point from fluctuating outside the input range. This represents a substitution of one known amplifier element for another to obtain the predictable variation of stabilized voltage comparison without increasing circuit size (KSR). Regarding dependent claim 3, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein: Aaltonen, is silent in regard to: M is equal to 2 and there are 4 secondary switches; and the control circuit is configured to control the switches such that, at each cycle: that of the M capacitive elements on which the first voltage is memorized is different at each period of the cycle, and However, Maurino, further teaches: M is equal to 2 and there are 4 secondary switches (Fig. 4; [0032]-[0033], [0048], [0053]-[0054], [Claim 3], & [Claim 4]: illustrates a double-sampling setup with exactly two capacitive elements (C1/C2) and exactly four secondary switches (two p1 switches and two p2 switches) coupling the capacitors to the amplifier stage); and the control circuit is configured to control the switches such that, at each cycle ([0032]-[0033], [0053]-[0054], [Claim 3], & [Claim 4]): that of the M capacitive elements on which the first voltage is memorized is different at each period of the cycle ([0032]-[0033], [0053]-[0054], [Claim 3], & [Claim 4]: the control circuit sequentially alternates the memorization (accumulation) of the input voltage between the two capacitors across different consecutive clock periods (T1 and T2)), and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s derivator to incorporate Maurino’s two-capacitor alternating sampling arrangement. Aaltonen does not teach restricting M to 2, using exactly 4 secondary switches, or controlling the switches such that the capacitor memorizing the voltage alternates at each period. Maurino teaches a double-sampling switched-capacitor integrator where M is equal to 2 (capacitors 111/112) using 4 secondary switches (p1/p2 sets) and a control circuit configuring the switches such that the element on which the first voltage is memorized is different at each period of the cycle (T1 and T2). The motivation to do is to maintain a short, consistent time delay between sequential samples to improve flicker noise rejection and reduce jitter, regardless of the master clock frequency. This modification is a substitution of one known switched-capacitor sampling arrangement for another to yield the predictable variation of improved low-frequency noise immunity in the measurement circuit (KSR). Aaltonen, and Maurino, are silent in regard to: at each period of the cycle, the second input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the first input of the first circuit receives a voltage across the other of the M capacitive elements. However, Matsuo, further teaches: at each period of the cycle, the second input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the first input of the first circuit receives a voltage across the other of the M capacitive elements (Fig. 7; [Col. 2, ll. 55-67], [Col. 8, ll. 65-67], [Col. 9, ll. 1-21], & [Col. 10, ll. 27-52]: details a “comparison operation” that follows the “sampling operation, during the comparison phase, the switches are reconfigured so that the voltages across the capacitors are used to generate differential inputs V+ and V- for the operation amplifier, the capacitors (e.g., CS1 and CS2) are charged during the sampling operation, and the stored charge is used to determine the voltages V+ and V- in the comparison operation, which is a form of reading a memorized voltage from a capacitor while another capacitor may be used for a new sampling or comparison). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Aaltonen and Maurino combination by implementing Matsuo’s differential input routing for the first circuit. The combination of Aaltonen and Maurino lack routing the voltages such that the first and second inputs of the first circuit receive the respective voltages across the terminals of the memorizing capacitor and the other holding capacitor. Matsuo teaches coupling the terminals of the respective capacitive elements (CS1/CS2) into a differential configuration where the first input (V+) receives the voltage across one capacitor and the second input (V-) receives the voltage across the other capacitor (nodes ND5/ND6). The motivation for this combination is to accurately compute the differential voltage across the sampled instants while keeping operational point fluctuations of the amplifier small. This represents the application of known technique to improve similar devices, predictably allowing the amplifier to directly process the voltage difference between the alternating samples for high-precision analog-to-digital conversion (KSR). Regarding dependent claim 11, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]-[0044]: figure illustrates the switched capacitor derivator circuit, which performs a derivative function to extract amplitude), Aaltonen, is silent in regard to: wherein the measurement circuit further comprises a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit. However, Matsuo, further teaches: wherein the measurement circuit further comprises a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 8, ll. 26-41], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], & [Col. 11, ll. 43-59]: Fig. 3 illustrates a “sampling use capacitor element CS1” connected between the input node ND1 and the amplifier input V-, Fig. 7 illustrates capacitor C1 connected between node ND3 (input to the first circuit/comparator) and ground, functioning to store the DC component and smooth the operational point) and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 8, ll. 26-41], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], & [Col. 11, ll. 43-59]: describes the “…DC component VC is supplied to the capacitor elements C1 and C2 connected to the nodes ND3 and ND4…”, Fig. 7 illustrates the symmetrical capacitor C2 connected between node ND4 (second input to the first circuit/comparator) and ground, performing the identical smoothing function as C1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit, of Matsuo to Aaltonen. In order to attain and improve, by combination, where the derivative measurement circuit of Aaltonen is susceptible to offsets and flicker noise, Matsuo addresses this problem, teaching that connecting capacitive elements C1/C2 to the inputs of a circuit (a comparator, a type of measurement circuit) to store the DC component of the input results in a significant reduction in the fluctuation of the operation points, smoothing the DC operating point. Incorporating Matsuo’s teaching into the derivative measurement circuit of Aaltonen, to improve its stability and accuracy, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR). Regarding dependent claim 13, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0030]-[0031], [0037], [0039], & [0043]-[0044]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator), Aaltonen, is silent in regard to: wherein the measurement circuit further comprises: a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage; and/or a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage. However, Matsuo, further teaches: a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 11-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 16, Claim 1, ll. 50-67], & [Col. 17, Claim 1, ll. 1-37]: describes a voltage comparator circuit that compares an input voltage to a reference voltage (“positive threshold”) and provides a binary output signal (D/XD), Fig. 7 details the circuitry to achieve this, the operational amplifier 10 can be considered a comparator, or its output is latched by latch circuit 20 to produce a binary output D/XD, discloses using a comparator (COMP1) to evaluate the computed difference voltage (the second voltage) against a reference threshold voltage (VRTn - VRBn) to generate a binary output signal (D) indicative of whether the threshold is met); and/or a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 7-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 20, Claim 12, ll. 13-67], [Col. 21, ll.1-11], & [Col. 22, ll. 1-10]: describes a parallel ADC with multiple comparators COMP1 to COMP14, each receiving different reference threshold voltage pairs (VRTn/VRBn), to generate a set of binary signals, conventional to use multiple comparators, each set to a different threshold (e.g., a positive and a negative one in a window comparator configuration), teaches using multiple comparators with different thresholds, the parallel architecture of secondary comparators configured to evaluate the same differential signal against a descending scale of threshold voltages generated by a resistor string). PNG media_image4.png 768 554 media_image4.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage and a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (SC derivator) and a system that uses multiple comparators (COMP1/COMP2) to generate clock signals. Matsuo provides a detailed teaching of voltage comparator circuits, their structure, and their function of comparing an input voltage to a reference threshold to generate a binary output, further establishes the common practice of using a plurality of comparators in a single system, each with its own reference point. The motivation for this modification is to digitize the computed differential analog voltage into a binary format suitable for downstream digital processing or encoding. This modification constitutes the application of a known technique to improve similar devices by predictably enabling high-speed parallel analog-to-digital conversion of the measured derivative signals. By combining, connecting one or more dedicated comparators of Matsuo to the output of the derivator circuit of Aaltonen to monitor its voltage level against predetermined positive and negative thresholds, generating binary flags for a control circuit, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR). Regarding dependent claim 14, Aaltonen, teaches: The derivative measurement circuit according to claim 13 (Fig. 3; [0030]-[0031], [0036]-[0037], [0039], [0043]-[0044], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator), wherein: Aaltonen, is silent in regard to: the measurement circuit comprises the first comparator; and the control circuit is configured to adapt a value of the positive threshold voltage as a function of a value of the first voltage. However, Matsuo, further teaches: the measurement circuit comprises the first comparator ([Col. 1, ll. 7-67]: discloses using a first comparator (COMP1) to evaluate the computed differential voltages and output binary signals); and The Examiner is combining Aaltonen in view of Matsuo by implementing Aaltonen’s teachings that the positive threshold voltage can be raised (adapted) based on the sampled amplitude measurement (the first voltage) ([0065]). the control circuit is configured to adapt a value of the positive threshold voltage as a function of a value of the first voltage ([Abstract], [Col. 8, ll. 7-67], [Col. 9, ll. 1-67], & [Col. 10, ll. 1-12]: provides the mechanism and describes the technique for adapting the effective comparison threshold (comparator’s operation point), the comparator uses a network of capacitors (C1, C2, C3, C4) to store the DC component of the input signal VC and the reference voltage Vref, during the comparison phase, the voltages on these capacitors are combined, setting the comparison threshold as a function of the stored input and reference voltages, Equations (7) and (8) show that the final compared voltages (V-/V+) are functions of both the input signal and the stored DC component/reference, meaning the threshold for comparison is adapted by the input). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the control circuit configured to adapt a value of the positive threshold voltage as a function of a value of the first voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (SC derivator) with a comparator and a control system that adapts operational parameters (DC bias voltages) based on a measured signal, where thresholds can be raised according to amplitude measurements but lacks detail on a control circuit continuously adapting the positive threshold voltage of a comparator as a precise mathematical function of the first voltage during standard operations. Matsuo provides a well-known circuit implementation for a voltage comparator where the threshold is dynamically set and adapted based on input voltages, where the dynamic threshold adaptation would improve comparator accuracy and stability. Utilizing a control scheme that extracts the DC component (Vc) of the analog input signal (the first voltage) and dynamically adapts the operation point (the threshold voltage) of the comparator as a direct mathematical function of that input voltage. The motivation to combine these teachings is to dynamically adjust the comparison threshold based on the input signal’s drift to prevent the operation point from fluctuation outside the comparator’s linear input range. The modification constitutes the application of a known technique to improve similar devices, leading to a derivative measurement circuit where a control circuit adapts to a positive threshold voltage as a function of a first voltage, stabilizing the analog-to-digital comparison operation regardless of variations in the input signal’s baseline voltage, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR). Regarding dependent claim 15, Aaltonen, teaches: The derivative measurement circuit according to claim 14 (Figs. 2 & 4-5; [0030]-[0031], [0036]-[0037], [0039], [0043]-[0044], [0048], & [0074]), Aaltonen, is silent in regard to: wherein the control circuit is configured to decrease the value of the positive threshold voltage when the first voltage is positive and increases. However, Matsuo, further teaches: wherein the control circuit is configured to decrease the value of the positive threshold voltage when the first voltage is positive and increases ([Col. 9, ll. 10-65]: discloses a control architecture where the operation point (the threshold voltage, Vs1) is actively calculated as a mathematical function of the DC component of the analog signal (Vc, corresponding to the first voltage). According to Matsuo’s equation, as the input voltage Vc becomes positive relative to the reference and increases, the subtracted term Cs(Vc-Vref)/(Cs + C1) becomes larger, inherently forcing the value of the threshold voltage Vs1 to decrease). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary combination to utilize Matsuo’s specific inverse-adaptive threshold calculation for the operational comparators. The combined measurement circuit discloses dynamically adapting threshold values but lacks configuring the control circuit to decrease the positive threshold voltage when the first voltage is positive and increases. Matsuo teaches a measurement circuit where the comparison operation point Vs1 (the threshold voltage) is calculated as Vref – Cs(Vc – Vref)/(Cs +C1), which inherently decreases the threshold as the DC component of the input signal Vc (the first voltage) becomes positive and increases relative to the reference. The motivation for this modification is to continuously correct the operation point of the amplifier during comparison to compensate for fluctuations in the DC component of the analog input signal. This represents the application of a known technique to improve similar devices, predictably keeping the differential amplifier within its optimal linear input range to maintain high precision even when the baseline input voltage drifts upward (KSR). Regarding dependent claim 16, Aaltonen, teaches: The derivative measurement circuit according to claim 13 (Figs. 2-3; [0028]-[0039], [0043]-[0044], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator, entire circuitry 20 constitutes a measurement and control circuit for MEMS resonator, includes the detection, amplification, and feedback loops that measure the resonator’s signal and derive control signals from it), wherein: Aaltonen, is silent in regard to: the measurement circuit comprises the second comparator; and the control circuit is configured to adapt a value of the negative threshold voltage as a function of a value of the first voltage. However, Matsuo, further teaches: the measurement circuit comprises the second comparator (Col. 1, ll. 24-44]: discloses a parallel measurement architecture containing a plurality of differential voltage comparators (COMP1 through COMP14); and the control circuit is configured to adapt a value of the negative threshold voltage as a function of a value of the first voltage ([Col. 3, ll. 22-41], [Col. 7, ll. 13-30], [Col. 10, ll. 1-22], [Col. 12, ll. 9-22], & [Col. 16, ll. 15-37]: provides a specific control topology where a secondary operation point (Vs2, corresponding to the negative threshold) dynamically adapts. This adaptation is calculated as a mathematical function of Vc, which is the extracted DC component of the analog input signal (the first voltage)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary combination to incorporate Matsuo’s secondary comparators and specific adaptive negative threshold calculation. The combined measurement circuit discloses a high-precision multi-capacitor system with dynamically adapting positive threshold voltages, but lacks detailing a second comparator where the control circuit adapts a negative threshold voltage as a mathematical function of the first voltage. Matsuo teaches a measurement circuit utilizing a plurality of comparators (e.g., COMP1 to COMP14) wherein a secondary operation point Vs2 (the negative threshold voltage) is actively adapted using the equation Vref + C1(Vc -Vref)/(C3+C1+C2) based on the input signal’s DC component Vc (the first voltage). The motivation for this modification is to continuously correct the secondary threshold boundaries during comparison to compensate for baseline fluctuations in the analog input signal. This represents the application of a known technique to improve similar devices by ensuring the differential amplifier remains within its optimal linear input range for accurate multi-level analog-to-digital conversion even as the baseline input voltage drifts (KSR). Regarding dependent claim 17, Aaltonen, teaches: The derivative measurement circuit according to claim 16 (Figs. 2-3; [0028]-[0039], [0043]-[0044], & [0074]), Aaltonen, is silent in regard to: wherein the control circuit is configured to decrease an absolute value of the negative threshold voltage when the first voltage is negative and decreases. However, Matsuo, further teaches: wherein the control circuit is configured to decrease an absolute value of the negative threshold voltage ([Col. 3, ll. 22-41], [Col. 7, ll. 13-30], [Col. 9, ll. 1-67], [Col. 10, ll. 1-67], [Col. 11, ll. 1-67], [Col. 12, ll. 1-65], & [Col. 16, ll. 15-37]: invention designed to compensate for fluctuations in the DC component VC of the input signal, where the purpose of the added capacitor elements (C1, C2, C3, C4) and switching network (switches 7, 8, 11, 12) is to adjust the effective threshold or operating point of the comparator to prevent errors, when the DC component VC changes, the circuit effectively “decreases the absolute value” of the impact the DC shift has on the comparator’s decision point/threshold) when the first voltage is negative and decreases (Fig. 9A; Col. 3, ll. 22-41], [Col. 7, ll. 13-30], [Col. 9, ll. 1-67], [Col. 10, ll. 1-67], [Col. 11, ll. 1-67], [Col. 12, ll. 1-65], & [Col. 16, ll. 15-37]: operates with a “first voltage” that can be negative and decrease, the input signals AIN and XAIN are differential (one is the inverse of the other), when one is positive, the other is negative, the circuit’s operation is designed to handle the scenario where these input voltages, and particularly their DC component VC, change, also provides an example that describes a condition where the input signal’s DC level is not at the expected midpoint, one side of the differential pair is at a more negative potential relative to the reference, and this “negative voltage” can “decrease” further, circuit is designed to compensate for this scenario). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary combination to utilize Matsuo’s specific adaptive negative threshold calculation. The combined measurement circuit discloses dynamically adapting threshold voltages but lacks configuring the control circuit to decrease an absolute value of the negative threshold voltage when the first voltage is negative and decreases. Matsuo teaches a measurement circuit where the secondary comparison operation point Vs2, corresponding to the negative threshold voltage, is calculated using the equation Vref + C1(Vc – Vref)/(C3+C1+C2), which inherently adapts and decreases the threshold’s absolute boundary as the DC component of the input signal Vc, corresponding to the first voltage, becomes negative and decreases relative to the reference. The motivation for this modification is to continuously correct the operation point of the amplifier during comparison to compensate for downward fluctuations in the DC component of the analog input signal. This represents the application of a known technique to improve similar devices, predictably keeping the differential amplifier within its optimal linear input range to maintain high precision even when the baseline input voltage drifts downward (KSR). Regarding independent claim 18, Aaltonen, teaches: A derivative measurement circuit (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal), comprising: a control circuit configured to (Figs. 2-3 & 5; [0030] & [0042]-[0043]: clock circuitry and controller function as a control circuit receiving a first clock (PLL reference) to generate derived secondary clock phases (C and XC) that implement successive sampling cycles): receive a first clock signal available at a third input of the measurement circuit (Figs. 2-3 & 5; [0030] &[0042]-[0043]: operation is controlled by clock signals C and XC, which are derived from a master clock signal synchronized with the resonator’s oscillation frequency f0, “The SC derivator circuit may be clocked at the same frequency as the input signal coming into the sampling amplifier from the HPF…”); implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal (Figs. 2-3 & 5; [0042]-[0043]: circuit operates in successive cycles corresponding to the sampling period of the input signal, each cycle involving two non-overlapping clock phases C and XC, which can be considered M=2 periods, and the “clock circuitry (23)” and “START UNIT (500)” generate and use clock signals (C, XC, CLK SIGNALS) to control the sampling amplifier switches in successive cycles and periods); and Aaltonen, is silent in regard to: M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential; However, Huang, further teaches: M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential (Fig. 1; [0021]-[0022] & [0026]: demonstrates an array of M capacitors (where M = N) with bottom terminals connected to reference potentials (VR/GND)); It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the derivator of Aaltonen with the M capacitive elements of Huang. It is known in the art from Aaltonen to utilize a switched capacitor derivator circuit with input capacitances to extract amplitude data. Aaltonen, however, does not detail M capacitive elements, where M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential. Huang teaches a sample and hold circuit comprising M capacitive elements, specifically capacitor array 140 with capacitors C1_1 to C1_N, each having a bottom electrode connected to a reference potential such as VR or GND. The motivation to combine these teachings would be to increase the charge storage capacity and enable multi-stage charge redistribution, which predictably improves signal amplification efficiency. This combination represents a substitution of single capacitors with a multi-capacitor array to yield the predictable variation of enhanced dynamic range in a switched-capacitor measurement circuit (KSR). Aaltonen, and Huang, are silent in regard to: M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first diode configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node; secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit; control the switches such that, at each period of each cycle: the first voltage is memorized on a respective one of the M capacitive elements; and the first input of the first circuit receives the first voltage memorized at a first instant on the respective one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant; However, Maurino, further teaches: M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first diode configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node (Fig. 4; [0003], [0032]-[0033], [0053]-[0054], & [0067]: teaches multiple primary switches (ps1/ps2) that directly connect to respective multi-sampling capacitors to the first node receiving the input voltage (Vin)); secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit (Fig. 4; [0034]-[0035], [0049], & [0055]-[0056]: uses secondary switches (p1/p2) to connect the capacitors to the amplifier’s input node (154) once sampling is complete); control the switches such that, at each period of each cycle: the first voltage is memorized on a respective one of the M capacitive elements ([0018], [0032], & [0053]: switches are controlled such that the respective capacitors accumulate and hold (memorize) the input voltage during their specific clock period); and the first input of the first circuit receives the first voltage memorized at a first instant on the respective one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant ([0018], [0034]-[0035], [0051], [0055]-[0056], [0061], [0109], & [Claim 19]: topology systematically feeds the voltages sampled at different time instants (e.g., T1 vs. T2) into the differential inputs of the amplifier during separate phases); It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined circuit of Aaltonen and Huang to include the primary and secondary switching topology of Maurino. The combination of Aaltonen and Huang discloses a derivator with M capacitive elements but lacks M primary switches coupling the elements to a first node, secondary switches coupling the elements to a first circuit, and controlling the switches to memorize voltages at distinct instants. Maurino teaches M primary switches ps1 and ps2 coupling a second terminal of M capacitive elements C1 and C2 to a first node 152 receiving a first voltage Vin. Maurino further teaches secondary switches p1 and p2 coupling the capacitive elements to the input 154 of a first circuit amplifier 120 and controlling the switches such that the first voltage is memorized and the first circuit receives the memorized voltage at different instants T1 through T4. The motivation would be to decouple the charging and discharging phases of the M capacitive elements to maintain a short, consistent time delay between sampling intervals. This modification constitutes the use of a known technique to improve similar devices by predictably rejecting flicker noise and reducing jitter in the sampling phases (KSR). Aaltonen, Huang, and Maurino, are silent in regard to: a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between the first and second inputs of the first circuit; a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage; and a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage. However, Matsuo, further teaches: a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between the first and second inputs of the first circuit (Fig. 7; [Col. 1, ll. 11-44 & 63-67], [Col. 2, ll. 23-31], [Col. 3, ll. 7-21, 42-53, & 62-67], [Col. 4, ll. 1-44], [Col. 6, ll. 1-63], [Col. 7, ll. 13-30], [Col. 14, ll. 10-18], [Col. 15, ll. 59-67], [Col. 16, ll. 1-7 & 15-37], [Claim 1], & [Claim 12]: provides the core difference amplifier (first circuit) that processes the sampled inputs and outputs the resultant voltage difference); a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 11-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 16, Claim 1, ll. 50-67], [Col. 17, Claim 1, ll. 1-37]: describes a voltage comparator circuit that compares an input voltage to a reference voltage (“positive threshold”) and provides a binary output signal (D/XD), Fig. 7 details the circuitry to achieve this, the operational amplifier 10 can be considered a comparator, or its output is latched by latch circuit 20 to produce a binary output D/XD, discloses using a comparator (COMP1) to evaluate the computed difference voltage against a reference threshold voltage to generate a binary signal output signal (D) indicative of whether the threshold is met); and a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 7-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 20, Claim 12, ll. 13-67], [Col. 21, ll.1-11], & [Col. 22, ll. 1-10]: describes a parallel ADC with multiple comparators COMP1 to COMP14, each receiving different reference threshold voltage pairs (VRTn/VRBn), to evaluate the same differential signal against a descending scale of positive and negative threshold voltages to generate a set of output binary signals, conventional to use multiple comparators, each set to a different threshold (e.g., a positive and a negative one in a window comparator configuration), teaches using multiple comparators with different thresholds). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Matsuo’s difference amplifier and parallel comparators into the modified primary device in place of a standard comparator. The preceding combination discloses a multi-capacitor switching topology but does not detail a first circuit configured to deliver a voltage difference, a first comparator, and a second comparator, configured to compare the voltage against threshold voltages to provide binary signals. Matsuo teaches a first circuit, specifically an operational amplifier 10, delivering an output indicating a voltage difference, and a plurality of comparators (COMP1 to COMP14) configured to compare this differential voltage against reference threshold voltages to provide binary output signals D and DX. Matsuo’s operational amplifier 10 is configured to amplify the differential voltage and deliver a second voltage comprising output signal D and inverted signal XD indicating the voltage difference. The motivation for this incorporation is to accurately compute the differential voltage across the sampled instants and reliably digitize the resulting analog difference into a binary format suitable for downstream processing, while preventing the operation point from fluctuating outside the input range. This represents a application of a known technique to improve similar devices, predictably enabling high-speed parallel analog-to-digital conversion without increasing the complexity of the core active circuitry and the predictable variation of stabilized voltage comparison without increasing circuit size (KSR). Regarding dependent claim 19, Aaltonen, teaches: The derivative measurement circuit according to claim 18 (Fig. 3; [0031] & [0043]), Aaltonen, is silent in regard to: wherein the control circuit is configured to: adapt a value of the positive threshold voltage as a function of a value of the first voltage; and adapt a value of the negative threshold as a function of a value of the first voltage. However, Matsuo, further teaches: wherein the control circuit is configured to ([Col. 3, ll. 22-41], [Col. 7, ll. 13-30], [Col. 9, ll. 10-65], [Col. 10, ll. 1-52], [Col. 12, ll. 9-22], & [Col. 16, ll. 15-37]): adapt a value of the positive threshold voltage as a function of a value of the first voltage ([Abstract], [Col. 3, ll. 22-41], [Col. 7, ll. 13-30], [Col. 8, ll. 7-67], [Col. 9, ll. 1-67], [Col. 10, ll. 1-52], [Col. 12, ll. 9-22], & [Col. 16, ll. 15-37]: discloses a control architecture where a primary operation point (Vs1, corresponding to the positive threshold voltage) dynamically adapts. This adaptation is calculated as a mathematical function of the DC component of the analog input signal (VC, the first voltage)); and adapt a value of the negative threshold as a function of a value of the first voltage ([Col. 3, ll. 22-41], [Col. 7, ll. 13-30], [Col. 9, ll. 10-65], [Col. 10, ll. 1-52], [Col. 12, ll. 9-22], & [Col. 16, ll. 15-37]: further provides that a secondary operation point (Vs2, corresponding to the negative threshold voltage) also dynamically adapts. This secondary adaptation is similarly calculated as a distinct mathematical function of the exact same input signal’s DC component (Vc, the first voltage)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary combination to utilize Matsuo’s specific dual-adaptive threshold calculations. The combined measurement circuit discloses a high-precision multi-capacitor system but lacks configuring the control circuit to simultaneously adapt both a positive and negative threshold voltage as a mathematical function of the first voltage. Matsuo taches a measurement circuit where the primary and secondary comparison operation points, corresponding to positive and negative threshold voltages, are dynamically calculated as Vs1 = Vref – Cs(Vc – Vref)/(Cs + C1) and Vs2 = Vref + C1(Vc -Vref)/(C3+C1+C2), adapting directly as functions of the input signal’s DC component Vc, which corresponds to the first voltage. The motivation for this modification is to continuously correct the upper and lower operation boundaries of the amplifier during comparison to predictably compensate for baseline fluctuations in the analog input signal. This represents the application of a known technique to improve similar devices, ensuring the differential amplifier remains within its optimal linear input range for accurate analog-to-digital conversion even as the baseline input voltage drifts (KSR). Claims 2 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Aaltonen, in view of Huang, in view of Maurino, in view of Matsuo, in view of Hughes (US 5179301, Pat. Date Jan. 12, 1993, hereinafter, Hughes), and further in view of Hurwitz et al. (US 2019/0081601 A1, Pub. Date Mar. 14, 2019, hereinafter, Hurwitz) . Regarding dependent claim 2, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein: Aaltonen, is silent in regard to: M is equal to 1 and there is 1 secondary switch; the first input of the first circuit is coupled to the first node; and the control circuit is configured to control the switches such that, at each period of each cycle, the second input of the first circuit receives the voltage memorized on the one capacitive element at this period. However, Hurwitz, further teaches: M is equal to 1 and there is 1 secondary switch (Fig. 5; [0057]: teaches a discrete single-capacitor (M=1) sampling structure utilizing exactly one sampling switch (transistor 82) and one holding capacitor (Chold 88)); the first input of the first circuit is coupled to the first node (Fig. 21; [0110]: teaches directly routing the live signal node (node 610, acting as the first node) straight to the first input of the measurement circuit (620) without intermediate buffering); and The Examiner is combining Aaltonen and Hurwitz in view of Hughes, by implementing the operational logic of Hughes for differentiation by comparing a live continuous sample against a delayed (memorized) sample (Figs. 2-3; [Abstract], [Col. 1, ll. 36-49], [Col. 4, ll. 6-17 & 52-68], [Col. 8, ll. 42-52], [Col. 9, ll. 59-66], [Col. 11, ll. 40-49], [Col. 14, ll. 37-65], [Col. 16, ll. 38-54], [Col. 17, ll. 53-68], [Claim 1], & [Claim 2]). PNG media_image5.png 566 647 media_image5.png Greyscale PNG media_image6.png 399 605 media_image6.png Greyscale the control circuit is configured to control the switches such that, at each period of each cycle, the second input of the first circuit receives the voltage memorized on the one capacitive element at this period (Fig. 21; [0110]: provides the matching structural routing, showing the measurement capacitor (608) feeding its stored/memorized state into the second input (node 612) of the measurement circuit). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s derivator to utilize the single-delay subtraction logic of Hughes, implemented via the direct-coupling measurement routing and single-capacitor structure of Hurwitz. Aaltonen teaches a switched-capacitor derivator but lacks a single-element (M=1) subtraction topology with one secondary switch where the live input is directly coupled to the first node of the amplifier. Hughes teaches the operational logic for a single-delay derivative measurement by subtracting a memorized sample from a live continuous sample. Hurwitz provides the necessary physical routing architecture for this logic, disclosing an M=1 track-and-hold circuit with one switch 82, wherein a live signal node 610 connects directly to a first input of a measurement circuit 620, while the stored voltage from a measurement capacitor 608 feeds into the second input at node 612. The motivation is to simplify the overall circuit architecture and reduce the active component footprint by eliminating redundant parallel sampling branches, instead using a single storage element to hold the prior sample for direct differential comparison against the live input. This represents the simple substitution of a multi-phase sampling network with a single-capacitor delay-and-compare architecture to yield the predictable variation of a compact derivative measurement circuit (KSR). Regarding dependent claim 12, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0031], [0043]-[0044], & [0059]: figure illustrates the switched capacitor derivator circuit, which performs a derivative function to extract amplitude), Aaltonen, is silent in regard to: wherein the measurement circuit further comprises a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit. However, Hurwitz, further teaches: wherein the measurement circuit further comprises a second circuit coupling the second input of the measurement circuit with the first node (Fig. 12; [0092]: teaches a measurement circuit utilizing a second supplementary circuit to actively couple an input signal (from generator 170) to a specific node (node 312) in the measurement path), wherein the second circuit is a buffer circuit (Fig. 12; [0092]: identifies this second coupling circuit as a buffer circuit, specifically implemented as an operational amplifier 306). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the measurement circuit of Aaltonen to incorporate the buffer circuit coupling the input to the first node as taught by Hurwitz. Aaltonen teaches a derivative measurement circuit but doe not detail a second circuit coupling a second input to the first node, wherein the second circuit is a buffer circuit. Hurwitz teaches a differential measurement circuit that comprises a second circuit coupling an input of the measurement circuit with a specific circuit node, wherein the second circuit is a buffer circuit, such as an operational amplifier 306 coupling a stimulus generator 170 to a node. The motivation for this modification is to maintain signal integrity and prevent the measurement node from drawing excessive current from the input signal source. This represents the application of a known technique to improve similar devices, predictably providing isolation and impedance matching between the input source and the sampling nodes to ensure accurate voltage measurements (KSR). Claims 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Aaltonen, in view of Huang, in view of Maurino, in view of Matsuo, in view of Parupalli et al. (US 2024/0187016 A1, Fil. Date Jan. 18, 2023, hereinafter, Parupalli), in view of Quiquempoix et al. (US 2011/0163901 A1, Pub. Date Jul. 7, 2011, hereinafter, Quiquempoix), and further in view of Han et al. (US 2012/0229204 A1, Pub. Date Sep. 13, 2012, hereinafter, Han). Regarding dependent claim 4, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein: Aaltonen, is silent in regard to: M is equal to 3 and there are 6 secondary switches; and However, Parupalli, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, and Matsuo in view of Parupalli and Quiquempoix, by implementing the parallel stages where each stage uses exactly two secondary switches (109a/109b) to connect to the amplifier 140, scaling this to M = 3 provides exactly 6 secondary switches of Quiquempoix (Fig. 3A; [0043]) M is equal to 3 and there are 6 secondary switches (Fig. 3; [0029]: explicitly provides an array restricted to exactly three main capacitors, establishing M = 3); and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s derivator to incorporate the exactly three-capacitor architecture of Parupalli. It is known in the art from Aaltonen to utilize a switched capacitor circuit for amplitude extraction. Aaltonen, however, does not detail an architecture restricted to exactly M=3 capacitive elements. Parupalli teaches a switched capacitor network comprising exactly three sampling capacitors 312A, 312B, and 312C coupled to distinct sub-DACs. The motivation for this modification is to partition the sampling workload across multiple dedicated capacitors to maximize inter-channel isolation to provide additional time for the input to settle. This modification represents a substitution of a single capacitor with a multi-capacitor array to yield the predictable variation of improved analog front-end settling performance in a measurement circuit (KSR). Aaltonen, and Parupalli, are silent in regard to: the control circuit is configured to control the switches such that, at each cycle: that of the M capacitive elements on which the first voltage is memorized is different at each period of the cycle, and However, Quiquempoix, further teaches: the control circuit is configured to control the switches such that, at each cycle: that of the M capacitive elements on which the first voltage is memorized is different at each period of the cycle ([0043] & [0046]-[0047]: the switching control unit 110 cyclically shifts the functional assigned of the parallel capacitors at each period (sample) so the specific element actively memorizing the input voltage constantly rotates), and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined circuit to include the six secondary switches and the rotational switching algorithm of Quiquempoix. The combination of Aaltonen and Parupalli discloses an M=3 capacitor arrangement, it does not detail scaling to exactly 6 secondary switches nor controlling the switches such that the memorizing element is different at each period. Quiquempoix teaches N parallel input stages, each having two secondary switches 109a and 109b (yielding exactly 6 switches for N=3), and a switching control unit 110 that rotates the functional assignment of the capacitors at each sample period so the memorizing element cyclically changes. The motivation is to average out mismatch errors between the unit capacitors and continuously cancel gain errors on-the-fly without requiring additional sampling time. This modification constitutes the use of a known technique to improve similar devices by predictably rotating capacitive assignments to achieve high-precision error-free charge transfers across consecutive periods (KSR). Aaltonen, Parupalli, and Quiquempoix, are silent in regard to: at each period of the cycle, the first input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the second input of the first circuit receives a voltage across another of the M capacitive elements other than the one on which the memorization is done at this period. However, Han, further teaches: at each period of the cycle, the first input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the second input of the first circuit receives a voltage across another of the M capacitive elements other than the one on which the memorization is done at this period (Fig. 2; [0006], [0017], [0029]-[0031], [0033]-[0034], [0038], [0043]-[0045], [0050]-[0052], [Claim 2], & [Claim 13]: teaches the simultaneous differential routing architecture where distinct, parallel holding capacitors (C1A/C1B) are actively connected to the first and second inputs (N3A/N3B) of the amplifier). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Han’s fully differential input routing architecture into the modified primary device to simultaneously process the voltages from the two holding capacitors while the third memorizes. The preceding combination discloses a rotating three-capacitor topology but does not detail routing voltages from the two non-memorizing capacitors simultaneously to the first and second inputs of the first circuit. Han teaches a switched capacitor circuit that simultaneously routes sampled voltages from distinct parallel holding capacitors C1A and C1B via switches 4A and S4B into the fully differential first and second inputs N3A and N3B of an amplifier 240. The motivation for this incorporation is to accurately compute the differential voltage across the distinct sampled instants while removing offset and amplification noise from the high-gain amplifier. This represents the application of a known technique to predictably allow the first circuit to directly process the voltage difference between alternating historical samples for stabilized high-precision measurement (KSR). Regarding dependent claim 5, Aaltonen, teaches: The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein: Aaltonen, is silent in regard to: M is equal to 3; each cycle corresponds to a succession of first, second and third periods of the second clock signal; and However, Parupalli, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, and Matsuo in view of Parupalli and Quiquempoix, by implementing periods of succession of Quiquempoix (Fig. 3A; [0043]) M is equal to 3 (Fig. 3; [0029]: explicitly provides an array restricted to exactly three main capacitors, establishing M = 3); each cycle corresponds to a succession of first, second and third periods of the second clock signal (Fig. 3; [0028]-[0029]: initial semiconductor logic and clock parameters are validated through Parupalli’s 3-capacitor array and Quiquempoix’s period succession); and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary circuit to include this three-element architecture to partition the sampling workload and maximize inter-channel isolation in electronics. Initial baseline logic and parameters are validated through Aaltonen’s derivator. Parupalli discloses the limitation wherein the measurement circuit utilizes exactly three sampling capacitors 312A, 312B, and 312C, establishing M is equal to 3. This represents a substitution of a single capacitor with a multi-capacitor array to yield the predictable variation of improved analog front-end settling performance (KSR). Aaltonen, and Parupalli, are silent in regard to: the control circuit is configured to control the switches such that: at each first period, the first voltage is memorized on a first element and the first and second inputs of the first circuit receive voltages of third and second elements, respectively, at each second period, the first voltage is memorized on the second element and the first and second inputs of the first circuit receive voltages of the first and third elements, respectively, and However, Quiquempoix, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, Matsuo, and Parupalli in view of Quiquempoix and Han, by implementing the two non-memorizing capacitors (C1A/C1B) that are connected between a first pair of nodes (N1A and N1B) and a second pair of nodes (N2A and N2B) within the sampling unit 210, routing them into the fully differential first and second inputs of the amplifier simultaneously of Han (Fig. 2; [0033]-[0034]). the control circuit is configured to control the switches such that ([0046]: standard rotational processing applied): at each first period, the first voltage is memorized on a first element and the first and second inputs of the first circuit receive voltages of third and second elements, respectively ([Abstract], [0003]-[0012], [0014], [0017]-[0023], [0026]-[0035], [0038]-[0048], [0050]-[0052], [0054]-[0058], [0060]-[0071], [0073]-[0079], [0082]-[0083], [0085], [0087], [Claim 1], [Claim 6], [Claim 8], [Claim 9], [Claim 11], [Claim 12], [Claim 15], [Claim 19], [Claim 20], [Claim 21], [Claim 23], & [Claim 25]: teaches a switching control unit that cyclically rotates assignments across N parallel input stages at each sample period providing the exact structural logic for the 1st, 2nd, and 3rd period rotation), at each second period, the first voltage is memorized on the second element and the first and second inputs of the first circuit receive voltages of the first and third elements, respectively ([Abstract], [0003]-[0012], [0014], [0017]-[0023], [0026]-[0035], [0038]-[0048], [0050]-[0052], [0054]-[0058], [0060]-[0071], [0073]-[0079], [0082]-[0083], [0085], [0087], [Claim 1], [Claim 6], [Claim 8], [Claim 9], [Claim 11], [Claim 12], [Claim 15], [Claim 19], [Claim 20], [Claim 21], [Claim 23], & [Claim 25]), and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine this rotational switching algorithm with the three-capacitor network to average out mismatch errors between unit capacitors on-the-fly without requiring additional sampling time. The established multi-capacitor context is further modified by Quiquempoix to address the succession of first, second, and third periods of the second clock signal. Quiquempoix discloses a control circuit 110 configured to control the switches such that the specific element on which the first voltage is memorized cyclically rotates and is different at each period of the cycle. This modification constitutes the use of a known technique to improve similar devices by predictably rotating capacitive assignments to achieve high-precision charge transfers across consecutive periods (KSR). Aaltonen, Parupalli, and Quiquempoix, are silent in regard to: at each third period, the first voltage is memorized on the third element and the first and second inputs of the first circuit receive voltages of the second and first elements, respectively. However, Han, further teaches: at each third period, the first voltage is memorized on the third element and the first and second inputs of the first circuit receive voltages of the second and first elements, respectively (Fig. 2; [0006], [0017], [0029]-[0031], [0033]-[0034], [0038], [0043]-[0045], [0050]-[0052], [Claim 2], & [Claim 13]: fully differential input routing is applied to Quiquempoix’s N=3 cyclic assignment, routing the two holding capacitors to the operational amplifier while the third element memorizes the current signal). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Han’s fully differential input routing to the 3-phase cyclic assignment to simultaneously process the historical holding voltages while the third element memorizes the current signal. Bypassing intermediate signal transitions, the final 3-phase transformation relies on Han to achieve the differential routing. Han discloses the first and second inputs N3A and N3B of the first circuit receive voltages of the other two elements (C1A/C1B) not currently memorizing the signal during each respective period. This combination computes the differential voltage across the distinct sampled instants while removing offset and amplification noise from the high-gain amplifier. Implementing this routing represents the application of a known technique to predictably allow the first circuit to process the voltage difference between alternating historical samples for stabilized high-precision semiconductor measurement (KSR). Regarding dependent claim 6, Aaltonen, teaches: The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), Aaltonen, is silent in regard to: wherein the primary switches comprise a first primary switch configured to couple the second terminal of the first element with the first node, a second primary switch configured to couple the second terminal of the second element with the first node, and a third primary switch configured to couple the second terminal of the third element with the first node. However, Quiquempoix, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, and Matsuo, in view of Parupalli and Quiquempoix, by implementing Parupalli’s exact three-capacitor architecture (M=3), the parallel configuration inherently dictates the presence of a first, second, and third primary switch to individually couple the three respective capacitive elements to the input node during the sampling phase (Fig. 3; [0028]-[0029]). wherein the primary switches comprise a first primary switch configured to couple the second terminal of the first element with the first node, a second primary switch configured to couple the second terminal of the second element with the first node, and a third primary switch configured to couple the second terminal of the third element with the first node (Fig. 4; [0052]-[0060]: discloses parallel input stages where each individual stage utilizes a dedicated primary sampling switch (switch 220a) to connect to the first input node (VINP) to the respective capacitive element (capacitor 104a) which is applied to the exact three-capacitor architecture (M=3) taught by Parapulli). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s circuit by incorporating Parupalli’s three-capacitor architecture and Quiquempoix’s parallel switching to provide a first, second, and third primary switch respectively configured to couple the second terminal of the first, second, and third elements with the first node. Aaltonen teaches a switched capacitor measurement circuit but lacks a configuration utilizing exactly three distinct capacitive elements each coupled to an input node via dedicated primary switches. Parupalli teaches a switched capacitor network comprising exactly three capacitors 312A, 312B, 312C acting as the first, second, and third elements, while Quiquempoix teaches utilizing a dedicated primary sampling switch 220a for each parallel capacitor stage to couple the first input node VINP to its respective capacitor 104a. The motivation to combine these teachings is to partition the sampling workload across multiple dedicated capacitors to maximize inter-channel isolation and to enable independent sampling of the input voltage for each state to prevent short circuits between analog inputs during continuous operation. This modification constitutes the substitution of known multi-capacitor arrays and switching topologies to yield the predictable variation of improved analog front-end settling performance and accurate charge transfers (KSR). Regarding dependent claim 7, Aaltonen, teaches: The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), Aaltonen, is silent in regard to: wherein the control circuit is configured to: at each first period, keep open the second and third primary switches and switch the first primary switch to an ON state; at each second period, keep open the third and first primary switches and switch the second primary switch to the ON state; and at each third period, keep open the second and first primary switches and switch the third primary switch to the ON state. However, Quiquempoix, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, and Matsuo, in view of Parupalli and Quiquempoix, by implementing Parupalli’s exact three-capacitor architecture (M=3), during the first period when the capacitor is assigned to sample the input, its primary switch turns ON while the control circuit actively keeps the switches for the second and third capacitors OFF (open) (Fig. 3; [0028]-[0031] & [0035]-[0041]). wherein the control circuit is configured to (0046], [0052]-[0054], & [0056]): at each first period, keep open the second and third primary switches and switch the first primary switch to an ON state ([0046], [0052]-[0053], & [0056]: discloses a control circuit that rotates assignments and strictly enforces a mutually exclusive switching state to avoid short circuits, which is applied to the three capacitors (M=3) of Parupalli); at each second period, keep open the third and first primary switches and switch the second primary switch to the ON state ([0046], [0052]-[0054], & [0056]: as the control circuit cyclically advances to the second period, the sampling assignment rotates to the second element. Consequently the second primary switch turns ON, and the mutually exclusive logic forces the first and third primary switches to remain open); and at each third period, keep open the second and first primary switches and switch the third primary switch to the ON state ([0046], [0052]-[0054], & [0056]: as the cycle advances to the third period, the rotational algorithm assigns the input sampling task to the third element. The third primary switch turns ON, and the control circuit dictates that the first and second primary switches are kept open to maintain channel isolation). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s circuit by incorporating Parupalli’s three-capacitor architecture and Quiquempoix’s rotational switching to configure the control circuit to sequentially switch the first, second, and third primary switches to an ON state during their respective first, second, and third periods while keeping the other two primary switches open. Aaltonen teaches a switched capacitor measurement circuit but lacks a configuration utilizing exactly three distinct capacitive elements sequentially coupled to an input node via mutually exclusive primary switches. Parupalli teaches a switched capacitor network comprising exactly three capacitors 312A, 312B, and 312C, establishing the first, second, and third elements, while Quiquempoix teaches utilizing a dedicated primary sampling switch 220a for each parallel stage and a control circuit 110 that rotates assignments such that when one switch is ON, all others are OFF to isolate the inputs. The motivation to combine these teachings is to safely partition the sampling workload across multiple dedicated capacitors over successive cycles while preventing short circuits between parallel analog inputs. This modification constitutes the substitution of known multi-capacitor arrays and switching topologies to yield the predictable variation of isolated accurate charge transfers across rotating sampling phases (KSR). Regarding dependent claim 8, Aaltonen, teaches: The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), Aaltonen, is silent in regard to: wherein each memorization of the first voltage on each capacitive element has a same duration, for example less than or equal to one period of the second clock signal, preferably equal to half a period of the second clock signal. However, Quiquempoix, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, and Matsuo, in view of Quiquempoix, by implementing Matsuo’s driving the sampling and holding operations utilizing a clock signal (SCK) with a symmetrical 50% duty cycle, meaning the memorization duration perfectly equals half a period of the second clock signal (Figs. 4 & 9; [Col. 2, ll. 16-67], [Col. 3, ll. 1-20], [Col. 8, ll. 49-67], [Col. 9, ll. 1-67], & [Col. 10, ll. 1-54]). wherein each memorization of the first voltage on each capacitive element has a same duration, for example less than or equal to one period of the second clock signal, preferably equal to half a period of the second clock signal ([0007], [0032]-[0033], [0042], [0060], & [0082]: discloses that the phases for sampling have the same duration across the array and are specifically equal to one half of the clock’s sample period, and further reinforced by Matsuo). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-capacitor circuit of Aaltonen and Parupalli to include the uniform, half-period memorization durations taught by Quiquiempoix. Aaltonen teaches a switched capacitor measurement circuit but lacks configuring the control circuit such that each memorization on the capacitive elements has a same duration equal to half a clock period. Quiquempoix teaches controlling a switched capacitor network utilizing uniform sampling phases and discloses that each phase timing is typically equal to one half of the sample period. The motivation to do so is to provide sufficient and equal settling time for each parallel capacitor stage while reserving the remaining half of the cycle for the subsequent charge transfer phase. This modification constitutes the use of a known technique to improve similar devices by predictably establishing symmetrical clock phases to ensure accurate balanced charge acquisition across all rotating capacitors (KSR). Regarding dependent claim 9, Aaltonen, teaches: The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), Aaltonen, is silent in regard to: wherein the second switches comprise: first and second secondary switches configured to couple the second terminal of the first element respectively with the first and second inputs of the first circuit; third and fourth secondary switches configured to couple the second terminal of the second element respectively with the first and second inputs of the first circuit; and fifth and sixth secondary switches configured to couple the second terminal of the third element respectively with the first and second inputs of the first circuit. However, Han, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, Matsuo, and Han in view of Parupalli, by implementing Parupalli’s first capacitive element of the array, providing the first and secondary switches routing the element to both amplifier inputs (Fig. 3; [Abstract], [0007]-[0011], [0028]-[0031], [0033]-[0043], [Claim 1], [Claim 2], [Claim 3], [Claim 5], [Claim 6], [Claim 7], [Claim 9], [Claim 10], [Claim 11], [Claim 13], [Claim 14], [Claim 15], [Claim 17], [Claim 18], [Claim 19], [Claim 20], [Claim 21], & [Claim 22]). wherein the second switches comprise (Fig. 4; [0006], [0009], [0011], [0017]-[0018], [0039], [0042]-[0044], [0046]-[0047], [Claim 2], [Claim 5], [Claim 7], [Claim 13], & [Claim 14]): first and second secondary switches configured to couple the second terminal of the first element respectively with the first and second inputs of the first circuit (Fig. 4; [0006], [0009], [0011], [0017]-[0018], [0039], [0042]-[0044], [0046]-[0047], [Claim 2], [Claim 5], [Claim 7], [Claim 13], & [Claim 14]: teaches configuring secondary switches such that the output node of a single capacitive element (C3A) is coupled to both the first and second differential inputs of the amplifier via a cross-coupled switch pair (SCH1A and SCH2A). Applied to the first capacitive element of Parupalli’s array); The Examiner is combining Aaltonen, Huang, Maurino, Matsuo, and Han in view of Parupalli, by implementing Parupalli’s M=3 array that directly yields the third and fourth secondary switches coupling the second element of the first and second inputs of the amplifier (Fig. 3; [Abstract], [0007]-[0011], [0028]-[0031], [0033]-[0043], [Claim 1], [Claim 2], [Claim 3], [Claim 5], [Claim 6], [Claim 7], [Claim 9], [Claim 10], [Claim 11], [Claim 13], [Claim 14], [Claim 15], [Claim 17], [Claim 18], [Claim 19], [Claim 20], [Claim 21], & [Claim 22]). third and fourth secondary switches configured to couple the second terminal of the second element respectively with the first and second inputs of the first circuit (Fig. 4; [0006], [0009], [0011], [0017]-[0018], [0039], [0042]-[0044], [0046]-[0047], [Claim 2], [Claim 5], [Claim 7], [Claim 13], & [Claim 14]: scaling Han’s chopper stabilization cross-coupling to the second capacitive element of Parupalli’s M=3 array directly yields the third and fourth secondary switches coupling the second element to the first and second inputs of the amplifier); and The Examiner is combining Aaltonen, Huang, Maurino, Matsuo, and Han in view of Parupalli, by implementing Parupalli’s M=3 array that directly yields the fifth and sixth secondary switches coupling the third element to both amplifier inputs (Fig. 3; [Abstract], [0007]-[0011], [0028]-[0031], [0033]-[0043], [Claim 1], [Claim 2], [Claim 3], [Claim 5], [Claim 6], [Claim 7], [Claim 9], [Claim 10], [Claim 11], [Claim 13], [Claim 14], [Claim 15], [Claim 17], [Claim 18], [Claim 19], [Claim 20], [Claim 21], & [Claim 22]). fifth and sixth secondary switches configured to couple the second terminal of the third element respectively with the first and second inputs of the first circuit (Fig. 4; [0006], [0009], [0011], [0017]-[0018], [0039], [0042]-[0044], [0046]-[0047], [Claim 2], [Claim 5], [Claim 7], [Claim 13], & [Claim 14]: applying the exact same fully differential chopper routing from Han to the third capacitive element of the M=3 array results in the fifth and sixth secondary switches coupling the third element to both amplifier inputs). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s circuit by incorporating Parupalli’s three- capacitor architecture with Han’s dual switch routing to provide first and secondary switches for the first element, third and fourth secondary switches for the second element, and fifth and sixth secondary switches for the third element, with each pair configured to couple the second terminal of its respective element to the first and second inputs of the first circuit. Aaltonen teaches a switched capacitor measurement circuit but lacks a configuration utilizing exactly three distinct capacitive elements where each element’s second terminal is cross-coupled to both the first and second inputs of the first circuit via pairs of secondary switches. Parupalli teaches a switched capacitor network comprising exactly three capacitors (312A, 312B, and 312C), establishing the first, second, and third elements, while Han teaches a chopper stabilization circuit featuring dual secondary switches (e.g., SCH1A and SCH2A) that couple the output node of a sampling capacitor respectively to both the first and second differential inputs of an amplifier. The motivation to combine these teaches is to partition the sampling workload across multiple dedicated capacitors to maximize inter-channel isolation, and to enable chopper stabilization at the amplifier inputs to remove offset voltages and low-frequency flicker noise during signal integration. This modification constitutes the substitution of a single capacitor with a multi-capacitor array and the use of a known technique to improve similar devices by predictably converting unnecessary DC offset signals into AC signals to prevent amplification noise in high-gain measurement circuits (KSR). Regarding dependent claim 10, Aaltonen, teaches: The derivative measurement circuit according to claim 9 (Fig. 3; [0031]-[0032] & [0043]), Aaltonen, is silent in regard to: wherein the control circuit is configured to: at each first period, switch the fifth and fourth secondary switches to an ON state and keep open the other secondary switches; at each second period, switch the first and sixth secondary switches to the ON state and keep open the other secondary switches; and at each third period, switch the third and second secondary switches to the ON state and keep open the other secondary switches. However, Quiquempoix, further teaches: The Examiner is combining Aaltonen, Huang, Maurino, and Matsuo, in view of Han and Quiquempoix, by implementing Han’s secondary switches necessary to route holding capacitors to specific differential outputs (Fig. 4; [0006], [0017], [0029]-[0031], [0033]-[0034], [0038], [0043]-[0045], & [0050]-[0052]). wherein the control circuit is configured to ([0009]-[0010], [0012], [0040]-[0041], [0043], [0046], [0051]-[0053], [0056]-[0057], [0061], [0070], [0072], [0077], & [0082]): at each first period, switch the fifth and fourth secondary switches to an ON state and keep open the other secondary switches ([0052]-[0053]: provides the mutually exclusive control logic, applying this to a 3-capacitor array, during the first period when the first element memorizes, the fifth switch (routing the third element) and fourth switch (routing the second element) are switched ON, while Quiquempoix’s logic keeps all other secondary switches OFF (open)); at each second period, switch the first and sixth secondary switches to the ON state and keep open the other secondary switches ([0052]-[0053]: as the cycle rotates to the second period, the second element memorizes. The control circuit actively switches the first secondary switch (routing the first element) and the sixth secondary switch (routing the third element) to the ON state to drive the amplifier, while maintaining the explicit rule to keep all other secondary switches open to isolate the channels); and at each third period, switch the third and second secondary switches to the ON state and keep open the other secondary switches ([0052]-[0053]: in the final third period, the third element memorizes. The control circuit rotates to switch the third secondary switch (routing the second element) and second secondary switch (routing the first element) to the ON state. The control circuit concurrently keeps all other secondary switches open to prevent signal collision). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aaltonen’s circuit by incorporating Parupalli’s three-capacitor architecture, Han’s differential switch routing, and Quiquempoix’s mutually exclusive rotationally control logic to configure the control circuit to sequentially switch the 5th/4th, 1st/6th, and 3rd/2nd secondary switches ON during their respective first, second, and third periods while keeping the other secondary switches open. Aaltonen teaches a switched capacitor measurement circuit but lacks exactly three capacitive elements with cross-coupled secondary switches controlled to cyclically alternate specific ON/OFF differential pairings at each period. Parupalli teaches an array of exactly three capacitors (312A, 312B, and 312C) establishing the first, second, and third elements, Han teaches cross-coupled secondary switches (SCH1A/SCH2A) coupling capacitors to both differential inputs of an amplifier, and Quiquempoix teaches a rotational control circuit 110 that ensures when specific switches are ON, all other switches are strictly kept OFF to isolate channels. The motivation to combine these teachings is to safely process alternating differential historical samples from multiple dedicated holding capacitors while preventing short circuits between parallel analog inputs during continuous high-gain integration. This modification constitutes the substitution of known multi-capacitor arrays and switching topologies to yield the predictable variation of isolated accurate differential charge transfers across rotating sampling phases (KSR). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Aaltonen, in view of Huang, in view of Maurino, in view of Matsuo, and further in view of Hurwitz. Regarding independent claim 20, Aaltonen, teaches: A derivative measurement circuit (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal), comprising: a control circuit configured to (Figs. 2-3 & 5; [0030] & [0042]-[0043]: clock circuitry and controller function as a control circuit receiving a first clock (PLL reference) to generate derived secondary clock phases (C and XC) that implement successive sampling cycles): receive a first clock signal available at a third input of the measurement circuit (Figs. 2-3 & 5; [0030] &[0042]-[0043]: operation is controlled by clock signals C and XC, which are derived from a master clock signal synchronized with the resonator’s oscillation frequency f0, “The SC derivator circuit may be clocked at the same frequency as the input signal coming into the sampling amplifier from the HPF…”); implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal (Figs. 2-3 & 5; [0042]-[0043]: circuit operates in successive cycles corresponding to the sampling period of the input signal, each cycle involving two non-overlapping clock phases C and XC, which can be considered M=2 periods, and the “clock circuitry (23)” and “START UNIT (500)” generate and use clock signals (C, XC, CLK SIGNALS) to control the sampling amplifier switches in successive cycles and periods); and Aaltonen, is silent in regard to: M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential; However, Huang, further teaches: M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential (Fig. 1; [0021]-[0022] & [0026]: demonstrates an array of M capacitors (where M = N) with bottom terminals connected to reference potentials (VR/GND)); It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the derivator of Aaltonen with the M capacitive elements of Huang. It is known in the art from Aaltonen to utilize a switched capacitor derivator circuit with input capacitances to extract amplitude data. Aaltonen, however, does not detail M capacitive elements, where M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential. Huang teaches a sample and hold circuit comprising M capacitive elements, specifically capacitor array 140 with capacitors C1_1 to C1_N, each having a bottom electrode connected to a reference potential such as VR or GND. The motivation to combine these teachings would be to increase the charge storage capacity and enable multi-stage charge redistribution, which predictably improves signal amplification efficiency and dynamic range. This combination represents a substitution of single capacitors with a multi-capacitor array to yield the predictable variation of enhanced dynamic range in a switched-capacitor network (KSR). Aaltonen, and Huang, are silent in regard to: M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first diode configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node; secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit; control the switches such that, at each period of each cycle: the first voltage is memorized on a respective one of the M capacitive elements; and the first input of the first circuit receives the first voltage memorized at a first instant on the respective one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant; However, Maurino, further teaches: M primary switches each configured to couple a second terminal of a corresponding one of the M capacitive elements to a first diode configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node (Fig. 4; [0003], [0032]-[0033], [0053]-[0054], & [0067]: teaches multiple primary switches (ps1/ps2) that directly connect to respective multi-sampling capacitors to the first node receiving the input voltage (Vin)); secondary switches each configured to couple the second terminal of the corresponding one of the M capacitive elements and a second terminal of a corresponding one of the M primary switches to the second input of the first circuit (Fig. 4; [0034]-[0035], [0049], & [0055]-[0056]: uses secondary switches (p1/p2) to connect the capacitors to the amplifier’s input node (154) once sampling is complete); control the switches such that, at each period of each cycle: the first voltage is memorized on a respective one of the M capacitive elements ([0018], [0032], & [0053]: switches are controlled such that the respective capacitors accumulate and hold (memorize) the input voltage during their specific clock period); and the first input of the first circuit receives the first voltage memorized at a first instant on the respective one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant ([0018], [0034]-[0035], [0051], [0055]-[0056], [0061], [0109], & [Claim 19]: topology systematically feeds the voltages sampled at different time instants (e.g., T1 vs. T2) into the differential inputs of the amplifier during separate phases); It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined circuit of Aaltonen and Huang to include the primary and secondary switching topology of Maurino. The combination of Aaltonen and Huang discloses a derivator with M capacitive elements but lacks M primary switches coupling the elements to a first node, secondary switches coupling the elements to a first circuit, and controlling the switches to memorize voltages at distinct instants. Maurino teaches M primary switches ps1 and ps2 coupling a second terminal of M capacitive elements C1 and C2 to a first node 152 receiving a first voltage Vin. Maurino further teaches secondary switches p1 and p2 coupling the capacitive elements to the input 154 of a first circuit amplifier 120 and controlling the switches such that the first voltage is memorized and the first circuit receives the memorized voltage at different instants T1 through T4. The motivation would be to decouple the charging and discharging phases of the M capacitive elements to maintain a short, consistent time delay between sampling intervals. This modification constitutes the use of a known technique to improve similar devices by predictably rejecting flicker noise and reducing jitter in the sampling phases (KSR). Aaltonen, Huang, and Maurino, are silent in regard to: a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between first and second inputs of the first circuit; a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit; and However, Matsuo, further teaches: a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between first and second inputs of the first circuit (Fig. 7; [Col. 1, ll. 11-44 & 63-67], [Col. 2, ll. 23-31], [Col. 3, ll. 7-21, 42-53, & 62-67], [Col. 4, ll. 1-44], [Col. 6, ll. 1-63], [Col. 7, ll. 13-30], [Col. 14, ll. 10-18], [Col. 15, ll. 59-67], [Col. 16, ll. 1-7 & 15-37], [Claim 1], & [Claim 12]: provides the core difference amplifier (first circuit) that processes the sampled inputs and outputs the resultant voltage difference); a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 8, ll. 26-32], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], & [Col. 11, ll. 43-59]: Fig. 3 illustrates a “sampling use capacitor element CS1” connected between the input node ND1 and the amplifier input V-, Fig. 7 illustrates capacitor C1 connected between node ND3 (input to the first circuit/comparator) and ground, functioning to store the DC component and smooth the operational point; alternatively teaches a first smoothing capacitor C3 and a second smoothing capacitor C4 connected between the first and second inputs of the operational amplifier (ND5/ND6) and the ground potential (the measurement circuit reference input)) and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 8, ll. 26-32], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], & [Col. 11, ll. 43-59]: describes the “…DC component VC is supplied to the capacitor elements C1 and C2 connected to the nodes ND3 and ND4…”, Fig. 7 illustrates the symmetrical capacitor C2 connected between node ND4 (second input to the first circuit/comparator) and ground, performing the identical smoothing function as C1); and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Matsuo’s difference amplifier and smoothing capacitors into the modified primary device. The preceding combination discloses a multi-capacitor switching topology but does not detail a first circuit delivering a voltage difference, nor does it teach first and second smoothing capacitive elements connected between the inputs of the first circuit and a reference potential. Matsuo teaches a first circuit, specifically an operational amplifier 10, configured to amplify a differential voltage and deliver a second voltage comprising output signal D and inverted signal XD indicating the voltage difference. Matsuo also teaches a first smoothing capacitive element C3 and a second smoothing capacitive element C4 connected between the first input ND5 and second input ND6 of the first circuit and a ground potential, which acts as the reference input. Matsuo further teaches that connecting capacitive elements C1/C2 to the inputs of a circuit (a comparator, a type of measurement circuit) to store the DC component of the input results in a significant reduction in the fluctuation of the operation points, smoothing the DC operating point. The motivation for this incorporation is to accurately compute the differential voltage across the sampled instants while preventing the operation point from fluctuation outside the input range due to transient noise. This represents a substitution of known amplifier and filtering elements into the measurement circuit to obtain the predictable variation of stabilized voltage comparison without increasing circuit size (KSR). Aaltonen, Huang, Maurino, and Matsuo, are silent in regard to: a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit. However, Hurwitz, further teaches: a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit (Fig. 12; [0092]: teaches a measurement circuit utilizing a second coupling circuit that functions as a buffer circuit (operational amplifier 306) to actively couple an input signal to a specific measurement node). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined measurement circuit to incorporate the buffer circuit coupling the input to the first node as taught by Hurwitz. The combination of Aaltonen, Huang, Maurino, and Matsuo provides a stabilized differential measurement circuit but lacks a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit. Hurwitz teaches a differential measurement circuit comprising a second circuit coupling an input of the measurement circuit with a specific circuit node, wherein the second circuit is explicitly a buffer circuit, such as an operational amplifier 306 coupling a stimulus generator 170 to a node 312. The motivation for this modification is to maintain signal integrity and prevent the measurement node from drawing excessive current from the input signal source. This represents the application of a known technique to improve similar devices, predictably providing isolation and impedance matching between the input source and the sampling nodes to ensure accurate voltage measurements (KSR). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUGO NAVARRO whose telephone number is (571)272-6122. The examiner can normally be reached Monday-Friday 08:30-5:00 pm EST. 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For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUGO NAVARRO/ Examiner, Art Unit 2858 September 24, 2026 /SON T LE/ Primary Examiner, Art Unit 2858