Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of figure 3 (presumably Species I) in the reply filed on 11/10/25 is acknowledged. The traversal is on the ground(s) that figures 2 and 3 are not distinct species. Since fig. 2 was not found to be a separate species from the other species of fig. 5 and 6 in the Requirement for Restriction/Election on 09/08/2025, Examiner accepts that fig. 2 and 3 can be examined together.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claims 1, 2, and 11 are objected to because of the following informalities:
Regarding claim 1, in lines 14 and 15, "logic and gate" should be --logic AND gate--. Similar corrections should be made in claims 2 and 11. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-7, 9-13, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, the tristate inverter is 218. The p-channel transistor introduced in claim 2 appears to be 206 since it receives a signal from the clock generation circuitry at the gate and has a terminal coupled to the supply. However, it is unclear how 218 has a second input terminal coupled to the second terminal [drain] of the p-channel transistor 206. Note that the input terminal of the tristate inverter is already introduced in claim 1 as that being at EN_LATCHED. The other input terminals of 218 are CLKZ and CLKB, which are not coupled to the drain of 206.
Regarding claim 4, it is claimed that the third transistor [214] has a control terminal coupled to the second terminal of the p-channel transistor [206]. However, the control of 214 is coupled to the clock generator and does not connect to the second terminal of 206. 206 is presumably the p-channel transistor introduced in claim 2 due to the claims connections. If 206 is not the p-channel transistor, there do not appear to be any transistors with a terminal coupled to the control terminal of the third transistor.
Regarding claim 5, first, it is unclear which transistor constitutes the second p-channel transistor. This transistor has a control terminal coupled to a clock. 206 was already introduced in claim 2 and is the first p-channel transistor. 306 receives a clock at the gate but does not have a terminal coupled to the second terminal of the first p-channel transistor 206. It is unclear if the third transistor is supposed to reference 214, with an indirect connection to 306. However, the current flows from 214 to 216 to 218, and the feedback from 306 does not really couple to 214. Examiner is unclear as to whether the term coupling here only requires a physical connection and not an electrical one. Further, there is claimed a second inverter but parent claim 1 already claims inverter 216 and tristate inverter 218. 220 is the AND logic gate, and there does not appear to be a second inverter. Similar comments are directed towards the fourth and fifth transistors.
Regarding claim 9, the respective transistors appear to be 206, 208, 210, and 214. The second transistor appears to be 214 because it has a control terminal coupled to the clock generation circuitry. However, it is then claimed that the first terminal [drain] of the second transistor [214] is coupled to the second terminal [drain] of the second p-channel transistor [208] and the first terminal [drain] of the first transistor [210]. While the drain of 208 and drain of 210 are indeed coupled, it is unclear if it is intended that this claim recites where the drain of 214 couples to that node via 212 indirectly. There is a similar issue regarding the connections described in the last section of this claim as well. It is unclear whether the second transistor should have the control terminal coupled to the clock control circuitry via a second connection so that the second transistor then refers to 212, in which case the claimed coupling aligns directly. For the purpose of advancing prosecution, the Examiner will presume that the second transistor is coupled to the clock control circuitry to align with the figure.
Regarding claim 10, it appears that the third transistor is 214. While the control terminal of this transistors receives a clock signal, it is unclear how the claimed control terminal of the second transistor 212 also receives a clock signal. Furthermore, it appears from claim 9 that the second transistor refers to 214 since the control terminal is coupled to the clock generation circuitry.
Regarding claim 11, it contains similar issues as above. To the best of Examiner's knowledge, the first p-channel transistor is 206, the second p-channel transistor is 208, the first transistor is 210, the second transistor is 212, and the inverter is 216. It is unclear what the third and fourth transistors are since they are claimed to have control terminals coupled to the clock control circuit, which outputs EN and TE. However, from the top portion of fig. 3, there are no such transistors that receive those signals. The bottom portion of fig. 3 is the clock generator, which is introduced in claim 9. If the third and fourth transistors refer to transistors in the clock generator, claim 11 should specify that explicitly. However, this doesn't appear to be the case since these transistors appear to be in parallel but 210 and 212 seem to have already been introduced in claim 9. It is unclear whether there is a typo here or in claim 9. There is also claimed a second inverter in addition to the first inverter 216. It is unclear what inverter this references since tristate inverter 218 is also introduced in this claim.
Regarding claim 12, it is unclear which transistor is the fifth transistor that has a control terminal coupled to the second terminal of the first p-channel transistor 206.
Regarding claim 13, it is unclear which transistors are the third and fourth p-channel transistors. Examiner thought that the third p-channel transistor was 312 since it has a gate coupled to the output of the first inverter 216. However, then it claims that the fourth p-channel transistor [314?] has a first terminal coupled to the second terminal of the third p-channel transistor 312 and also a second terminal coupled to the first terminal of the third transistor. However, the other terminal of 314 is coupled to supply.
Regarding claim 16, the seventh p-channel transistor appears to be 314. It is unclear how the control terminal of 314 is coupled to the clock generation circuitry at the bottom of fig. 3. That circuitry shows where CLKB and CLKZ are generated based on CLK. 314 receives CLK and not CLKB or CLKZ. Two elements receiving the same input does not mean that they are coupled to each other. If 314 received CLKB or CLKZ, then it would be coupled to the clock generation circuitry. Further, it is unclear how the second terminal of 314 at the drain is coupled to the control terminal of 306 and the control terminal of 308.
Regarding claim 18, there is claimed an inverter but parent claim 14 already introduced the transistors 301 and 302 within the inverter. It is unclear if this is a separate inverter or referencing the same one.
Regarding claim 20, details of the inverter are provided. However, such transistors 301 and 302 were already introduced in claim 14 as the first p-channel transistor and third transistor. If the transistor is actually referencing 228 in the clock generator, then claim 16 already introduces clock generation circuitry and claims 18-20 do not specify that this inverter is part of the clock generation circuitry. Furthermore, the transistors of the tristate inverter have also already been introduced. It is unclear what inverter is being claimed and whether it is part of another previously introduced element.
Regarding claims 6, 7, 17, and 19, these claims are rejected since they depend on claims above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baratam (US 2019/0028091).
Regarding claim 9, fig. 3E of Baratam discloses an apparatus comprising: a first p-channel transistor [P2] including a control terminal, a first terminal, and a second terminal, the control terminal of the first p-channel transistor coupled to clock generation circuitry [310A and 312A], the first terminal of the first p-channel transistor coupled to a supply voltage terminal; a second p-channel transistor [P0] including a control terminal, a first terminal, and a second terminal, the control terminal of the second p-channel transistor coupled to the clock control circuitry [that generating E and SE] via a first connection, the first terminal of the second p-channel transistor coupled to the second terminal of the first p-channel transistor; a first transistor [N0] including a control terminal, a first terminal, and a second terminal, the control terminal of the first transistor coupled to the clock control circuitry via the first connection, the first terminal of the first transistor coupled to the second terminal of the second p-channel transistor, the second terminal of the first transistor coupled to a ground terminal; a second transistor [N1] including a control terminal, a first terminal, and a second terminal, the control terminal of the second transistor coupled to the clock control circuitry via a second connection, the first terminal of the second transistor coupled to the second terminal of the second p-channel transistor and the first terminal of the first transistor, the second terminal of the second transistor coupled to the ground terminal; and an inverter [304A] including an input terminal and an output terminal, the input terminal of the inverter coupled to the second terminal of the second p-channel transistor, the first terminal of the first transistor, and the first terminal of the second transistor.
Regarding claim 10, fig. 3E of Baratam discloses a third transistor [e.g. N5] including a control terminal, a first terminal, and a second terminal, the control terminal of the third transistor coupled to the clock generation circuitry, the first terminal of the third transistor coupled to the second terminal of the first p-channel transistor, the second terminal of the third transistor coupled to the ground terminal, the control terminal of the second transistor and the control terminal of the third transistor to receive a first clock signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 8, and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gurumurthy (US 2014/0184271) in view of Kim (US 10,944,401).
Regarding claim 1, fig. 2 of Gurumurthy discloses an apparatus comprising a NOR gate 105, an inverter [120] including an input terminal and an output terminal, the input terminal of the inverter coupled to the NOR gate; a tristate inverter [125] including an input terminal and an output terminal, the input terminal of the tristate inverter coupled to the output terminal of the inverter, the output terminal of the tristate inverter coupled to the input terminal of the inverter, and the NOR gate; and a logic AND gate [130 and 135, since 130 is a NAND and 135 is an inverter] including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the logic and gate coupled to the output terminal of the inverter and the input terminal of the tristate inverter, and the second input terminal coupled to clock generation circuitry [that generating CLKIN]. Gurumurthy does not explicitly disclose the transistor implementation of NOR gate 105. However, fig. 2 of Kim shows a transistor implementation of a NOR gate [120A]. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the NOR design as taught in Kim for the purpose of utilizing a suitable and well-known type of NOR. After the combination described above, the resulting combination discloses a first transistor [NA1 of 105] including a control terminal, a first terminal, and a second terminal; a second transistor [NA2 of 105] including a control terminal, a first terminal, and a second terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor.
Regarding claim 2, the combination as indicated above discloses a p-channel transistor [e.g. p-channel transistor in 110] including a control terminal, a first terminal, and a second terminal, the control terminal of the p-channel transistor coupled to the clock generation circuitry, the first terminal of the p-channel transistor coupled to a supply voltage terminal, wherein the control terminal of the p-channel transistor is coupled to receive a first clock signal and the output terminal of the logic AND gate is configured to provide a second clock signal based on the first clock signal.
Regarding claim 8, the combination as indicated above discloses wherein the control terminal of the first transistor is coupled to clock control circuitry via a first connection and the control terminal of the second transistor is coupled to the clock control circuitry via a second connection.
Regarding claim 14, fig. 2 of Gurumurthy discloses an apparatus comprising: a NOR gate 105 coupled to an inverter 120 coupled to a tristate inverter 125 coupled to NAND gate 130 and inverter 135. Gurumurthy does not explicitly disclose the transistor implementations of the NOR gate, inverter, tristate inverter, and NAND gate. However, fig. 2 of Kim shows transistor implementations of a NOR gate 120A, inverter 220A, tristate inverter 240A, and NAND gate 260A. In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the transistor designs as taught in Kim for the purpose of utilizing a suitable and well-known type of transistor implementation for well-known circuits. After the combination described above, the resulting combination discloses a first transistor [NA1 of 105] including a control terminal, a first terminal, and a second terminal; a second transistor [NA2 of 105] including a control terminal, a first terminal, and a second terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the second terminal of the second transistor coupled to the second terminal of the first transistor; a first p-channel transistor [PA9 of 120] including a control terminal, a first terminal, and a second terminal, the control terminal of the first p-channel transistor coupled to the first terminal of the first transistor and the first terminal of the second transistor, the first terminal of the first p-channel transistor coupled to a supply terminal; a third transistor [NA9 of 120] including a control terminal, a first terminal, and a second terminal, the control terminal of the third transistor coupled to the first terminal of the first transistor, the first terminal of the second transistor, and the control terminal of the first p-channel transistor, the first terminal of the third transistor coupled to the second terminal of the first p-channel transistor, the second terminal of the third transistor coupled to a ground terminal; a second p-channel transistor [PA5 of 125] including a control terminal, a first terminal, and a second terminal, the control terminal of the second p-channel transistor coupled to the second terminal of the first p-channel transistor and the first terminal of the third transistor, the first terminal of the second p-channel transistor coupled to the supply terminal; a third p-channel transistor [PA6 of 125] including a control terminal, a first terminal, and a second terminal, the first terminal of the third p-channel transistor coupled to the second terminal of the second p-channel transistor, the second terminal of the third p-channel transistor coupled to the first terminal of the first transistor, the first terminal of the second transistor, the control terminal of the first p-channel transistor, and the control terminal of the third transistor; a fourth transistor [NA6 of 125] including a control terminal, a first terminal, and a second terminal, the first terminal of the fourth transistor coupled to the second terminal of the third p-channel transistor, the first terminal of the first transistor, the first terminal of the second transistor, the control terminal of the first p-channel transistor, and the control terminal of the third transistor; and a fifth transistor [NA5 of 125] including a control terminal, a first terminal, and a second terminal, the control terminal of the fifth transistor coupled to the control terminal of the second p-channel transistor, the second terminal of the first p-channel transistor, and the first terminal of the third transistor, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor, the second terminal of the fifth transistor coupled to the ground terminal.
Regarding claim 15, the combination as indicated above discloses a fourth p-channel transistor [PA7 of 130] including a control terminal, a first terminal, and a second terminal, the control terminal of the fourth p-channel transistor coupled to the second terminal of the first p-channel transistor, the first terminal of the third transistor, the control terminal of the second p-channel transistor, and the control terminal of the fifth transistor, the first terminal of the fourth p-channel transistor coupled to the supply terminal; a fifth p-channel transistor [PA8 of 130] including a control terminal, a first terminal, and a second terminal, the control terminal of the fifth p-channel transistor coupled to clock generation circuitry, the first terminal of the fifth p-channel transistor coupled to the supply terminal, the second terminal of the fifth p-channel transistor coupled to the second terminal of the fourth p-channel transistor; a sixth transistor [NA8 of 130] including a control terminal, a first terminal, and a second terminal, the control terminal of the sixth transistor coupled to the clock generation circuitry, the first terminal of the sixth transistor coupled to the second terminal of the fourth p-channel transistor and the second terminal of the fifth p-channel transistor; a seventh transistor [NA7 of 130] including a control terminal, a first terminal, and a second terminal, the control terminal of the seventh transistor coupled to the control terminal of the fourth p-channel transistor, the second terminal of the first p-channel transistor, the first terminal of the third transistor, the control terminal of the second p-channel transistor, and the control terminal of the fifth transistor, the first terminal of the seventh transistor coupled to the second terminal of the sixth transistor, and the second terminal of the seventh transistor coupled to the ground terminal; a sixth p-channel transistor [in 135] including a control terminal, a first terminal, and a second terminal, the control terminal of the sixth p-channel transistor coupled to the second terminal of the fourth p-channel transistor, the second terminal of the fifth p-channel transistor, and the first terminal of the sixth transistor, the first terminal of the sixth p-channel transistor coupled to the supply terminal; and an eighth transistor [in 135] including a control terminal, a first terminal, and a second terminal, the control terminal of the eighth transistor coupled to the control terminal of the sixth p-channel transistor, the second terminal of the fourth p-channel transistor, the second terminal of the fifth p-channel transistor, and the first terminal of the sixth transistor, the first terminal of the eighth transistor coupled to the second terminal of the sixth p-channel transistor, and the second terminal of the eighth transistor coupled to the ground terminal.
Regarding claim 16, the combination as indicated above discloses a seventh p-channel transistor [PA8 of 130]including a control terminal, a first terminal, and a second terminal, the control terminal of the seventh p-channel transistor coupled to clock generation circuitry, the first terminal of the seventh p-channel transistor coupled to a supply voltage terminal, the second terminal of the seventh p-channel transistor coupled to the control terminal of the third p- channel transistor and the control terminal of the fourth transistor.
Regarding claim 17, the combination as indicated above discloses a sixth transistor [in 135] including a control terminal, a first terminal, and a second terminal, the control terminal of the sixth transistor coupled to the second terminal of the seventh p-channel transistor, the first terminal of the sixth transistor coupled to the second terminal of the first transistor and the second terminal of the second transistor, the second terminal of the sixth transistor coupled to the ground terminal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Rasouli discloses a clock gating circuit and method of operating the same. Lee discloses a clock gating cell with low power.
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/SIBIN CHEN/Primary Examiner, Art Unit 2896