Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 5, 7, 9 – 14, & 17 - 19 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by YAMAMOTO (WO 2011004580 A1).
With regards to claim 1, YAMAMOTO teaches:
A test device comprising a receiving circuit, wherein the receiving circuit includes: a first data sampling circuit configured to sample a data signal using a first recovery clock (Abstract & Description: a sampling circuit which samples received data signals; this specification relates to a clock data recovery circuit that extracts data and a clock synchronized with the data from a data signal); a second data sampling circuit configured to sample an output signal of the first data sampling circuit using a second recovery clock; a third data sampling circuit configured to sample an output signal of the second data sampling circuit using a third recovery clock (Fig. 1 and corresponding specification & abstract: The multi-phase clock generation circuit 10 has a PLL (Phase Locked Loop), generates a multi-phase clock CKS, and outputs it to the sampling circuit 32. The sampling circuit 32 receives a differential data signal (RX +, RX−) transmitted from a host or the like and transmits serial data; and selects a clock corresponding to this data signal); a first clock recovery circuit configured to receive the data signal and generate the first recovery clock; a second clock recovery circuit configured to receive the output signal of the first data sampling circuit and generate the second recovery clock; and a third clock recovery circuit configured to receive the output signal of the second data sampling circuit and generate the third recovery clock (Fig. 10 and corresponding specification & abstract: The clock data recovery circuit of FIG. 10 is different from the clock data recovery circuit of FIG. 1; The clock data recovery circuit comprises: a multiphase clock generation circuit which generates a multiphase clock comprising a plurality of clocks).
With regards to claim 2, YAMAMOTO teaches the test device of claim 1:
wherein each of the first data sampling circuit, the second data sampling circuit, and the third data sampling circuit includes a flip-flop (Fig. 1 and the corresponding specification: The sampling circuit 32 receives a differential data signal (RX +, RX−) transmitted from a host or the like and transmits serial data, and synchronizes this signal with each of n clocks included in the multiphase clock CKS. Sampling is performed, and the sampled values are output to the parallel circuit 34 as data signals DS [n−1: 0] corresponding to these n clocks).
With regards to claim 3, YAMAMOTO teaches the test device of claim 1:
wherein the data signal includes random jitter of a predetermined bandwidth (Fig. 22 and the corresponding specification: the frequency of the received data signal only changes due to the influence of jitter), wherein the output signal of the first data sampling circuit has about 1/2 random jitter of the random jitter, the output signal of the second data sampling circuit has about 1/4 random jitter of the random jitter, and an output signal of the third data sampling circuit has about 1/8 random jitter of the random jitter (Fig. 23 and the corresponding specification: the loop bandwidth control circuit 619 sets the phase comparator 613 before starting data communication so that the loop bandwidth is reduced. At least one of the gain Kpd, the transfer function F of the low-pass filter 614, and the gain Kvco of the VCO 615 is made smaller than when the determination signal SC indicates that the SSC is on. Then, jitter is suppressed and the accuracy of clock data recovery can be improved).
With regards to claim 4, YAMAMOTO teaches the test device of claim 3:
wherein the predetermined bandwidth is about 10 MHz to about 20 MHz (Fig. 23 and the corresponding specification: The loop bandwidth control circuit 619 controls the loop bandwidth).
With regards to claim 5, YAMAMOTO teaches the test device of claim 1:
wherein the output signal of the first data sampling circuit includes jitter at or above a predetermined frequency, wherein the output signal of the second data sampling circuit and an output signal of the third data sampling circuit reduce the jitter (Fig. 23 and the corresponding specification: FIG. 20 may detect jitter based on the tracking result and generate a determination signal SC indicating whether the jitter is equal to or greater than a predetermined threshold. When the determination signal SC indicates that the jitter, jitter is suppressed and the accuracy of clock data recovery can be improved).
With regards to claim 7, YAMAMOTO teaches the test device of claim 1:
wherein the data signal is transmitted without a clock (Fig. 10 and corresponding specification: a clock that is not supplied when a part of the clocks included in the multiphase clock is stopped by the clock selection circuits 38A to 38C).
With regards to claim 9, YAMAMOTO teaches the test device of claim 1:
wherein the receiving circuit allows random jitter of about 10 MHz or less (Fig. 23 and the corresponding specification: The loop bandwidth control circuit 619 controls the loop bandwidth, jitter is suppressed and the accuracy of clock data recovery can be improved).
With regards to claim 10, YAMAMOTO teaches the test device of claim 1:
wherein a test operation is performed in the test device at a speed of about 13 Gbps or more (Fig. 23 and corresponding specification: The loop bandwidth control circuit 619 controls the loop bandwidth, jitter is suppressed and the accuracy of clock data recovery can be improved).
With regards to claim 11, YAMAMOTO teaches:
A test device comprising a receiving circuit, wherein the receiving circuit includes: a plurality of clock data recovery circuits connected in cascade, wherein each of the plurality of clock data recovery circuits includes: a clock recovery circuit configured to receive a data signal and generate a recovery clock; and a data sampling circuit configured to sample the data signal in response to the recovery clock (Fig. 10 and corresponding specification & abstract: The clock selection circuits 38B and 38C supply the selected clock to the parallelization circuit 34 and the data restoration unit 40, respectively. The clock data recovery circuit comprises: a multiphase clock generation circuit which generates a multiphase clock comprising a plurality of clocks; a sampling circuit which samples received data signals, which transmit serial data, in synchronization with each of the plurality of clocks, and generates a plurality of data signals).
With regards to claim 12, YAMAMOTO teaches the test device of claim 11:
wherein the plurality of clock data recovery circuits reduces random jitter having a predetermined frequency band in a stepwise manner (Fig. 23 and the corresponding specification: the loop bandwidth control circuit 619 sets the phase comparator 613 before starting data communication so that the loop bandwidth is reduced. At least one of the gain Kpd, the transfer function F of the low-pass filter 614, and the gain Kvco of the VCO 615 is made smaller than when the determination signal SC indicates that the SSC is on. Then, jitter is suppressed and the accuracy of clock data recovery can be improved).
With regards to claim 13, YAMAMOTO teaches the test device of claim 12:
wherein a first clock data recovery circuit, among the plurality of clock data recovery circuits, reduces the random jitter by about ½ (Fig. 23 and the corresponding specification: the loop bandwidth control circuit 619 sets the phase comparator 613 before starting data communication so that the loop bandwidth is reduced).
With regards to claim 14, YAMAMOTO teaches the test device of claim 12:
wherein the predetermined frequency band is about 10 MHz to about 20 MHz (Fig. 23 and the corresponding specification: The loop bandwidth control circuit 619 controls the loop bandwidth, jitter is suppressed and the accuracy of clock data recovery can be improved).
With regards to claim 17, YAMAMOTO teaches the test device of claim 16 and corresponds to claim 12 as analyzed accordingly.
With regards to claim 18, YAMAMOTO teaches the test device of claim 17 and corresponds to claim 14 as analyzed accordingly.
With regards to claim 19, YAMAMOTO teaches the test device of claim 16 and corresponds to claim 10 as analyzed accordingly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8, 15, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (WO 2011004580 A1) in view of XU (CN 1677844 A).
With regards to claim 6, YAMAMOTO teaches the test device of claim 1.
YAMAMOTO fails to teach:
wherein the receiving circuit is implemented with a field programmable gate array (FPGA).
However, XU teaches:
wherein the receiving circuit is implemented with a field programmable gate array (FPGA) (Fig. 3 and corresponding specification: In a preferred embodiment, the digital phase detector 312, digital loop filter 314 and σ-modulator 316 is provided together with a single digital component, such as a FPGA (field programmable gate array)).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a of a clock data recovery unit wherein the time required for clock data recovery is reduced of YAMAMOTO with the teaching of XU, which teaches image read out of the output in order to display signals from receiving circuit to the user as suggested by XU in Fig. 9 and the corresponding specification (The automatic test system by the main control computer 1010 for testing the DUT, comprising a waveform generator).
With regards to claim 8, YAMAMOTO teaches the test device of claim 1.
YAMAMOTO fails to teach:
wherein the data signal is received from an image sensor at a wafer level.
However, XU teaches:
wherein the data signal is received from an image sensor at a wafer level (XU: Fig. 7 and corresponding specification: These images form the orthogonal differential signal).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a clock data recovery unit wherein the clock is selected based on the received data signal of YAMAMOTO with the teaching of XU, which teaches image read out of the output in order to display the frequencies as images to the user as suggested by XU in Fig. 9 and the corresponding specification (The automatic test system by the main control computer 1010 for testing the DUT, comprising a waveform generator).
With regards to claim 15, YAMAMOTO teaches the test device of claim 11.
YAMAMOTO teaches:
without a clock (Fig. 10 and corresponding specification: a clock that is not supplied when a part of the clocks included in the multiphase clock is stopped by the clock selection circuits 38A to 38C).
YAMAMOTO fails to teach:
wherein the data signal is received from an image sensor.
However, XU teaches:
wherein the data signal is received from an image sensor without a clock (XU: Fig. 7 and corresponding specification: These images form the orthogonal differential signal.).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a clock recovery circuit configured to receive a data signal and generate a recovery clock of YAMAMOTO with the teaching of XU, which teaches image read out of the output in order to prioritize a jitter free signal to the user as suggested by XU in Fig. 9 and the corresponding specification (The digital pin sources and/or sensing the digital signal at a predetermined instant time format and precisely controlled).
With regards to claim 20, YAMAMOTO in view of LEE teaches the test device of claim 16. YAMAMOTO in view of LEE fails to teach:
wherein the DUT comprises an image sensor.
However, XU teaches:
wherein the DUT comprises an image sensor (XU: Fig. 2 and the corresponding specification: frequency sensor of the phase detector can be used for electronic system, such as the ATE generates a periodic waveform).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a clock data recovery unit wherein the time required for clock data recovery is reduced of YAMAMOTO with the teaching of XU, which teaches generating images from signals in order to read the output of the device under test to the user as suggested by XU in Fig. 9 and the corresponding specification (The automatic test system by the main control computer 1010 for testing the DUT, comprising a waveform generator).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (WO 2011004580 A1) in view of LEE (US 20170052221 A1).
With regards to claim 16, YAMAMOTO teaches the test device of claim 1.
YAMAMOTO teaches:
wherein the receiving circuit having a plurality of clock data recovery circuits connected in cascade (Fig. 8 and corresponding specification: using any one of the circuits).
YAMAMOTO fails to teach:
wherein the test device connected to an interface board through a cable and configured to test a device under test (DUT) through signals received through the cable,
However, LEE teaches:
wherein the test device connected to an interface board through a cable and configured to test a device under test (DUT) through signals received through the cable, wherein the receiving circuit having a plurality of clock data recovery circuits connected in cascade (LEE: 0006, DUT 140 are coupled to one or more receivers 120B of BERT 120 by way of an interconnect (such as a cable)).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to modify the system of a clock data recovery unit wherein the time required for clock data recovery is reduced of YAMAMOTO with the teaching of LEE, which teaches test a device under test (DUT) through signals received through the cable in order to reduce clock recovery time of the device under test as suggested by Lee. (Lee: 0019, Such on-chip circuits eliminate or reduce the need for expensive specialized test equipment and reduce the time required for manufacturing/testing an integrated circuit).
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
UMAI (JP 2013009389 A): A clock data recovery circuit of an interpolator type capable of multi-rate data without increasing the bandwidth of an interpolator circuit.
Conclusion
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/V.P./Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111