CTNF 18/583,530 CTNF 76497 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 7-9, 14, 16-18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Gonzalez-Guerrero et al., "Temporal and SFQ Pulse-Streams Encoding for Area-Efficient Superconducting Accelerators", ASPLOS '22, February 28 - March 4, 2022, Lausanne, Switzerland . Claim 1, Gonzalez-Guerrero discloses a superconducting computing architecture (Figs. 13a-b) comprising: a first computing element (PE, Fig. 13a-b) comprising: a first input (In1 input) to receive a first set of electrical pulses encoded in a first data representation; a second input (E or In2 input) to receive a second set of electrical pulses encoded in a second data representation; and an operator (Multiplier, Adder, Accumulator, Fig. 13a) to perform an operation and generate an output (OUT output) based on the first set of electrical pulse of the first input and the second set of electrical pulses of the second input. Claim 7, Gonzalez-Guerrero discloses superconducting computing architecture of claim 1, further comprising a processing element comprising at least the first computing element (see Fig. 13A). Claim 8, Gonzalez-Guerrero discloses the superconducting computing architecture of claim 7, wherein the processing element comprises at least one of a unary multiplier, a unary adder, and an accumulator (Multiplier, Adder, Accumulator, Fig. 13a) implemented using the first data representation or the second data representation. Claim 9, Gonzalez-Guerrero discloses the superconducting computing architecture of claim 7, further comprising: a plurality of processing elements arranged in an array of processing elements (see Fig. 13b). Claim 14, Gonzalez-Guerrero discloses superconducting hardware accelerator circuit (see Fig. 13a-b and section 5.2: …hardware accelerators such as CGRAs and SpA…) comprising: a first computing element (PE, Fig. 13a-b) comprising: a first input (In1 input) to receive a first set of electrical pulses encoded in a first data representation; a second input (E or In2 input) to receive a second set of electrical pulses encoded in a second data representation; and an operator (Multiplier, Adder, Accumulator, Fig. 13a) to perform an operation and generate an output (OUT output) based on the first set of electrical pulse of the first input and the second set of electrical pulses of the second input. Claim 16, Gonzalez-Guerrero discloses superconducting hardware accelerator circuit of claim 14, further comprising a processing element comprising at least the first computing element (see Fig. 13A). Claim 17, Gonzalez-Guerrero discloses the superconducting hardware accelerator circuit of claim 16, wherein the processing element comprises at least one of a unary multiplier, a unary adder, and an accumulator (Multiplier, Adder, Accumulator, Fig. 13a) implemented using the first data representation or the second data representation. Claim 18, Gonzalez-Guerrero discloses the superconducting hardware accelerator circuit of claim 7, further comprising: a plurality of processing elements arranged in an array of processing elements (see Fig. 13b) . 07-15-aia AIA Claim(s) 1, 7-9, 14, 16-18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tzimpragos et al. (WO 2021/183344 A1) . Claim 1, Tzimpragos discloses a superconducting computing architecture (see P[0023]-[0024]…superconducting computing accelerators…), comprising: a first computing element (see Figure 8 (iii) and P[00106]…the sequencing accelerator depicted in Figures 8 and 9…) comprising: a first input to receive a first set of electrical pulses encoded in a first data representation; a second input to receive a second set of electrical pulses encoded in a second data representation; and an operator to perform an operation and generate an output based on the first set of electrical pulse of the first input and the second set of electrical pulses of the second input (see Figs. 3 and 10, basic RSFQ logic circuits for implement the computing element of Figure 8 (iii), which included two inputs to receive electrical pulses and an output, see the graphs of Figs. 3 and 10 for electrical pulses). Claim 7, Tzimpragos discloses the superconducting computing architecture of claim 1, further comprising a processing element (Fig. 8(iii)) comprising at least the first computing element. Claim 8, Tzimpragos discloses the superconducting computing architecture of claim 7, wherein the processing element comprises at least one of a unary multiplier, a unary adder (see P[0023]…adders…), and an accumulator implemented using the first data representation or the second data representation. Claim 9, Tzimpragos discloses the superconducting computing architecture of claim 7, further comprising: a plurality of processing elements arranged in an array of processing elements (see Fig. 8(i)). Claim 14, Tzimpragos discloses a superconducting hardware accelerator circuit (see P[0023]-[0024]…superconducting computing accelerators…, and see P[00106]…the sequencing accelerator depicted in Figures 8 and 9…) comprising: a first computing element (see Figure 8 (iii) and P[00106]…the sequencing accelerator depicted in Figures 8 and 9…) comprising: a first input to receive a first set of electrical pulses encoded in a first data representation; a second input to receive a second set of electrical pulses encoded in a second data representation; and an operator to perform an operation and generate an output based on the first set of electrical pulse of the first input and the second set of electrical pulses of the second input (see Figs. 3 and 10, basic RSFQ logic circuits for implement the computing element of Figure 8 (iii), which included two inputs to receive electrical pulses and an output, see the graphs of Figs. 3 and 10 for electrical pulses). Claim 16, Tzimpragos discloses the superconducting computing architecture of claim 14, further comprising a processing element (Fig. 8(iii)) comprising at least the first computing element. Claim 17, Tzimpragos discloses the superconducting computing architecture of claim 16, wherein the processing element comprises at least one of a unary multiplier, a unary adder (see P[0023]…adders…), and an accumulator implemented using the first data representation or the second data representation. Claim 18, Tzimpragos discloses the superconducting computing architecture of claim 16, further comprising: a plurality of processing elements arranged in an array of processing elements (see Fig. 8(i)). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH Q TRAN/Primary Examiner, Art Unit 2845 5/28/26 Application/Control Number: 18/583,530 Page 2 Art Unit: 2845 Application/Control Number: 18/583,530 Page 3 Art Unit: 2845 Application/Control Number: 18/583,530 Page 4 Art Unit: 2845 Application/Control Number: 18/583,530 Page 5 Art Unit: 2845 Application/Control Number: 18/583,530 Page 6 Art Unit: 2845 Application/Control Number: 18/583,530 Page 7 Art Unit: 2845
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