Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
Applicant’s election without traverse of Group I, Species A identified as encompassing Claims 1-5 and 9 is acknowledged.
The restriction is maintained and made final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 6043520 A), hereinafter as Y1, in view of Shamir et al. (US 6465804 B1), hereinafter as S1, and Li et al. (US 7868335 B1), hereinafter as L1 is utilized herein as evidence.
Regarding Claim 1, Y1 discloses a heterojunction bipolar transistor (see FIG. 1 and col. 3 ln. 34 “FIG. 1 is a cross-sectional view of a hetero-junction bipolar transistor (HBT)”) comprising:
a collector layer including an n-type compound semiconductor material (see FIG. 1, element 4, and col. 3 ln. 41 “4 denotes a GaAs collector layer including n-type impurities”);
a base layer on the collector layer, the base layer including a p-type compound semiconductor material (see FIG. 1, element 5, and col. 3 ln. 43 “5 denotes a GaAs base layer doped with p-type impurities” where this base layer 5 is on the collector layer 4);
an emitter layer on the base layer (see FIG. 1, element 7, and col. 3 ln. 44 “7 denotes a GaAs emitter layer doped with n-type impurities to a high concentration” where this layer is above and on the base layer 5),
Y1 does not explicitly disclose the emitter layer including an n-type compound semiconductor material having a band gap larger than a band gap of the base layer; and
Y1 discloses at least one ballast resistance layer on the emitter layer (see FIG. 1, elements 8 and 10, and col. 3 ln. 45 “8 and 10 denote GaAs ballast resistance stabilizing layers” where they are on the emitter layer 7).
Y1 does not explicitly disclose the ballast resistance layer including an intrinsic or p-type compound semiconductor material.
S1 discloses the emitter layer including an n-type compound semiconductor material having a band gap larger than a band gap of the base layer (see FIGs. 3 and 4, elements 42, 44, and 48, col. 5 ln. 17 “layers 42 and 44 in FIG. 4 are the wide bandgap emitter of the HBT” and also see how 42 and 44 are made of InP in FIG. 4 which is an n-type semiconductor material as shown. See col. 5 ln. 20 “the base of the transistor is layer 48” and how base layer 48 is made of InGaAs. The wide bandgap of InP in layers 42 and 44 and narrow band gap of InGaAs in layer 48 is an inherent property. See L1 [US 7868335 B1] and col. 4 ln. 52 “it should be understood that InP can be replaced with any material with a wide band gap and InGaAs can be replaced with any material with a narrower band gap…a band gap for InP may be 1.35 eV, while the band gap for InGaAs may be 0.4 eV” where it is noted that InP has a wider band gap than InGaAs and the specific values are provided as further evidence for the inherent band gaps of the semiconductor materials.)
S1 discloses the ballast resistance layer (see FIG. 3, elements 26 and 36, col. 4 ln. 61 high resistance p-type layer 26 adds ballast resistance to the emitter” and col. 5 ln. 8 “a common P++ layer, which is 36” which is an element of the ballast layer 26) including an intrinsic or p-type compound semiconductor material (The ballast layer 26 is said to be made of p-type compounds in FIG. 4 as layer 36).
The semiconductor materials for the base layer, emitter layer, and ballast resistance layers of S1 are incorporated as the materials disclosed by Y1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 into Y1 as there is motivation to include materials of this type to improve the HBT device without sacrificing desired resistance values. Including materials with p-type compounds allows for the thickness of the layer to be reduced without changing the resistance value and by having this material with a material of a higher band gap allows more precise current flow in the device. Using these materials in this manner creates predictable results due to the motivation for doing so being obvious (see S1 col. 3 ln. 47-64 and col. 5 ln. 17-24 col. 3 ln. 47-64)
Regarding Claim 2, Y1 and S1 disclose the heterojunction bipolar transistor according to Claim 1, wherein S1 further discloses the ballast resistance layer (element 36) and the collector layer (see FIGs. 3 and 4, element 50, col. 5 ln. 21 “collector is layer 50” and as seen in FIG. 4 the layer is made of InGaAs) include a same compound semiconductor (layer 36 that makes up the ballast resist is made of the same InGaAs as the collector layer 50).
Regarding Claim 3, Y1 and S1 disclose the heterojunction bipolar transistor according to Claim 1, wherein S1 further discloses the ballast resistance layer includes two n-type layers including an n-type compound semiconductor material and a p-type layer between the two n-type layers (see FIG. 4 elements 34, 36, and 38, and col. 5 ln. 4 “Esaki diode is the junction between layers 34 and 36, and the bottom Esaki diode is the junction between layers 36 and 38” where these make up the resistance layer, where in FIG. 4 it can be see that layers 34 and 38 are made of n-type compounds with the p-type compound layer 36 between them) and including a p-type compound semiconductor material (Layer 36 includes the compound InGaAs which is a semiconducting material).
Regarding Claim 4, Y1 and S1 disclose the heterojunction bipolar transistor according to Claim 3, wherein Y1 further discloses a donor concentration in each of the two n-type layers (elements 8 and 10 in FIG. 1, and col. 2 ln. 55 “concentration of impurities in the ballast resistor layer is preferably within the range from 1×1016 cm-3 to 5×1016 cm-3” where the lowest value is within the presented range) and an acceptor concentration in the p-type layer are each less than or equal to 1×1016 cm-3 (see col. 2 ln. 58 “concentration of impurities in the low-resistance GaAs layer is preferably within the range from 1×1018 cm-3 to 6×1018 cm-3 “ which represents the p-type materials and is within the presented range).
Regarding Claim 5, Y1 and S1 disclose the heterojunction bipolar transistor according to Claim 1, wherein the collector layer (as disclosed by Y1 in FIG. 1, the collector layer 4 includes GaAs in its compound) and the base layer each include a GaAs compound semiconductor material (as disclosed in S1 FIG. 4 in the integrated base layer 48 includes GaAs in its InGaAs composition). Regarding Claim 9, S1 and Y1 disclose the heterojunction bipolar transistor according to Claim 2, wherein S1 further discloses the ballast resistance layer includes two n-type layers including an n-type compound semiconductor material and a p-type layer between the two n-type layers (see FIG. 4 elements 34, 36, and 38, and col. 5 ln. 4 “Esaki diode is the junction between layers 34 and 36, and the bottom Esaki diode is the junction between layers 36 and 38” where these make up the resistance layer, where in FIG. 4 it can be see that layers 34 and 38 are made of n-type compounds with the p-type compound layer 36 between them) and including a p-type compound semiconductor material (Layer 36 includes the compound InGaAs which is a semiconducting material).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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