DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
Examiner states for the record that no Information Disclosure Statement is presently filed in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (Pub. No. US 2008/0025129) in view of Aichelmann, Jr. (U.S. Patent No. 5,150,328).
Claim 26:
Bartley et al. disclose a memory system, comprising:
a plurality of logic units connected with one another in series to form a chain [fig. 8 – chained memory chips 54], each of the logic units has an identifier [par. 0091 – “FIG. 5A shows an exemplary address/command word 120 transmitted on address/command bus 58. Address/command word 120, in the embodiment shown in FIG. 5A comprises a chip ID 121, a command 122, a packet number 123, and an address 124. Memory controller 52 knows which memory chip 54 in a particular daisy chain of memory chips 47 a particular piece of data is to be written to or read from. Chip ID 121 identifies which memory chip 54 in a particular daisy chain of memory chips 47 the address command word 120 is intended for, and the chip ID 121 is written by memory controller 52 when the address/command word 120 is sent from memory controller 52.”], a clock port [fig. 8; par. 0137 – “Bus clocks 60 are brought onto or driven from memory 52 at bus clock port 33 (one shown referenced in FIG. 8).”], an input data port and an output data port [fig. 8; par. 0136 – “Data words 130 (data words shown in FIGS. 7B and 7C) are driven onto data bus 59A at data bus port 32 (one shown referenced in FIG. 8) by memory controller 52 for writing into a memory chip 54.”], wherein the output data ports of the corresponding one of the logic units are coupled to the input data ports of an adjacent one of the logic units [fig. 8 – chained memory chips 54]; and
a host controller, coupled to the input data ports of the first logic unit of the logic units, and coupled to the output data ports of the last logic unit [fig. 8 – Memory controller coupled to input of first chip 54A and output of last chip 54M].
However, Bartley et al. do not specifically disclose,
a plurality of input data ports and a plurality of output data ports,
In the same field of endeavor, Aichelmann, Jr. discloses,
a plurality of input data ports and a plurality of output data ports [column 5, line 63, column 6, line 5 – “Typically, there may be fewer data lines 40 than address lines 17. Memory chip 13 is provided with the data port 21 in the event that the memory chip is desired to be used in a high-speed application, where external I/O circuits dedicated to this data port are provided. Data port 21, however, need not be used. Instead, in a feature of the present invention, data may be read into and out of the memory chip 13 through the address port 23 of the memory chip. In this way, the address port may also serve as an alternate data port for the memory array chip.”],
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Bartley et al. to include using the address port as an alternate data port, as taught by Aichelmann, Jr. in order to improve reliability by providing a redundant data line.
Allowable Subject Matter
Claims 1-25 allowed.
The following is an examiner’s statement of reasons for allowance:
Chained logic units is generally known. However, the prior art does not adequately disclose chained logic units in conjunction with logic unit identifier enumeration, as claimed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abraham et al. (Pub. No. US 2012/0109896) disclose, “The bus 220 can have various types of bus structures including, but not limited to, bus structures related to Open NAND Flash Interface (ONFI), Compact Flash Interface, Multimedia Card (MMC), Secure Digital (SD), CE-ATA, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).” … “As illustrated, a daisy chain configuration can be created between the memory devices 630-0, 630-1, 630-2, and 630-3. In this example, the enable input pin 639-0 of device 630-0 and the enable output pin 641-3 of device 630-3 are not connected (NC). The enable input pins 639 of the other devices are connected to the enable output pin 641 of the previous device in a daisy chain configuration as shown in FIG. 6.” [pars. 0022, 0042]
Webb et al. (Pub. No. US 2015/0378814) disclose, “An apparatus comprising: a first extensible non-volatile memory (NVM) hub (EN hub) comprising: an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller comprising command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing comprising enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.” [claim 1]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
10 January 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139