Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Actions
2. Claims 1-8 are pending.
Response to Arguments
3. Applicant's arguments filed on 12/29/2025 have been fully considered but they are not persuasive.
4. Applicant’s argument states that Applicant’s argument Neither Janardhanan nor Ballard teach an aggregation switch coupled to a ring along with servers,
an aggregation switch coupled to a ring along with servers. The Examiner relies on Ballard to provide the teaching of a "ring" network. However, Ballard's ring is fundamentally different from the claimed architecture. Ballard's Figure 2 and Claim 6. In Ballard, the ToR switch acts as the terminus, or aggregator for the server ring. However, Ballard does not teach or suggest a ring that includes an aggregation switch as a member of the ring itself.
In response,
Examiner respectfully disagrees with the applicant’s argument. First the examiner would like to point out that “a ring that includes an aggregation switch as a member of the ring itself” limitation finds no support in the claim language and should not be imported.
Ballard expressly discloses an aggregation switch coupled to a ring topology with servers. Ballard Fig. 2 and paragraph [0028] explicitly teaches servers 202-208 are connected in a series between the first and second ToR server ports to from a ring topology network. The ToR switch (220) connects to both ends of this series-connected server ring via lines 260 and 268. The ToR switch’s ports 233 and 232 serve as the two endpoints of the ring. Thus, the ToR switch (aggregation switch) is directly coupled to the ring topology. The servers are also couple to the ring as (intermediate series nodes). This clearly shows an aggregation switch coupled to a ring along with servers. [0029] confirms the ToR switch “may act as a switch that includes multiple ports to facilitate transmission data packets from one of the stacked serves of the formed ring typology to an outside network” – i.e., it aggregates traffic from the ring to external networks. [0031] further discloses how the ToR switch optimized bandwidth using a minimal number of Tor server poots for the ring. Ballard full teaches an aggregation switch 220 coupled to a ring topology formed by series-connected servers (202-208), where the switch provides the ring’s endpoints and aggregates traffic to outside networks. (see also para. [0027]-[0031] and [0038]-[0040]). Therefore, for the above reasons, Examiner believes that rejection of the last Office action was proper and within their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-l] Interpretation of Claims-Broadest Reasonable Interpretation.
5. Applicant’s argument states that to establish a prima facie case of obviousness, the Examiner must provide a reason why a person of ordinary skill in the art would have been motivated to combine the references to arrive at the claimed invention.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071,5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Janardhanan and include the aggregation switch, the first network hardware component and the second network hardware component are coupled together in a ring architecture using the teaching of Ballard. One would have been motivated to do so in order to facilitate efficient packet transmission and to reduce cost, latency and Improve bandwidth efficiency (see Ballard’s para.[0029] and [0031]).
Response to Amendment
6. Applicant's amendments filed on 12/29/2025 have been fully considered but are moot in view of new ground(s) of rejection
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AlA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of pre-AlA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
9. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Janardhanan et al. (US 20140029618 A1) hereinafter Janardhanan in view of Ballard et al. (US 20200366625 A1) hereinafter Ballard and further in view of Thacker et al. (US 20130188486 A1) hereinafter Thacker.
Regarding claim 1, Janardhanan discloses a system for configuring a data center (Fig. 1 [0006]), comprising:
an aggregation switch, configured to receive data communicated over a network (para. [0021] aggregation switches 106AD may facilitate routing between the racks 102A-N. Network 100 may include a number of VLANs in a variety of configurations),
a plurality of network hardware components, comprising a first network hardware component and a second network hardware component (para. [0017], FIG. 1 shows an information handling system with a network 100 such as might be used in a data center. Network 100 may include a plurality of racks 102A-N, and each rack, like rack 102A, may include a plurality of servers and one a plurality of switches, such as top-of-rack switches (TORs) 104A-N, like TOR 104A. Each of the TORs 104A-N may layer-two devices capable of implementing various networking protocols, including the Transparent Interconnect of Lots of Links (TRILL) networking protocol, which is a protocol defined by the Internet Engineering Task Force. TRILL allows layer 2 link state routing. Additionally, each of TORS 104A-N may act as a bridging device, and in some embodiments, TORs 104A-N may act as routing bridge devices (RBridges), which are devices that may implement a TRILL network. TORs 104A-N may provide for intra-rack switching); and
a plurality of servers housed in a rack, each server having at least one of the plurality of network hardware components (para. [002] aggregation switches 106A-D may facilitate routing between the racks 102A-N. Network 100 may include a number of VLANs in a variety of configurations. For example, a first VLAN may be present on a server or servers in rack 102A. Or, the first VLAN may include servers on racks 102A and 102C. Other VLANS may exist in network 100 on the servers on these racks or on other racks. For example, the first VLAN may be present on servers in racks 102A and 102C and a second VLAN may be present on rack 102B),
wherein the first network hardware component is associated with a first server of the plurality of servers and the second network hardware component is associated with a second server of the plurality of servers [0021], a first VLAN may be present on a server or servers in rack 102A. Or, the first VLAN may include servers on racks 102A and 102C. Other VLANS may exist in network 100 on the servers on these racks or on other racks. For example, the first VLAN may be present on servers in racks 102A and 102C and second VLAN may be present on rack 102B);
wherein the first network hardware component is coupled to the aggregation switch and to the second network hardware component and the second network hardware component is coupled to the aggregation switch ( para. [0022], a first VLAN server (a server that is part of the first VLAN) on rack 102A may need to communicate with a first VLAN server on rack 102C. This may be done when the rack 102A first VLAN server sends a packet to the TOR 104A on rack 102A. TOR 104A may recognize from a destination MAC address that the packet is to be sent to rack 102C and may encapsulate the packet with an identifier for TOR 104C as the egress RBridge address and an identifier for TOR 104A as the ingress RBridge address in the packet's header. As part of the TRILL protocol, when a packet enters the TRILL network at an RBridge, the packet is encapsulated with a TRILL header. The TRILL header contains an identifier of the RBridge by which the packet entered the TRILL network, called the ingress RBridge address, and also an identifier of the RBridge by which the packet should exit the TRILL network, called the egress RBridge address. For the encapsulated packet to reach TOR 104C from TOR 104A, the packet may be forwarded to one of aggregation switches 106A-D. The determination as to which of aggregation switches 106A-D receives the packet may be made in a variety of ways).
Janardhanan may not explicitly disclose wherein the aggregation switch, the first network hardware component and the second network hardware component are coupled together in a ring architecture.
However, Ballard discloses wherein the aggregation switch, the first network hardware component and the second network hardware component are coupled together in a ring architecture configured to transport data packets between the servers and the network (para. [0028] [0032] the servers 202-208 are stacked together and are connected in series between the first and second TOR server ports to form a ring topology network. A dynamic aggregator 270 of the TOR server may be configured to create a MCLAG 280 across the formed ring topology network …[0029] The TOR server may act as a switch that includes multiple ports to facilitate transmission of data packets from one of the stacked servers of the formed ring topology to an outside network, or to facilitate reception of data packets from the outside network to the stacked server as its final destination), (see also response to argument above))
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Janardhanan and include the aggregation switch, the first network hardware component and the second network hardware component are coupled together in a ring architecture using the teaching of Ballard. One would have been motivated to do so in order to facilitate efficient packet transmission and to reduce cost, latency and Improve bandwidth efficiency (see Ballard’s para.[0029] and [0031]).
Janardhanan in view of Ballard discloses claim 1 as recited above. Janardhanan in view of Ballard may not explicitly disclose the network without an intervening top-or-rack (ToR) switch.
However, Thacker discloses the network without an intervening top-or-rack (ToR) switch (para, [0031] by organizing the data center 100 in this fashion--rather than the typical approach which uses expensive top-of-rack (TOR) switches--the data center can benefit from improved bandwidth for traffic that stays within a half rack/nodal group while avoiding the costs of TOR switches.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Janardhanan in view of Ballard and include the network without an intervening top-or-rack (ToR) switch using the teaching of Thacker. One would have been motivated to do so in order to provide large datacenter environment for the circuit-based digital communications, so as to reduce the cost of the network and to gain performance efficiencies.
Regarding claim 2, claim 1 is incorporated. Janardhanan further discloses, wherein at least the first network hardware component includes a first virtual router and the second network hardware component include a second virtual router (para.[0028]-[0030], a first server on rack 102A may need to communicate with a second server on rack 102C. For typical routing, the servers may all be configured to use a default gateway which may be provided by the virtual RBridge using the same anycast MAC address as anycast MAC virtual IP instance 204. The first server may send out an ARP packet to the default gateway. The packet may be a broadcast packet, and thus may reach all of aggregation switches 106A-D. Since each of the aggregation switches can perform the routing functions of the default gateway, and each may receive the broadcast ARP packet, all aggregation switches 106A-D may recognize the ARP request).
Regarding claim 3, claim 2 is incorporated. Janardhanan further discloses wherein each virtual router receives routes from the other virtual router and generates a routing table based on the routes received (see at least para. [0028] –[0030])
Regarding claim 4, claim 1 is incorporated. Janardhanan further discloses wherein each virtual router advertises routes to the aggregation switch [0026] Additionally, FIG. 2 depicts an anycast MAC virtual IP instance 204. Anycast MAC virtual IP instance 204 is a single virtual IP instance running on a plurality of aggregation switches, such as aggregation switches 106A-D. The single virtual IP instance may be associated with a specific IP address which may be a default gateway for a particular VLAN, and may be a VRRP instance. Anycast MAC virtual IP instance 204 may act as a single virtual router for all of the aggregation switches 106A-D. In practice, anycast MAC virtual IP instance 204 may function as follows. A server associated with a first VLAN on rack 102A may need to communicate with a server on a second VLAN on rack 102B. The server on rack 102A may perform address resolution protocol (ARP) resolution on its default gateway IP address, which may be broadcast to aggregation switches 106A-D).
Regarding claim 5, claim 1 is incorporated. Janardhanan further discloses wherein only the first and second network hardware components have virtual routers, configured to advertise routes to the aggregation switch, and the remaining network hardware components of the plurality of network hardware components have routing agents ( see at least para.[0026, ]0032]-[0034] and Figs 1-2).
Regarding claim 6, claim 1 is incorporated. Janardhanan further discloses a third network hardware component associated with a third server, the third network hardware component coupled to the first network hardware component and the second hardware network component ( see at least para. ]0032]-[0034] and Figs 1-2).
Regarding claim 7, claim 1 is incorporated. Janardhanan may not explicitly disclose wherein a given network hardware component has a central processing unit core distinct from processing devices of a given server that includes the given network hardware component. However, Ballard discloses wherein a given network hardware component has a central processing unit core distinct from processing devices of a given server that includes the given network hardware component (see at least para [0033]-[0034], [0037]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Janardhanan and include wherein a given network hardware component has a central processing unit core distinct from processing devices of a given server that includes the given network hardware component using the teaching of Ballard. One would have been motivated to do so in order to facilitate transmission of data packets from one of the stacked servers of the formed ring topology to an outside network.
Regarding claim 8, claim 1 is incorporated. Janardhanan may not explicitly disclose wherein each network hardware component comprises a network interface controller or card, or an infrastructure processing unit. However, Ballard discloses wherein each network hardware component comprises a network interface controller or card, or an infrastructure processing unit ( see para. [0028], [0033], a network interface controller or card).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Janardhanan and include wherein each network hardware component comprises a network interface controller or card, or an infrastructure processing unit using the teaching of Ballard. One would have been motivated to do so in order to facilitate transmission of data packets from one of the stacked servers of the formed ring topology to an outside network.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kidest Mendaye whose telephone number is (571)272-2603. The examiner can normally be reached on Monday through Friday 7:00 am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ario Etienne can be reached on (571) 272-4001. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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04/28/2026
/KIDEST MENDAYE/
Examiner, Art Unit 2457
/ARIO ETIENNE/Supervisory Patent Examiner, Art Unit 2457
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