DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 5-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srinidhi Embar et al. (US 10,868,500).
In regard to Claim 1:
Srinidhi Embar discloses, in Figure 2, a Doherty power amplifier comprising:
a) an input (Figure 1: 102);
b) an output (Figures 1 and 2: 170);
c) a main power amplification device (136) connected between the input (102) and the output (170);
d) an auxiliary power amplification device (156) connected between the input (102) and the output (170), and arranged in parallel with the main power amplification device (135 and 156 are connected in parallel);
e) a main side output matching network (OMN) (240) connected between the main power amplification device (136) and the output (170); and
f) an auxiliary side OMN (260) connected between the auxiliary power amplification device (156) and the output (170);
wherein the main side (240) and auxiliary side (260) OMNs each comprise a first shunted T junction (270, Column 11: lines 11-17), the first shunted T junctions facilitating creation of multiple transmission zeros (TZ) as well as impedance conversion (Column 12: lines 14-34).
In regard to Claim 2:
Srinidhi Embar discloses, in Figure 2, the Doherty power amplifier of claim 1, wherein the first shunted T junction (270) of the main side OMN (240) or the auxiliary side OMN (260) facilitates generation of two TZs in a corresponding one of the main side and auxiliary side OMNs (Column 12: lines 14-34).
In regard to Claim 5:
Srinidhi Embar discloses, in Figure 1, the Doherty power amplifier of claim 1, further comprising a stub-loaded power divider (120) connected between the input (102), and the main (136) and auxiliary (156) power amplification devices (Column 3: lines 48-61).
In regard to Claim 6:
Srinidhi Embar discloses, in Figure 1, the Doherty power amplifier of claim 5, further comprising a main side input impedance matching network (IMN) (134) connected between the stub-loaded power divider (120) and the main power amplification device (136), and an auxiliary side IMN (154) connected between the stub-loaded power divider (120) and the auxiliary power amplification device (156).
In regard to Claim 7:
Srinidhi Embar discloses, in Figure 2, the Doherty power amplifier of claim 6, further comprising a phase compensation circuit located in the auxiliary side IMN (154, Column 10: lines 59-66).
In regard to Claim 8:
Srinidhi Embar discloses, in Figure 2, the Doherty power amplifier of claim 1, wherein the first shunted T junction (270 of 240) is connected to a drain of a corresponding one of the main (136 drain) and auxiliary power amplification devices.
In regard to Claim 9:
Srinidhi Embar discloses, in Figure 2, the Doherty power amplifier of claim 1, wherein input impedances of the main (136) and auxiliary (156) power amplification devices are complex impedances (Column 3: lines 64-67 and Column 4: lines 1-8), and a load impedance (106) of the Doherty power amplifier is a real impedance (Column 3: lines 3-17).
Allowable Subject Matter
Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2006/0145757) discloses a power amplifying apparatus includes a Doherty amplifier having a carrier amplifier and a peaking amplifier connected in parallel, each having an input/output matching circuit and an asymmetric power driver for driving the carrier amplifier and the peaking amplifier using an asymmetric power driver.
Boumaiza et al. (US 2014/0035681) discloses a method and system for designing and implementing a reconfigurable Doherty amplifier system are disclosed. In one embodiment, a design method includes determining, using a processor, a first set of ABCD transmission parameters of a first output compensation network in a main path of a Doherty amplifier for the case where an auxiliary amplifier of the Doherty amplifier is off.
Seneviratne et al. (US 2015/0091651) discloses a wideband Doherty amplifier includes Doherty amplifier circuitry and a wideband combining network. The wideband combining network includes a wideband quarter-wave impedance transformer that includes a quarter-wave impedance transformer and compensation circuitry connected in parallel with the quarter-wave impedance transformer at a low-impedance end of the quarter-wave impedance transformer. The compensation circuitry is configured to reduce a total quality factor of the wideband quarter-wave impedance transformer as compared to a quality factor of the quarter-wave impedance transformer, which in turn increases a bandwidth of the wideband quarter-wave impedance transformer, and thus a bandwidth of the wideband Doherty amplifier.
Ma et al. (US 9,948,246) discloses a wideband power amplifier includes a set of amplifiers connected in parallel to amplify signals from input ports of the amplifiers, a matching network configured to match the signals amplified by the amplifiers with predetermined load values, the matching network having a first impedance frequency response as a monotonically decreasing function of frequency of the amplified signals in a target operation frequency range, a converter network configured to convert the signals matched by the matching network, and an impedance flattening network having a second impedance frequency response as a monotonically increasing function of frequency of the amplified signals in the target operation frequency range.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN W POOS/Primary Examiner, Art Unit 2843
Prosecution Insights