Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Kocev et al. (United States Patent Application Publication US 2012/0102344), hereinafter Kocev, in view of George-Kelso et al. (United States Patent Application Publication US 2014/0015505), hereinafter George-Kelso.
Regarding claim 1, Kocev teaches a system on chip (SoC) for receiving an external supply voltage (FIG. 1 “Vsupply” [0025] “FIG. 1 is a block diagram of one embodiment of an integrated circuit (IC) coupled to a memory…IC2 is a system on a chip (SOC) type processor having a number of processor cores 11 (e.g., 11-1, 11-2, and so forth).” As shown in FIG. 1, the IC, which is a SOC type processor, receives Vsupply from an outside of the IC.),
the SoC comprising: a core having a clock gating state in which supplying a clock signal from the outside is suspended ([0033] “IC2 includes a phase-locked loop (PLL) 4 coupled to receive a system clock signal. PLL 4 may distribute corresponding clock signals to each of processor cores 11…a functional unit is to be clock-gated. PLL 4 may respond to such signal by inhibiting the clock signal from being provided to the given functional unit.” The PLL receives a clock signal as shown in FIG. 1 and provides clock signals to cores. As the core is clock gated, the PLL inhibits or suspend the clock signal to the core.); and
a power manager configured to generate a supply voltage based on the external supply voltage and provide the supply voltage to the core ([0034] “IC 2 also includes voltage regulator 5. Voltage regulator 5 may provide an operating voltage to each of processor cores 11, to GPU 14, I/O unit 13, and the various functional units of north bridge 12. For some units (e.g., processor cores 11), the operating voltage may be varied by voltage regulator 5 in accordance with the signals SetV[M:0] generated by power management unit 20.” As discussed above, the voltage regulator receives the voltage, Vssuply, to supply Vdd to cores.)
However, Kocev does not explicitly teach wherein the power manager is further configured to increase the supply voltage every time the supply voltage provided to the core having the clock gating state is lower than a target voltage for maintaining the clock gating state.
George-Kelso teaches wherein the power manager is further configured to increase the supply voltage every time the supply voltage provided to the core having the clock gating state is lower than a target voltage for maintaining the clock gating state ([0032] “In low power mode the LDO 190 is enabled and the fast clock 114 and pulse control 112 are disabled.” [0037] “The output voltage sensor 270 is used by the slow control unit 218 to detect if the output voltage Vout drops too close to a predetermined threshold, set above the retention threshold, at which point the slow control 218 activates the switching element 230 to provide current transfer from the voltage source (such as a battery) 220 to the storage elements 250, 260, raising the output voltage above the threshold. The size of the current pulse is determined solely by the pulse duration.” [0038] “In order to comply with the ripple requirements in low current modes, the slow control circuit 218 must supply pulses of less than or equal to the maximum pulse duration at an average rate to match the load current requirements.” In low power mode, the fast clock, which provide clock signals are disable, the output voltage sensor detects the output voltage, which is further compared to a retention threshold. Then, the output voltage is raised above the threshold. Furthermore, since the retention voltage is a very low voltage, which is only to retain their state, George-Kelso suggests that the threshold must be lower than other voltages supplied to the circuitry of George-Kelso. As discussed above in [0036]-[0038], the ripple requirement that supply voltage above the threshold is performed also in the low power mode, which the clock signal is disabled or gated.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kocev by incorporating the teaching of George-Kelso of increasing the supply voltage provided to the core having the clock gating state every time the supply voltage is lower than a target voltage for maintaining the clock gating state, and wherein the target voltage is lower than the external supply voltage. As recognized by George-Kelso, in order for the SoC and DRAM to retain their state, a retention voltage must be provided ([0036]-[0037]). When the supply voltage to the SoC and DRAM drops below the retention voltage, the states of the SoC and the DRAM is lost. By increasing the supply voltage when the supply voltage drops below a threshold, the supply voltage to the SoC and the DRAM can be maintained above the retention voltage. Therefore, it would be advantageous to incorporate the teaching of George-Kelso in order not to lose states of the SoC in the low power mode or the clock-gated state.
Regarding claim 2, Kocev in view of George-Kelso teaches all the limitations of the SoC of claim 1, as discussed above.
George-Kelso further teaches wherein the power manager is further configured to determine an increased amount of the supply voltage provided to the core having the clock gating state, according to a difference between the target voltage and the supply voltage ([0037] “The output voltage sensor 270 is used by the slow control unit 218 to detect if the output voltage Vout drops too close to a predetermined threshold, set above the retention threshold, at which point the slow control 218 activates the switching element 230 to provide current transfer from the voltage source (such as a battery) 220 to the storage elements 250, 260, raising the output voltage above the threshold. The size of the current pulse is determined solely by the pulse duration.” When determining that the output voltage drops too close to a predetermined threshold or below threshold, by comparing two voltages, difference or dissimilarity between two voltages are determined. Based on the difference between the voltages, the amount of the increased output voltage is determined to be above the threshold).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kocev in view of George-Kelso as applied to claim 1 above, and further in view of Lundberg.
Regarding claim 3, Kocev in view of George-Kelso teaches all the limitations of the SoC of claim 1, as discussed above.
George-Kelso further teaches a voltage regulator configured to change respective logic levels of the plurality of control signals according to a difference level equal to a difference between the supply voltage provided to the core having the clock gating state and the target voltage ([0033] “For low power mode, slow control unit 218 is enabled and controls the switching circuitry 230 while the fast clock 214 and pulse control unit 212 are disabled.” [0037] “The output voltage sensor 270 is used by the slow control unit 218 to detect if the output voltage Vout drops too close to a predetermined threshold, set above the retention threshold, at which point the slow control 218 activates the switching element 230 to provide current transfer from the voltage source (such as a battery) 220 to the storage elements 250, 260, raising the output voltage above the threshold. The size of the current pulse is determined solely by the pulse duration.” When the switching regulator changes power modes, control signals of the switching regulator change slow control unit and switching circuitry, such as pulses, “disable”, and “enable.” Furthermore, the control signals to switch to the low power mode is based on the difference between the output voltage and the threshold by comparing two voltages.).
However, Kocev in view of George-Kelso does not teach a plurality of header switch circuits configured to deliver, as the supply voltage, a voltage reduced from the external supply voltage to the core in response to a plurality of control signals.
Lundberg teaches a plurality of header switch circuits configured to deliver, as the supply voltage, a voltage reduced from the external supply voltage to the core in response to a plurality of control signals ([Col. 13 Lines 42-55] “Each side block 301 further includes inputs coupled to the global supply bus 109 providing VDD0 and has outputs coupled to the gated supply bus 206 developing VDD1. In general, each bit of the PG_CNTRL<16:0> turns on a corresponding subset of devices with current terminals coupled between VDD0 and VDD1 and thus determines the relative current capacity or resistance between the supply voltages.” By control signals to turn on or off PMOS transistors, the VDD0, which is the external supply voltage, is regulated to the VDD1, which is the supply voltage to the core.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kocev in view of George-Kelso by incorporating the teaching of Lundberg of a plurality of header switch circuits configured to deliver, as the supply voltage, a voltage reduced from the external supply voltage to the core in response to a plurality of control signals. As recognized by Lundberg, in conventional CMOS device configuration, leakage current can consume energy (“BACKGROUND OF THE INENTION”). Since the PMOS transistors are less leaky compared to NMOS transistors, by using header switch circuits, which uses PMOS transistors, the power consumption due to the leakage current can be reduced. Therefore, it would be advantageous to incorporate the teaching of Lundberg of a plurality of header switch circuits configured to deliver, as the supply voltage, a voltage reduced from the external supply voltage to the core in response to a plurality of control signals in order to reduce power consumption.
Allowable Subject Matter
Claims 6-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Kocev et al. (United States Patent Application Publication US 2012/0102344) teaches switching states of cores between active state, clock-gated state, and power gated state based on idle time. However, Kocev does not teach “wherein the plurality of header switch groups comprises a first header switch group, a first header switch circuit of the first header switch group comprises a first number of header switches, and a second header switch circuit of the first header switch group comprises a second number of header switches different from the first number.”
Lundberg (United States Patent US 9450580) teaches power gating systems including P-type transistors to adjust supply voltages to cores. However, Lundberg does not teach “wherein the plurality of header switch groups comprises a first header switch group, a first header switch circuit of the first header switch group comprises a first number of header switches, and a second header switch circuit of the first header switch group comprises a second number of header switches different from the first number.”
George-Kelso (United States Patent Application Publication US 2014/00115505) teaches to detect an output voltage to drops close to a threshold and raise the supply voltage above the threshold. However, George-Kelso does not teach “wherein the plurality of header switch groups comprises a first header switch group, a first header switch circuit of the first header switch group comprises a first number of header switches, and a second header switch circuit of the first header switch group comprises a second number of header switches different from the first number.”
Branover et al. (United States Patent Application Publication US 2008/0276026) teaches voltage regulators to control supply voltages to processor cores based on difference between VDD and VSS. However, Branover does not teach “wherein the plurality of header switch groups comprises a first header switch group, a first header switch circuit of the first header switch group comprises a first number of header switches, and a second header switch circuit of the first header switch group comprises a second number of header switches different from the first number.”
Rangarajan et al. (United States Patent Application Publication US 2019/0065359) teaches detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail. However, Rangarajan does not teach “wherein the plurality of header switch groups comprises a first header switch group, a first header switch circuit of the first header switch group comprises a first number of header switches, and a second header switch circuit of the first header switch group comprises a second number of header switches different from the first number.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Kocev et al. (United States Patent Application Publication US 2012/0102344) teaches switching states of cores between active state, clock-gated state, and power gated state based on idle time. However, Kocev does not teach “wherein each of the plurality of header switch circuits comprises a different number of header switches from each other of the plurality of header switch circuits.”
Lundberg (United States Patent US 9450580) teaches power gating systems including P-type transistors to adjust supply voltages to cores. However, Lundberg does not teach “wherein each of the plurality of header switch circuits comprises a different number of header switches from each other of the plurality of header switch circuits.”
George-Kelso (United States Patent Application Publication US 2014/00115505) teaches to detect an output voltage to drops close to a threshold and raise the supply voltage above the threshold. However, George-Kelso does not teach “wherein each of the plurality of header switch circuits comprises a different number of header switches from each other of the plurality of header switch circuits.”
Branover et al. (United States Patent Application Publication US 2008/0276026) teaches voltage regulators to control supply voltages to processor cores based on difference between VDD and VSS. However, Branover does not teach “wherein each of the plurality of header switch circuits comprises a different number of header switches from each other of the plurality of header switch circuits.”
Rangarajan et al. (United States Patent Application Publication US 2019/0065359) teaches detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail. However, Rangarajan does not teach “wherein each of the plurality of header switch circuits comprises a different number of header switches from each other of the plurality of header switch circuits.”
Response to Arguments
Applicant’s arguments, see Remarks, filed 2/26/2026, with respect to “Rejection Under 35 U.S.C. §112” have been fully considered and are persuasive. The rejection of claims 1-5 and 19 under 35 U.S.C. §112(b) has been withdrawn.
Applicant’s arguments, see Remarks, filed 2/26/2026, with respect to “Rejections Under 35 U.S.C. §§ 102 and 103” have been fully considered and are persuasive. The rejection of claims 6 and 11 under 35 U.S.C. § 102(a)(2) and claims 7-10, 12-20 under 35 U.S.C. § 103 has been withdrawn.
Applicant's arguments filed 2/26/2026 with respect to the rejection of claims 1-5 under 35 U.S.C. § 103 have been fully considered but they are not persuasive.
Applicant argues:
George-Kelso is cited as allegedly disclosing these features. Applicant respectfully disagrees. Paragraph [0032] of George-Kelso discloses that according to a related method, in a lower power mode the "LDO 190 is enabled and the fast clock 114 and pulse control 112 are disabled." Paragraph [0037] of George-Kelso discloses detecting if an output voltage drops "too close to a predetermined threshold, set above the retention threshold, at which point the slow control 218 activates the switching element 230 to provide current transfer from the voltage source (such as a battery) 220 to the storage elements 250, 260, raising the output voltage above the threshold." However, George-Kelso does not teach or suggest a clock gating state, or a target voltage for maintaining the clock gating state.
Page 13
Examiner respectfully disagrees with applicant’s argument that George-Kelso does not teach or suggest a clock gating state, or a target voltage for maintaining the clock gating state. As applicant recognizes, George-Kelso teaches that “the fast clock 114 and pulse control 112 are disabled” in [0032]. George-Kelso further teaches that “For low power mode, slow control unit 218 is enabled and controls the switching circuitry 230 while the fast clock 214 and pulse control unit 212 are disabled” in [0033]. Thus, in the low power mode, the clock is disabled or gated. George-Kelso further teaches that “The output voltage sensor 270 is used by the slow control unit 218 to detect if the output voltage Vout drops too close to a predetermined threshold, set above the retention threshold, at which point the slow control 218 activates the switching element 230 to provide current transfer from the voltage source (such as a battery) 220 to the storage elements 250, 260, raising the output voltage above the threshold. The size of the current pulse is determined solely by the pulse duration” in [0037] and “In order to comply with the ripple requirements in low current modes, the slow control circuit 218 must supply pulses of less than or equal to the maximum pulse duration at an average rate to match the load current requirements” in [0038]. Thus, George-Kelso increase the output voltage Vout, such that the output voltage is above the retention threshold. George-Kelso also teaches that, in the low power mode that the clock is gated, the pulses are also supplied, which is to raise the output voltage above the threshold. Thus, George-Kelso suggests that, in order to maintain or retain the state of the memory in the low power mode, that disables the clock, the output voltage is increased above the threshold when the output voltage is too close to the threshold.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HYUN SOO KIM/Examiner, Art Unit 2176