DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-5 and 8-11 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/586,938.
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application is broader than claim 1 of copending Application No. 18/586,938 by omitting other features recited in claim 1 such as “a third voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a third bias applied to the gate of the second FET; and a second switch between the third voltage divider resistor circuit and the power supply, and configured to switch a second electrical connection between the power supply and the third voltage divider resistor circuit, wherein a resistance value of each of a plurality of resistors in the third voltage divider resistor circuit is less than the resistance value of each of the plurality of resistors in the second voltage divider resistor circuit, and wherein a voltage division ratio of the resistors in the second voltage divider resistor circuit is the same as a voltage division ratio of the resistors in the third voltage divider resistor circuit.”
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application 18/584,365
Copending Application 18/586,938
1. An amplifier circuit comprising: an input terminal to which a signal is input; a first field effect transistor (FET) having a gate to which the signal input to the input terminal is applied; a second FET connected, together with the first FET, between a power supply and a reference potential; an output terminal between the second FET and a load, and that is configured to output an amplified signal; a first voltage divider resistor circuit configured to divide a potential difference between the power supply and the reference potential, and to generate a first bias applied to a gate of the second FET; and a first switch between the first voltage divider resistor circuit and the power supply, and that is configured to switch an electrical connection between the power supply and the first voltage divider resistor circuit, a second voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a second bias applied to the gate of the second FET,
wherein a source of the first FET is connected to a drain of the second FET, and wherein the first switch is configured to disconnect the electrical connection when an amplification operation by the first FET and the second FET is not performed, and wherein a resistance value of each of a plurality of resistors in the second voltage divider resistor circuit is greater than a resistance value of each of a plurality of resistors in the first voltage divider resistor circuit.
1. An amplifier circuit comprising: an input terminal to which a signal is input; a first field effect transistor (FET) having a gate to which the signal input to the input terminal is applied; a second FET connected, together with the first FET, between a power supply and a reference potential; an output terminal between the second FET and a load, and that is configured to output an amplified signal; a first voltage divider resistor circuit configured to divide a potential difference between the power supply and the reference potential, and to generate a first bias applied to a gate of the second FET; a first switch between the first voltage divider resistor circuit and the power supply, and configured to switch a first electrical connection between the power supply and the first voltage divider resistor circuit; a second voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a second bias applied to the gate of the second FET; a third voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a third bias applied to the gate of the second FET; and a second switch between the third voltage divider resistor circuit and the power supply, and configured to switch a second electrical connection between the power supply and the third voltage divider resistor circuit, wherein a drain of the first FET is connected to a source of the second FET, wherein a resistance value of each of a plurality of resistors in the second voltage divider resistor circuit is greater than a resistance value of each of a plurality of resistors in the first voltage divider resistor circuit, wherein a resistance value of each of a plurality of resistors in the third voltage divider resistor circuit is less than the resistance value of each of the plurality of resistors in the second voltage divider resistor circuit, and wherein a voltage division ratio of the resistors in the second voltage divider resistor circuit is the same as a voltage division ratio of the resistors in the third voltage divider resistor circuit.
2. The amplifier circuit according to Claim 1, wherein when transitioning from a state in which amplification operation is performed to a standby state in which amplification operation is not performed, the first switch is configured to disconnect the first electrical connection, and the second switch is configured to connect the second electrical connection, and wherein a predetermined time after transitioning to the standby state, the second switch is configured to disconnect the second electrical connection.
3. The amplifier circuit according to Claim 1, further comprising: a first diode connected in parallel to a resistor in the second voltage divider resistor circuit, wherein an anode of the first diode is connected to a power supply side of the resistor, and wherein a cathode of the first diode is connected to a reference potential side of the resistor.
5. The amplifier circuit according to Claim 1, further comprising: a first diode connected in parallel to a resistor in the second voltage divider resistor circuit, wherein an anode of the first diode is connected to a power supply side of the resistor, and wherein a cathode of the first diode is connected to a reference potential side of the resistor.
4. The amplifier circuit according to Claim 3, further comprising: a second diode connected in parallel to a resistor in the second voltage divider resistor circuit, wherein an anode of the second diode is connected to a reference potential side of the resistor, and wherein a cathode of the second diode is connected to a power supply side of the resistor.
7. The amplifier circuit according to Claim 1, further comprising: a second diode connected in parallel to a resistor in the second voltage divider resistor circuit, wherein an anode of the second diode is connected to a reference potential side of the resistor, and wherein a cathode of the second diode is connected to a power supply side of the resistor.
5. The amplifier circuit according to Claim 3, wherein the first diode is not connected to the resistor in the second voltage divider resistor circuit that is closest to the reference potential.
6. The amplifier circuit according to Claim 5, wherein the first diode is not connected to the resistor in the second voltage divider resistor circuit that is closest to the reference potential.
8. The amplifier circuit according to Claim 1, wherein a voltage value of the power supply fluctuates.
9. The amplifier circuit according to Claim 1, wherein a voltage value of the power supply fluctuates.
9. A power amplifier comprising: a driver-stage amplifier circuit comprising the amplifier circuit according to Claim 1; and a power-stage amplifier circuit, wherein the amplified signal output from the output terminal of the driver-stage amplifier circuit is input to the power-stage amplifier circuit.
10. A power amplifier comprising: a driver-stage amplifier circuit comprising the amplifier circuit according to Claim 1; and a power-stage amplifier circuit, wherein the amplified signal output from the output terminal of the driver-stage amplifier circuit is input to the power-stage amplifier circuit.
10. (Original) The power amplifier circuit according to Claim 9, wherein the power-stage amplifier circuit comprises a bipolar transistor.
11. (Original) The power amplifier circuit according to Claim 10, wherein the power- stage amplifier circuit comprises a bipolar transistor.
11. A communication device comprising a plurality of the power amplifiers according to Claim 9, wherein the plurality of the power amplifiers are configured to selectively perform an amplification operation according to a voltage supplied by a common power supply.
12. A communication device comprising a plurality of the power amplifiers according to Claim 11, wherein the plurality of the power amplifiers are configured to selectively perform an amplification operation according to a voltage supplied by a common power supply.
Allowable Subject Matter
Claims 6-7 would be allowable upon timely filing of a terminal disclaimer.
Response to Arguments
Applicant amended claim 1 incorporates the limitation of dependent claim 2. Although the limitations of claim 2 were previously found allowable over the prior art, the amended claim still recites subject matter that is not patentably distinct from claim 1 of the copending application, as shown above. Therefore, the obviousness double patenting rejection is still applicable. Applicant may overcome the rejection by filing a terminal disclaimer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
