CTNF 18/584,365 CTNF 91316 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of copending Application No. 18/586,938. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 1 of the instant application is broader than claim 1 of copending Application No. 18/586,938 by omitting other features recited in claim 1 such as “a second voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a second bias applied to the gate of the second FET; a third voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a third bias applied to the gate of the second FET; and a second switch between the third voltage divider resistor circuit and the power supply, and configured to switch a second electrical connection between the power supply and the third voltage divider resistor circuit, wherein a resistance value of each of a plurality of resistors in the second voltage divider resistor circuit is greater than a resistance value of each of a plurality of resistors in the first voltage divider resistor circuit, wherein a resistance value of each of a plurality of resistors in the third voltage divider resistor circuit is less than the resistance value of each of the plurality of resistors in the second voltage divider resistor circuit, and wherein a voltage division ratio of the resistors in the second voltage divider resistor circuit is the same as a voltage division ratio of the resistors in the third voltage divider resistor circuit.” This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. Instant Application 18/584,365 Copending Application 18/586,938 1. An amplifier circuit comprising: an input terminal to which a signal is input; a first field effect transistor (FET) having a gate to which the signal input to the input terminal is applied; a second FET connected, together with the first FET, between a power supply and a reference potential; an output terminal between the second FET and a load, and that is configured to output an amplified signal; a first voltage divider resistor circuit configured to divide a potential difference between the power supply and the reference potential, and to generate a first bias applied to a gate of the second FET; and a first switch between the first voltage divider resistor circuit and the power supply, and that is configured to switch an electrical connection between the power supply and the first voltage divider resistor circuit, wherein a source of the first FET is connected to a drain of the second FET, and wherein the first switch is configured to disconnect the electrical connection when an amplification operation by the first FET and the second FET is not performed. 1. An amplifier circuit comprising: an input terminal to which a signal is input; a first field effect transistor (FET) having a gate to which the signal input to the input terminal is applied; a second FET connected, together with the first FET, between a power supply and a reference potential; an output terminal between the second FET and a load, and that is configured to output an amplified signal; a first voltage divider resistor circuit configured to divide a potential difference between the power supply and the reference potential, and to generate a first bias applied to a gate of the second FET; a first switch between the first voltage divider resistor circuit and the power supply, and configured to switch a first electrical connection between the power supply and the first voltage divider resistor circuit; a second voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a second bias applied to the gate of the second FET; a third voltage divider resistor circuit configured to divide the potential difference between the power supply and the reference potential, and to generate a third bias applied to the gate of the second FET; and a second switch between the third voltage divider resistor circuit and the power supply, and configured to switch a second electrical connection between the power supply and the third voltage divider resistor circuit , wherein a source of the first FET is connected to a drain of the second FET, wherein a resistance value of each of a plurality of resistors in the second voltage divider resistor circuit is greater than a resistance value of each of a plurality of resistors in the first voltage divider resistor circuit, wherein a resistance value of each of a plurality of resistors in the third voltage divider resistor circuit is less than the resistance value of each of the plurality of resistors in the second voltage divider resistor circuit, and wherein a voltage division ratio of the resistors in the second voltage divider resistor circuit is the same as a voltage division ratio of the resistors in the third voltage divider resistor circuit. 2. The amplifier circuit according to Claim 1, wherein when transitioning from a state in which amplification operation is performed to a standby state in which amplification operation is not performed, the first switch is configured to disconnect the first electrical connection , and the second switch is configured to connect the second electrical connection, and wherein a predetermined time after transitioning to the standby state, the second switch is configured to disconnect the second electrical connection. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US 2011/0043284 and Zhao hereinafter) in view of Lin et al. (US 2007/0052472 and Lin hereinafter) . Regarding claim 1, Zhao discloses an amplifier circuit [fig. 3] comprising: an input terminal [terminal RFin] to which a signal [RFin] is input; a first field effect transistor (FET) [212] having a gate [gate 212] to which the signal input to the input terminal is applied; a second FET [214] connected, together with the first FET, between a power supply [vdd] and a reference potential [gnd]; an output terminal [terminal RFout] between the second FET and a load [218], and that is configured to output an amplified signal [amplified RF signal]; a first voltage divider resistor circuit [a resistor ladder formed by four resistors 252, 254, 256 and 258] configured to divide a potential difference [divide voltage difference vdd and gnd] between the power supply and the reference potential, and to generate a first bias [vbias2] applied to a gate of the second FET [gate 214]; and wherein a source of the first FET [source 212] is connected to a drain of the second FET [drain 214]. Zhao does not explicitly disclose a first switch between the first voltage divider resistor circuit and the power supply, and that is configured to switch an electrical connection between the power supply and the first voltage divider resistor circuit, and wherein the first switch is configured to disconnect the electrical connection when an amplification operation by the first FET and the second FET is not performed. However, Lin discloses voltage generating circuit [10, fig. 1] comprises a first switch [SW15] between the first voltage divider resistor circuit [a resistor ladder formed by resistors R1~R7] and a power supply [V0], and that is configured to switch an electrical connection between the power supply and the first voltage divider resistor circuit, and wherein the first switch is configured to disconnect [15 turn off] the electrical connection during the power-saving mode. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Zhao by incorporating switch between the first voltage divider resistor circuit and a power supply to connect /disconnect when amplification operation by the first FET and the second FET is performed/not performed as taught in Lin in order to reduce power consumption . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. in view of Lin et al . Regarding claim 8, Zhao in view of Lin discloses all the features with respect to claim 1 as indicated above. Zhao in view of Lin does not explicitly disclose wherein a voltage value of the power supply fluctuates. One of ordinary skill in the art would have been motivated to have used the claimed range since such a voltage range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/ experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990) . 07-21-aia AIA 4. Claim s 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. in view of Lin et al. further in view of Tahara et al. (US 2022/0368284 and Tahara hereinafter) . Regarding claim 9, Zhao in view of Lin discloses the amplifier circuit according to Claim 1 as indicated above. Zhao in view of Lin does not explicitly disclose a driver-stage amplifier circuit comprising the amplifier circuit; and a power-stage amplifier circuit, wherein the amplified signal output from the output terminal of the driver-stage amplifier circuit is input to the power-stage amplifier circuit. However, Tahara discloses [fig. 1] a driver-stage amplifier circuit [1] comprising amplifier circuit; and a power-stage amplifier circuit [2], wherein the amplified signal output from the output terminal of the driver-stage amplifier circuit [output 1] is input to the power-stage amplifier circuit [input 2]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Zhao in view of Lin by incorporating driver and power amplifier stage as taught in Tahara in order to enable suppression of the current flowing through the transistor of the final-stage amplifier. Regarding claim 10, Zhao in view of Lin further in view of Tahara discloses wherein the power-stage amplifier circuit comprises a bipolar transistor [par. 0047]. Regarding claim 11, Zhao in view of Lin further in view of Tahara discloses a communication device [300, fig. 2] comprising a plurality of the power amplifiers [10] according to Claim 9, wherein the plurality of the power amplifiers [1/2/3] are configured to selectively perform an amplification operation according to a voltage supplied [voltage supply at T3] by a common power supply [power supply at T3] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /METASEBIA T RETEBO/Primary Examiner, Art Unit 2836 Application/Control Number: 18/584,365 Page 2 Art Unit: 2836 Application/Control Number: 18/584,365 Page 3 Art Unit: 2836 Application/Control Number: 18/584,365 Page 4 Art Unit: 2836 Application/Control Number: 18/584,365 Page 5 Art Unit: 2836 Application/Control Number: 18/584,365 Page 6 Art Unit: 2836 Application/Control Number: 18/584,365 Page 7 Art Unit: 2836 Application/Control Number: 18/584,365 Page 8 Art Unit: 2836 Application/Control Number: 18/584,365 Page 9 Art Unit: 2836 Application/Control Number: 18/584,365 Page 10 Art Unit: 2836 Application/Control Number: 18/584,365 Page 11 Art Unit: 2836 Application/Control Number: 18/584,365 Page 12 Art Unit: 2836
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