Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
The examiner has considered the remarks provided by the applicant, provided on
February 26, 2026, for the drawing and claim objections on the non-final
rejection mailed on November 5, 2025. The applicant’s remarks and corrections
overcome the drawing and claim objections issued on the non-final rejection.
Therefore, the drawing and claim objections have been withdrawn.
Response to Arguments
Applicant's arguments filed on February 26, 2026 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach each and every element of claims 1, 8, and 15.
Applicant argues, “Hsing does not comprise ‘a multipurpose gate driver’.” Examiner respectfully disagrees. Hsing discloses, as shown in Fig. 2/3/4, a driving circuit (Db) whose output (DS) drives the gate of SWb.
Also, applicant argues, “Hsing's current-limiting circuits (180a-180d) primarily adjust resistance to limit current”. Examiner agrees that Hsing discloses that 180a-180d are current-limiting circuits, however Hsing explicitly teaches the driver (Db) which incorporates the current-limiting circuits (180a-180d) to output a signal (signal DS) to drive the gate of the switch (SWb).
Further, applicant argues, “There is no disclosure of an active element” and “Hsing does not disclose ‘a plurality of gate drive circuits each configured with a different combination of passive and/or active electrical components’.” Examiner respectfully disagrees. Examiner interprets “passive and/or active” as either ‘passive electrical components only’, ‘active electrical components only’, or ‘passive and active electrical components combined’. Therefore, Hsing discloses the resistors and diodes, which are passive electrical components, within each of the 180a-180d. Hsing clearly teaches the passive elements, which satisfies the claim feature of “passive and/or active”.
Additionally, applicant argues, “Hsing does not disclose ‘a plurality of gate drive circuits each configured with a different combination of passive and/or active electrical components’.” Examiner respectfully disagrees. Hsing discloses a plurality of gate drive circuits (180a-180d) each configured with a different combination of passive electrical components (180a configured with resistors (Ron1 & Roff1) and diode (D1); 180b configured with resistors (Ron2 & Roff2) and diode (D2); 180c configured with resistors (Ron3 & Roff3) and diode (D3); 180d configured with resistors (Ron4 & Roff4) and diode (D4)). Hsing clearly teaches “a plurality of gate drive circuits each configured with a different combination of passive and/or active electrical components”.
Further, applicant argues, “Hsing does not disclose ‘at least one switch arranged between the input and each of the plurality of gate drive circuits, the at least one switch is configured to switch between each of the plurality of gate drive circuits and thereby divert a drive signal to any one of the plurality of gate drive circuits’.” Examiner respectfully disagrees. Hsing discloses, as shown in Fig. 4, shows the switch circuit (124) arranged between the input signal (SRC) and each of the plurality of gate drive circuits (180a-180d), wherein the switch circuit (124) is configured to switch, shown in Fig. 4, and more closely in Fig. 3A & 3B, between each of the plurality of gate drive circuits and thereby divert a drive signal (PWM) to any one of the plurality of gate drive circuits (paragraph 0038).
Also, applicant argues, “Hsing does not disclose ‘the switch is configured to switch between the plurality of gate drive circuits based on the input signal received from the input’.” Examiner respectfully disagrees. Hsing discloses, as shown in Fig. 3A/3B, that the switch (124) is configured to switch between the plurality of gate drive circuits (signal from No to the plurality of gate drive circuit inputs (N1/N2/N3/N4) based on the input signal (SRC) received from the input.
Further, applicant argues, “there is no indication that each circuit includes an active driver element”. As stated above, examiner interprets the “passive and/or active electrical components” phrase as being only passive electrical components/elements. The applicant continues to argue the Hsing reference must have “active elements” which is inconsistent with the claim language, and the arguments are improperly narrowing the scope of the claim language, “and/or”. Under the broadest reasonable interpretation, Hsing’s “passive element” alone is sufficient to meet the “passive and/or active” limitation.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 8-11, and 15-16 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hsing et al. (US 20190074760 A1); hereinafter Hsing.
Regarding Claim 1, Hsing teaches a multipurpose gate driver (Fig. 4), comprising: an input (SRC) for receiving an input signal; a plurality of gate drive circuits (180a-180d) each configured with a different combination of passive and/or active electrical components (different resistive values, paragraph 0047); and at least one switch (124) arranged between the input and each of the plurality of gate drive circuits, the at least one switch configured to switch between each of the plurality of gate drive circuits and thereby divert a drive signal (PWM) to any one of the plurality of gate drive circuits, wherein the switch is configured to switch between the plurality of gate drive circuits based on the input signal received from the input.
Regarding Claim 3, Hsing teaches the multipurpose gate driver of claim 1, wherein the plurality of gate drive circuits are arranged on a single board (paragraph 0064).
Regarding Claim 4, Hsing teaches the multipurpose gate driver of claim 1, wherein the gate drive circuits are configured to modify and transmit the drive signal to a semiconductor device, wherein the semiconductor device includes at least one of an insulated-gate bipolar transistor(IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or an integrated gate-commutated thyristor (IGCT) [paragraph 0019; the semiconductor device is the metal-oxide-semiconductor field-effect transistor; examiner interprets 'or' as one of the items listed in the claim].
Regarding Claim 5, Hsing teaches the multipurpose gate driver of claim 4, wherein the multipurpose gate driver is communicatively coupled with a controller (122), the controller configured to output the drive signal to the input of the semiconductor device (IGBT, IGCT, MOSFET), wherein the controller receives the input signal in addition to a plurality of external input signals, and wherein the controller outputs the drive signal to the input of the semiconductor device (IGBT, IGCT, MOSFET) based on the input signal and the plurality of external input signals (Fig. 1/2/3/4; paragraphs 0019, 0037).
Regarding Claim 8, Hsing teaches a multipurpose power electronic switch system (Fig. 4), comprising: a multipurpose gate driver (Db) including: an input (SRC) for receiving at least one input signal, a plurality of gate drive circuits (180a-180d) each configured with a different combination of passive and/or active electrical components (different resistive values, paragraph 0047), and at least one switch (124) arranged between the input and each of the plurality of gate drive circuits, at least one switch configured to switch between each of the plurality of gate drive circuits and thereby divert a drive signal (PWM) to any one of the plurality of gate drive circuits, wherein the switch is configured to switch between the plurality of gate drive circuits based on the at least one input signal received from the input; and at least one input device configured to output the at least one input signal (output of 140).
Regarding Claim 9, Hsing teaches the system of claim 8, wherein the at least one input device includes a controller (122) configured to output a single signal (output of 122) as the at least one input signal to the at least one input of the multipurpose gate driver.
Regarding Claim 10, Hsing teaches the system of claim 9, wherein the controller is further configured to output digital selector signals to the at least one switch of the multipurpose gate driver.
Regarding Claim 11, Hsing teaches the system of claim 8, wherein the at least one input device includes a plurality of devices (180a-180d) each configured to independently output an input signal (output of 180a-180d) to the at least one input of the multipurpose gate driver.
Regarding Claim 15, Hsing teaches a method for providing a signal to an insulated-gate bipolar transistor (IGBT) [paragraph 0019], a metal-oxide-semiconductor field-effect transistor (MOSFET) [paragraph 0019], or integrated gate-commutated thyristor (IGCT), the method comprising: receiving a control signal (SRC) and a selector signal (PWM); transmitting the control signal to one of a plurality of gate drive circuits (180a-180d) via a switch (124), a position of the switch being based on the selector signal; modifying the control signal via the one gate drive circuit of the plurality of gate drive circuits to which the control signal is transmitted; and outputting, via the one gate drive circuit to which the control signal is transmitted, the modified control signal to the IGBT, MOSFET, or IGCT.
Regarding Claim 16, Hsing teaches the method of claim 15, wherein the IGBT, MOSFET, or IGCT are connected with a solid-state switch, and wherein the modified control signal output by the one gate drive circuit is configured to control a state of the solid-state switch.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hsing, in view of Alam et al. (US 10505538 B1); hereinafter Hsing, in view of Alam.
Regarding Claim 2, Hsing teaches the multipurpose gate driver of claim 1, but does not explicitly teach wherein the plurality of gate drive circuits includes at least one gate drive circuit comprising a combination of passive and/or active electrical components optimized for reduced voltage overshoot and at least one gate drive circuit comprising a combination of passive and/or active electrical components optimized for reduced turn off switching time.
However, Alam teaches the multipurpose gate driver (Fig. 3) of claim 1, wherein the plurality of gate drive circuits (32/40) includes at least one gate drive circuit comprising a combination of passive and/or active electrical components (40 includes combinations of resistors which are passive electrical components) optimized for reduced voltage overshoot (Column 1, line 51 to Column 2, line 3) and at least one gate drive circuit (32/40) comprising a combination of passive and/or active electrical components (40 includes combinations of resistors which are passive electrical components) optimized for reduced turn off switching time (Column 10, lines 16-27). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Hsing, in view of Alam, for the purpose of the gates having different resistance values, therefore the gate drivers will cause a reduced voltage overshoot comparing them to other gate drivers, and one of the gate drivers will have a lower switching time compared to another gate driver.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hsing, in view of Huang et al. (CN 111969988 A); hereinafter Hsing, in view of Huang.
Regarding Claim 6, Hsing teaches the multipurpose gate driver of claim 1, but does not explicitly teach wherein the switch includes a multiplexer.
However, Huang teaches wherein the switch includes a multiplexer (switch referred to as multiplexer; Technical Field, Background). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Hsing, in view of Huang, for the purpose of allowing multiple signals to share a single source to save space.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hsing.
Regarding Claim 7, although Hsing uses a single-pole multi-throw switch instead of at least one relay, field-effect transistors (FET), bipolar junction transistor (BJT), and/or optocoupler for the switch, these are just different types of switches and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of switch for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Claims 12-13, are rejected under 35 U.S.C. 103 as being unpatentable over Hsing, in view of Urciuoli (US 20100277006 A1); hereinafter Hsing, in view of Urciuoli.
Regarding Claims 12 & 13, Hsing teaches the system of claim 8, wherein the multipurpose gate driver further includes an output, but does not explicitly teach wherein the multipurpose power electronic switch system further comprises a solid-state circuit breaker electrically connected to the output of the multipurpose gate driver.
However, Urciuoli teaches a solid-state circuit breaker electrically comprises the multipurpose gate driver. (Examiner has interpreted this claim, as stated in applicant's specification paragraphs 0003 & 0023). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Hsing, in view of Urciuoli, for the purpose of switching control and performance.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hsing, in view of Urciuoli, further in view of Alam.
Regarding Claim 14, Hsing, in view of Urciuoli, teaches the system of claim 13, but does not explicitly teach wherein each of the plurality of gate drive circuits includes at least one gate drive circuit comprising a combination of passive and/or active electrical components optimized for reduced voltage overshoot and at least one gate drive circuit comprising a combination of passive and/or active electrical components optimized for reduced turn off switching time.
However, Alam teaches (Fig. 3) wherein each of the plurality of gate drive circuits (32/40) includes at least one gate drive circuit comprising a combination of passive and/or active electrical components (40 includes combinations of resistors which are passive electrical components) optimized for reduced voltage overshoot (Column 1, line 51 to Column 2, line 3) and at least one gate drive circuit (32/40) comprising a combination of passive and/or active electrical components (40 includes combinations of resistors which are passive electrical components) optimized for reduced turn off switching time (Column 10, lines 16-27). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the invention of Hsing, in view of Urciuoli, further in view of Alam, for the purpose of the gates having different resistance values, therefore the gate drivers will cause a reduced voltage overshoot comparing them to other gate drivers, and one of the gate drivers will have a lower switching time compared to another gate driver.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2842
/REGIS J BETSCH/SPE, Art Unit 2843