Prosecution Insights
Last updated: April 19, 2026
Application No. 18/584,369

ELECTRONIC FUSE CIRCUIT AND CIRCUIT SYSTEM USING THE SAME

Final Rejection §103
Filed
Feb 22, 2024
Examiner
CLARK, CHRISTOPHER JAY
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Joulwatt Technology Co. Ltd.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
98%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
560 granted / 742 resolved
+7.5% vs TC avg
Strong +23% interview lift
Without
With
+23.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
18 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
46.9%
+6.9% vs TC avg
§102
30.3%
-9.7% vs TC avg
§112
17.5%
-22.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 742 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with regard to the previous 35 USC 102 rejection have been considered but are moot because the new ground of rejection does not rely on any of the grounds applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Newly cited reference Yousef et al (2022/006011) has been utilized in the modified rejection below to address the amendments made. The previous objections to the specification and claims are withdrawn due to the amendments made. Objections remain with regard to the drawings as discussed further below. Drawings The drawings were received on December 3, 2025. These drawings are not acceptable as issues discussed in previous rejection remain. In particular, with regard to Figures 3 and 5, the comparator outputting “Vocp2” needs to have its positive and negative input signs reversed based on the teaching of paragraphs 37 and 38 of the instant specification. The drawings remain objected to for the reasons discussed above. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 1 is objected to because of the following informalities: CLAIM 1: In the final line, before “sampling” insert --a--. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7, 10, and 11 is/are rejected is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (2013/0166947) in view of Yousef et al (2022/0060011). In re Claim 1, Yang teaches an electronic fuse circuit used in a circuit system with a switching power supply (22, 23 Co), the switching power supply being for supplying power to a load (not shown but connected at 103, paragraph 24), wherein the electronic fuse circuit as seen in Figure 9 (paragraph 50) comprises: an electronic switch (21), coupled to a transmission terminal of an input power supply (VIN) and an input terminal (cathode of 22) of the switching power supply, respectively through a corresponding wire, the electronic switch being configured to connect or disconnect the transmission terminal of the input power supply with the input terminal of the switch power supply according to a switch control signal (paragraph 24); a first protection circuit (41 as seen in Figure 3), configured to obtain a first protection signal (Icom) according to a first threshold signal (Iref) and a current sense signal (Isense) representing a current of a path where the electronic switch is located (paragraph 30); a second protection circuit (42 as seen in Figure 3), configured to obtain a second protection signal (Vcom) according to a second threshold signal (Vref) and a voltage sense signal (Vfb) representing a load voltage (paragraph 30), wherein the second protection circuit is connected to an output terminal of the switch power supply or an input terminal of the load to obtain the voltage sense signal representing the load voltage (as seen in Figures 3 and 9), a logic circuit (43 as seen in Figure 3), configured to generate the switch control signal for controlling the electronic switch to be turned on and off according to the first protection signal and the second protection signal, wherein when the current sense signal reaches the first threshold signal or the voltage sense signal reaches the second threshold signal, the logic circuit is configured to generate the switch control signal for controlling the electronic switch to be turned off (paragraph 30, the switch 21 will be turned off when the current reaches the value of Iref so that the current will follow Iref and turned off so that the output voltage follows Vref). Yang does not a differential sampling circuit and sampling resistor as claimed. Yousef teaches a current sensing arrangement that comprises a sampling resistor 4 (paragraph 33) with a differential amplifier 24 measuring the voltage across the resistor 4 (paragraph 33). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the current sensor of Yang with the resistor and amplifier as taught by Yousef since Yousef teaches them as providing a known alternative current sensing arrangement that is suitable for measuring a current. In re Claim 2, Yang teaches that under different operation states of the circuit system, a value of the second threshold signal is set differently (paragraphs 32-33). In r Claim 3, Yang teaches the value of the second threshold signal under a startup operation state is smaller than the value of the second threshold signal under a normal operation state (as seen in Figure 4). In re Claim 4, Yang teaches the first protection circuit is configured to provide the first protection signal in valid state so that the electronic switch is turned off, when the current sense signal reaches the first threshold signal (paragraph 30, the switch 21 will be turned off when the current reaches the value of Iref so that the current will follow Iref); the second protection circuit is configured to provide the second protection signal in valid state so that the electronic switch is turned off, when the voltage sense signal reaches the second threshold signal (paragraph 30, the switch 21 will be turned off when the output voltage reaches Vref so that the output voltage follows Vref). In re Claim 5, Yang teaches the logic circuit is configured to, during an operation process of the circuit system, if the first protection signal is in valid state, control the switch control signal to be in invalid state to control the electronic switch to be turned off (paragraph 30, the switch 21 will be turned off via the logic circuit 43 when the current reaches the value of Iref so that the current will follow Iref), or if the second protection signal is in valid state, control the switch control signal to be in invalid state to control the electronic switch to be turned off (paragraph 30, the switch 21 will be turned off via logic circuit 43 when the output voltage reaches Vref so that the output voltage follows Vref). In re Claim 6, Yang teaches the logic circuit is configured to, during a startup operation of the circuit system, if the second protection signal is in valid state, control the switch control signal to be in invalid state to control the electronic switch to be turned off (paragraph 30, , the switch 21 will be turned off via the logic circuit 43 when the current reaches the value of Iref so that the current will follow Iref including during a start up such as seen in Figure 4). In re Claim 7, Yang teaches the first protection circuit comprises a first comparison circuit (41 as seen in Figure 5), which obtains the first protection signal when receiving the current sense signal and the first threshold signal (as seen in Figure 5); the second protection circuit comprises a second comparison circuit (42 as seen in Figure 5), which obtains the second protection signal when receiving the voltage sense signal and the second threshold signal (as seen in Figure 5). In re Claim 10, Yang teaches a switching power supply (22, 23, and Co) that receives input power through the electronic fuse and converts the input power supply into an output electric signal to drive the load. In re Claim 11, Yang teaches the switching power supply is a Buck-type power supply (paragraph 24). Allowable Subject Matter Claims 8, 9, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In re Claim 8, Yang fails to specifically teach that the logic circuit 43 comprises the OR logic and trigger circuit as claimed. No teaching in the prior art was found to properly address this deficiency. In re Claim 9, Yang fails to specifically teach that the logic circuit 43 comprises the NOR logic and trigger circuit as claimed. No teaching in the prior art was found to properly address this deficiency. In re Claim 12, Yang fails to teach that the buck-type switching power supply is a multi-phase buck type switching power supply with driving control circuit as claimed. No teaching in the prior art was found to properly address this deficiency. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER JAY CLARK whose telephone number is (571)270-1427. The examiner can normally be reached Monday - Friday, 10:00am - 6:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER J CLARK/Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Feb 22, 2024
Application Filed
Aug 23, 2025
Non-Final Rejection — §103
Dec 03, 2025
Response Filed
Feb 26, 2026
Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
98%
With Interview (+23.0%)
2y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 742 resolved cases by this examiner. Grant probability derived from career allow rate.

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