DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 10/21/2025. Claims 1, 13, and 18 have been amended. Claims 1-20 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed provisional application 63/488,690 filed on 03/06/2023 is acknowledged.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/21/2025 and 11/04/2025 has been entered.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(2) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-16 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sela et al. (2023/0305756), hereinafter Sela in view of Bode et al. (US2021/0263655), hereinafter Bode, and further in view of Wakutsu et al. (US 2024/0094923), hereinafter Wakutsu, and Rathore et al. (US 2023/0367507), hereinafter Rathore.
Regarding claims 13 and 18, taking claim 13 as exemplary, Sela teaches a system, comprising:
a non-volatile memory (Sela, [0017], The present disclosure generally relates to data storage devices, such as solid state drives (SSDs)) configured with a wear-leveling media pool comprising a plurality of memory blocks (Sela, [0024], In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks),
wherein the wear-leveling media pool has an initial endurance limit that is a factory guaranteed endurance limit (Sela,; [0029]; Note – initial endurance limit is the TBW based on initial configuration of SLC/MLC/TLC capacity.),
wherein the wear-leveling media pool is divided into a plurality of virtual partitions (Sela, [0031], the memory device 252 may be partitioned into a number of virtual pools), including a first subset of one or more first virtual partitions configured to store system data associated with a host device and a second subset of one or more second virtual partitions configured to store non-system data associated with the host device, and
wherein each virtual partition of the plurality of virtual partitions is assigned a respective endurance threshold (Sela, [0036], the controller 108 determines and configures a TBW threshold or quota for each of the virtual pools) based at least in part on the initial endurance limit; and
a controller configured to:
evaluate an endurance parameter of the wear-leveling media pool,
determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the endurance parameter satisfying a memory endurance condition of the wear-leveling media pool, and
allocate the additional endurance amount to the second subset of one or more second virtual partitions to increase the respective endurance threshold of at least one of the one or more second virtual partitions.
Sela does not teach an initial endurance limit is a factory guaranteed endurance limit; a plurality of virtual partitions including a first subset of one or more first virtual partitions configured to store system data associated with a host device and a second subset of one or more second virtual partitions configured to store non-system data associated with the host device; wherein each virtual partition of the plurality of virtual partitions is assigned a respective endurance threshold based at least in part on the initial endurance limit; a controller configured to evaluate an endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the endurance parameter satisfying a memory endurance condition of the wear-leveling media pool, and allocate the additional endurance amount to the second subset of one or more second virtual partitions to increase the respective endurance threshold of at least one of the one or more second virtual partitions, as claimed.
Sela in view of Bode teaches an initial endurance limit that is a factory guaranteed endurance limit (Bode, [0022], the illustrative embodiments recognize and take into account that an endurance of a solid state storage device can be described in terms of drive writes per day (DWPD). The illustrative embodiments recognize and take into account that the manufacturer specifies the number of drive writes per day that can be performed and maintain the warranty; [0058], lower endurance tier 242 can be an entry-level tier within maximum write rate of 1.0 daily write per day (DWPD) specified by the manufacturer);
wherein each virtual partition of the plurality of virtual partitions is assigned a respective endurance threshold based at least in part on the initial endurance limit (Bode, [0053], The maximum write rate specified by the manufacturer can be measured, for example, as drive writes per day (DWPD); [0085], The process begins by receiving a request to create a new logical unit number (LUN) for a volume in a storage system; [0086], The process receives an expected write level for the new logical unit number (step 602). In step 602, the write level can be the amount of data expected to be written to the logical unit number on a daily basis; [0087], The process creates volume on an endurance tier that has a maximum recommended write rate that is greater than the write level received).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to incorporate teachings of Bode to set a manufacturer guaranteed drive writes per day (write rate) as an initial endurance limit for a storage pool and assign an endurance threshold (write rate) to logical partitions created on the storage pool based on the manufacturer guaranteed write rate. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Bode because it improves efficiency and reliability of the storage system disclosed in Sela by providing a threshold for each logical partition in order to avoid data loss due to writing data on end-of-life storage devices.
The combination of Sela does not explicitly teach a plurality of virtual partitions including a first subset of one or more first virtual partitions configured to store system data associated with a host device and a second subset of one or more second virtual partitions configured to store non-system data associated with the host device; a controller configured to evaluate an endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the endurance parameter satisfying a memory endurance condition of the wear-leveling media pool, and allocate the additional endurance amount to the second subset of one or more second virtual partitions to increase the respective endurance threshold of at least one of the one or more second virtual partitions, as claimed
The combination of Sela in view of Wakutsu teaches including a first subset of one or more first virtual partitions configured to store system data associated with a host device (Wakutsu, [0181], The SLC system area 230 stores the firmware program and management information of the memory system 1 a; Fig. 15) and a second subset of one or more second virtual partitions configured to store non-system data associated with the host device (Wakutsu, [0182], The user data area 240 is an area in which the user data received from the host device 2 is stored; Fig.15);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela to store system data in a first virtual partition and store user data in a second virtual partition of the plurality of logical units. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Sela with Wakutsu because it improves efficiency of the storage system disclosed in the combination of Sela by storing data having similar characteristics together in order to manage the similar data together, which increases endurance of the nonvolatile memory storage storing the data.
The combination of Sela does not explicitly teach evaluate an endurance parameter of the wear-leveling media pool and determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the endurance parameter satisfying a memory endurance condition of the wear-leveling media pool, and allocate the additional endurance amount to the second subset of one or more second virtual partitions to increase the respective endurance threshold of at least one of the one or more second virtual partitions, as claimed.
However, the combination of Sela in view of Rathore teaches wherein the wear-leveling media pool has an initial endurance limit (Rathore, [0022], a flash storage device operates based on its initial multi-bit mode, TBW rating);
evaluate an endurance parameter of the wear-leveling media pool (Rathore, [0060], determining that an amount of data written to the flash storage device is greater than a threshold amount of data),
determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the endurance parameter satisfying a memory endurance condition of the wear-leveling media pool (Rathore, [0060], triggers 224 may include a threshold amount of data which causes controller 220 to switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode; [0005], even after 1,000 P/E cycles, switching QLC flash blocks to SLC mode may still enable at least another 90,000 P/E cycles), and
allocate the additional endurance amount to the second subset of one or more second virtual partitions to increase the respective endurance threshold of at least one of the one or more second virtual partitions (Rathore, [0060]; Wakutsu, [0180], a user data area 240 in which the storage mode can be set in any manner; Note – since user data area 240 can have both single bit and multi-bit memory blocks, the mode of a selected memory block in the user data area 240 can be switched from multi-bit to single-bit. The TBW threshold (in Sela) of user data area 240 will be increased due to additional P/E cycles from changing of MLC to SLC).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Claim 18 has similar limitations as claim 13 and is rejected for the similar reasons.
Regarding claim 14, the combination of Sela teaches all the features with respect to claim 13 as outlined above. The combination of Sela further teaches the system of claim 13, wherein the controller is configured to maintain the initial endurance limit of the wear-leveling media pool based on the endurance parameter not satisfying the memory endurance condition of the wear-leveling media pool (Rathore, [0028], This process may occur based on one or more of the trigger events previously described for converting flash blocks from multi-bit mode to SLC mode; [0056], If trigger event has not occurred, then method 400 continues and the flash storage device maintains (406) multi-bit mode for the blocks).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory only in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Regarding claims 15 and 19, taking claim 15 as exemplary, the combination of Sela teaches all the features with respect to claim 13 as outlined above. The combination of Sela further teaches the system of claim 13, wherein the respective endurance threshold is a respective terabytes written (TBW) limit or a respective program/erase cycle limit (Sela, [0036], the controller 108 determines and configures a TBW threshold or quota for each of the virtual pools based on an allocated one or more LBA ranges or one or more LUs from one or more memory devices having one or more memory architectures.), and wherein the initial endurance limit is an initial TBW limit or an initial program/erase cycle limit (Sela, [0029]; Rathore, [0022], a flash storage device operates based on its initial multi-bit mode, TBW rating).
Claim 19 has similar limitations as claim 15 and is rejected for the similar reasons.
Regarding claim 16, the combination of Sela teaches all the features with respect to claim 13 as outlined above. The combination of Sela further teaches the system of claim 13, wherein the controller is configured to evaluate the endurance parameter of the wear-leveling media pool by evaluating a memory endurance of the plurality of memory blocks (Rathore, [0022], the trigger event may be based on a number of P/E cycles for the blocks in the flash memory of the flash storage device).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Sela, Bode, Wakutsu, and Rathore as applied to claim 13 above, and further in view of Bigdeliazari et al. (US 6744764), hereinafter Bigdeliazari.
Regarding claim 17, the combination of Sela teaches all the features with respect to claim 13 as outlined above. The combination of Sela does not explicitly teach the system of claim 13, wherein the controller is configured to allocate the additional endurance amount to the second subset of one or more second virtual partitions such that a weighted average of the respective endurance thresholds of the plurality of virtual partitions matches a sum of the initial endurance limit and the additional endurance amount, as claimed.
However, the combination of Sela in view of Bigdeliazari teaches the system of claim 13, wherein the controller is configured to allocate the additional endurance amount to the second subset of one or more second virtual partitions such that a weighted average of the respective endurance thresholds of the plurality of virtual partitions matches a sum of the initial endurance limit and the additional endurance amount (Bigdeliazari, col.13, lines, 8-51).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela to incorporate teachings of Bigdeliazari to ensure the sum of all average allocations equal to the total allocation. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Bigdeliazari because it ensures the storage system disclosed in the combination of Sela to function correctly when accurate mathematical relationships are maintained.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Sela, Bode, Wakutsu, and Rathore as applied to claim 18 above, and further in view of Kuang et al. (US 2016/0041760), hereinafter Kuang.
Regarding claim 20, the combination of Sela teaches all the features with respect to claim 18 as outlined above. The combination of Sela does not explicitly teach the method of claim 18, wherein the endurance parameter is a valley margin between pairs of adjacent programming distributions of the wear-leveling media pool, wherein the endurance parameter is a total quantity of error detection and correction operations performed on the wear-leveling media pool, or wherein the endurance parameter is a total quantity of errors detected within the wear-leveling media pool, as claimed.
However, the combination of Sela in view of Kuang teaches the method of claim 18, wherein the endurance parameter is a valley margin between pairs of adjacent programming distributions of the wear-leveling media pool, wherein the endurance parameter is a total quantity of error detection and correction operations performed on the wear-leveling media pool, or wherein the endurance parameter is a total quantity of errors detected within the wear-leveling media pool (Kuang, [0076], the selection based on physical location of the pages may be performed at a different threshold than the MLC threshold or in response to an event, such as a number of errors encountered over the lifetime of the MLC flash memory device reaching a particular value, a certain number of errors occurring within a particular period of time, or the like. In such a case, the triggering of the transition from the MLC mode to the SLC mode of operation may occur at a different time).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela to incorporate teachings of Kuang to switch from MLC mode to SLC mode based on number of errors of a flash memory. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Kuang because it improves efficiency and reliability of the storage system disclosed in the combination of Sela by switching from MLC mode to SLC mode in order to extend lifetime of a flash storage.
Claim(s) 1-7, and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sela et al. (2023/0305756), hereinafter Sela in view of Bode et al. (US2021/0263655), hereinafter Bode, further in view of Seo et al. (US2021/0157525), hereinafter Seo, Rathore et al. (US 2023/0367507), hereinafter Rathore, and Wakutsu et al. (US 2024/0094923), hereinafter Wakutsu.
Regarding claim 1, Sela teaches a system, comprising:
a non-volatile memory (Sela, [0017], The present disclosure generally relates to data storage devices, such as solid state drives (SSDs)) configured with a wear-leveling media pool comprising a plurality of memory blocks (Sela, [0024], In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks),
wherein the wear-leveling media pool has an initial endurance limit that is a factory-guaranteed endurance limit (Sela, [0029]; Note – initial endurance limit is the TBW based on initial configuration of SLC/MLC/TLC capacity),
wherein the wear-leveling media pool is divided into a plurality of virtual partitions (Sela, [0031], the memory device 252 may be partitioned into a number of virtual pools), and
wherein each virtual partition of the plurality of virtual partitions is assigned a respective endurance threshold (Sela, [0036], the controller 108 determines and configures a TBW threshold or quota for each of the virtual pools) based at least in part on the initial endurance limit; and
a controller (Sela, [0020], controller 108) configured to:
monitor a first endurance parameter for each virtual partition of the plurality of virtual partitions (Sela, [0032], the controller 108 may set a threshold count, where reaching the threshold count or exceeding the threshold count that the one or more applications or LUs may be overusing the allocated memory associated with the virtual pool or that the allocated memory associated with the virtual pool may be nearing end-of-life conditions), including enabling read operations and write operations at a respective virtual partition based on the first endurance parameter for the respective virtual partition not satisfying the respective endurance threshold of the respective virtual partition, and disabling the write operations at the respective virtual partition based on the first endurance parameter for the respective virtual partition satisfying the respective endurance threshold of the respective virtual partition,
evaluate a second endurance parameter of the wear-leveling media pool,
determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and
allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions.
Sela does not teach an initial endurance limit is a factory guaranteed endurance limit; wherein each virtual partition of the plurality of virtual partitions is assigned a respective endurance threshold based at least in part on the initial endurance limit; enabling read operations and write operations at a respective virtual partition based on the first endurance parameter for the respective virtual partition not satisfying the respective endurance threshold of the respective virtual partition, and disabling the write operations at the respective virtual partition based on the first endurance parameter for the respective virtual partition satisfying the respective endurance threshold of the respective virtual partition, evaluate a second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions, as claimed.
Sela in view of Bode teaches an initial endurance limit that is a factory guaranteed endurance limit (Bode, [0022], the illustrative embodiments recognize and take into account that an endurance of a solid state storage device can be described in terms of drive writes per day (DWPD). The illustrative embodiments recognize and take into account that the manufacturer specifies the number of drive writes per day that can be performed and maintain the warranty; [0058], lower endurance tier 242 can be an entry-level tier within maximum write rate of 1.0 daily write per day (DWPD) specified by the manufacturer);
wherein each virtual partition of the plurality of virtual partitions is assigned a respective endurance threshold based at least in part on the initial endurance limit (Bode, [0053], The maximum write rate specified by the manufacturer can be measured, for example, as drive writes per day (DWPD); [0085], The process begins by receiving a request to create a new logical unit number (LUN) for a volume in a storage system; [0086], The process receives an expected write level for the new logical unit number (step 602). In step 602, the write level can be the amount of data expected to be written to the logical unit number on a daily basis; [0087], The process creates volume on an endurance tier that has a maximum recommended write rate that is greater than the write level received).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to incorporate teachings of Bode to set a manufacturer guaranteed drive writes per day (write rate) as an initial endurance limit for a storage pool and assign an endurance threshold (write rate) to logical partitions created on the storage pool based on the manufacturer guaranteed write rate. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Bode because it improves efficiency and reliability of the storage system disclosed in Sela by providing a threshold for each logical partition in order to avoid data loss due to writing data on end-of-life storage devices.
The combination of Sela does not teach enabling read operations and write operations at a respective virtual partition based on the first endurance parameter for the respective virtual partition not satisfying the respective endurance threshold of the respective virtual partition, and disabling the write operations at the respective virtual partition based on the first endurance parameter for the respective virtual partition satisfying the respective endurance threshold of the respective virtual partition, evaluate a second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions, as claimed.
However, the combination of Sela in view of Seo teaches enabling read operations and write operations at a respective virtual partition based on the first endurance parameter for the respective virtual partition not satisfying the respective endurance threshold of the respective virtual partition, and disabling the write operations at the respective virtual partition based on the first endurance parameter for the respective virtual partition satisfying the respective endurance threshold of the respective virtual partition (Seo, [0041], When the memory device 100 accesses the selected area, it may mean that the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation; [0052], The reference number may be set to be greater than the threshold value serving as a basis on which the first memory area 110 or the second memory area 120 reaches End of Life, or is switched to the read only mode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela to incorporate teachings of Seo to disable write operations to a memory partition when the memory partition is determined to be near end-of-life. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with the combination of Seo because it improves reliability of the storage system disclosed in the combination of Sela by preventing storing data in memory partitions with higher failure probability.
The combination of Sela does not teach evaluate a second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions, as claimed.
However, the combination of Sela in view of Rathore teaches wherein the wear-leveling media pool has an initial endurance limit (Rathore, [0022], a flash storage device operates based on its initial multi-bit mode, TBW rating)
evaluate a second endurance parameter of the wear-leveling media pool (Rathore, [0060], determining that an amount of data written to the flash storage device is greater than a threshold amount of data),
determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold (Rathore, [0060], triggers 224 may include a threshold amount of data which causes controller 220 to switch one or more of blocks 238, 239 from multi-bit mode to single-bit mode; [0005], even after 1,000 P/E cycles, switching QLC flash blocks to SLC mode may still enable at least another 90,000 P/E cycles),
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
The combination of Sela does not explicitly teach allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions, as claimed.
However, the combination of Sela in view of Wakutsu teaches allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions (Rathore, [0060]; Wakutsu, [0180], a user data area 240 in which the storage mode can be set in any manner; Note – since user data area 240 can have both single bit and multi-bit memory blocks, the mode of a selected memory block in the user data area 240 can be switched from multi-bit to single-bit. The TBW threshold (in Sela) of user data area 240 will be increased due to additional P/E cycles from changing of MLC to SLC).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to store system data in a first virtual partition and store user data in a second virtual partition. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Wakutsu because it improves efficiency of the storage system disclosed in Sela by storing data having similar characteristics together in order to manage the similar data together, which increases endurance of the nonvolatile memory storage storing the data.
Regarding claim 2, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein the controller is configured to update the initial endurance limit of the wear-leveling media pool to an updated endurance limit by increasing the initial endurance limit of the wear-leveling media pool by the additional endurance amount (Rathore, [0022], a flash storage device operates based on its initial multi-bit mode, TBW rating; [0026], once the flash storage device is converted to SLC mode, the flash storage device may report a new TBW rating to the host system, for tracking the extended lifetime of the flash storage device).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to update an initial endurance limit by switching the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles in a memory pool in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Regarding claim 3, the combination of Sela teaches all the features with respect to claim 2 as outlined above. The combination of Sela further teaches the system of claim 2, wherein the additional endurance amount is a first additional endurance amount, the updated endurance limit is a first updated endurance limit, and the parameter threshold is a first parameter threshold, wherein, subsequent to allocating the first additional endurance amount among the one or more virtual partitions, the controller is configured to: evaluate the second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by a second additional endurance amount based on the second endurance parameter satisfying a second parameter threshold, and allocate the second additional endurance amount among the one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions (Rathore, [0028], This process may occur based on one or more of the trigger events previously described for converting flash blocks from multi-bit mode to SLC mode; Note – as long as a trigger event has occurred, conversion of multi-bit mode to single-bit mode can take place.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Regarding claim 4, the combination of Sela teaches all the features with respect to claim 3 as outlined above. The combination of Sela further teaches the system of claim 3, wherein the controller is configured to update the first updated endurance limit to a second updated endurance limit by increasing the first updated endurance limit by the second additional endurance amount (Rathore, [0026], once the flash storage device is converted to SLC mode, the flash storage device may report a new TBW rating to the host system, for tracking the extended lifetime of the flash storage device).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Regarding claim 5, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein the one or more virtual partitions are configured to store non-system data associated with a host device (Wakutsu, [0182], The user data area 240 is an area in which the user data received from the host device 2 is stored; Fig.15);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to store system data in a first virtual partition and store user data in a second virtual partition. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Wakutsu because it improves efficiency of the storage system disclosed in Sela by storing data having similar characteristics together in order to manage the similar data together, which increases endurance of the nonvolatile memory storage storing the data.
Regarding claim 6, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein the one or more virtual partitions are configured to store application data corresponding to one or more applications (Sela, [0007], herein each virtual pool corresponds with one or more logical block address (LBA) ranges or one or more logical units (LUs) of the memory device; [0030], It is to be understood that the embodiments described may be applicable to logical units (LUs), where one or more LUs may be associated with an applications and/or a host device).
Regarding claim 7, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein the respective endurance threshold is a respective terabytes written (TBW) limit or a respective program/erase cycle limit (Sela, [0036], the controller 108 determines and configures a TBW threshold or quota for each of the virtual pools based on an allocated one or more LBA ranges or one or more LUs from one or more memory devices having one or more memory architectures.), wherein the first endurance parameter is a quantity of TBW to the respective virtual partition or a quantity of program/erase cycles performed on the respective virtual partition (Sela, [0032]; By having virtual pools using counters, the memory device 252 may be configured with a TBW for each application and/or LU by the controller 108 associated with the virtual pools. The controller 108 may use the counters to determine the health of the virtual pools. Each virtual pool (or rather, each application and/or LU) may be associated with a wear-out quota; [0034]; [0036], TBW threshold or quota), and wherein the initial endurance limit is an initial TBW limit or an initial program/erase cycle limit (Sela, [0029]; Rathore, [0022], a flash storage device operates based on its initial multi-bit mode, TBW rating).
Regarding claim 9, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein each virtual partition of the plurality of virtual partitions is assigned a different subset of logical memory addresses (Sela, [0031], the virtual pools may be associated with one or more logical block address (LBA) ranges.).
Regarding claim 10, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein the plurality of virtual partitions includes one or more first virtual partitions configured to store system data associated with a host device (Wakutsu, [0181], The SLC system area 230 stores the firmware program and management information of the memory system 1 a; Fig. 15) and one or more second virtual partitions configured to store non-system data associated with the host device (Wakutsu, [0182], The user data area 240 is an area in which the user data received from the host device 2 is stored; Fig.15), and
wherein the controller is configured to allocate the additional endurance amount among at least one of the one or more second virtual partitions to increase the respective endurance threshold of the at least one of the one or more second virtual partitions (Rathore, [0060]; Wakutsu, [0180], a user data area 240 in which the storage mode can be set in any manner; Note – since user data area 240 can have both single bit and multi-bit memory blocks, the mode of a selected memory block in the user data area 240 can be switched from multi-bit to single-bit. The TBW threshold (in Sela) of user data area 240 will be increased due to additional P/E cycles from changing of MLC to SLC).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to store system data in a first virtual partition and store user data in a second virtual partition. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Wakutsu because it improves efficiency of the storage system disclosed in Sela by storing data having similar characteristics together in order to manage the similar data together, which increases endurance of nonvolatile memory storages.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Regarding claim 11, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela further teaches the system of claim 1, wherein the controller is configured to:
divide the wear-leveling media pool into the plurality of virtual partitions (Sela, [0031], the memory device 252 may be partitioned into a number of virtual pools), including a first subset of one or more first virtual partitions configured to store system data associated with a host device (Wakutsu, [0181], The SLC system area 230 stores the firmware program and management information of the memory system 1 a; Fig. 15) and a second subset of one or more second virtual partitions configured to store non-system data associated with the host device (Wakutsu, [0182], The user data area 240 is an area in which the user data received from the host device 2 is stored; Fig.15),
assign each virtual partition of the plurality of virtual partitions a respective endurance threshold (Sela, [0036], the controller 108 determines and configures a TBW threshold or quota for each of the virtual pools), and
allocate the additional endurance amount among the second subset of one or more second virtual partitions to increase the respective endurance threshold of at least one of the one or more second virtual partitions (Rathore, [0060]; Wakutsu, [0180], a user data area 240 in which the storage mode can be set in any manner; Note – since user data area 240 can have both single bit and multi-bit memory blocks, the mode of a selected memory block in the user data area 240 can be switched from multi-bit to single-bit. The TBW threshold (in Sela) of user data area 240 will be increased due to additional P/E cycles from changing of MLC to SLC).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to store system data in a first virtual partition and store user data in a second virtual partition. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Wakutsu because it improves efficiency of the storage system disclosed in Sela by storing data having similar characteristics together in nonvolatile memory storages (NVM) in order to manage similar data together, which increases endurance of NVM.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela with Rathore to switch the mode of a memory block from multi-bit to single bit to increase endurance/program-erase cycles of a nonvolatile memory in response to a trigger event. A person of ordinary skill in the art would have been motivated to combine the combination of Sela with Rathore because it improves efficiency of the storage system disclosed in the combination of Sela by balancing endurance and capacity of a nonvolatile memory storage.
Regarding claim 12, the combination of Sela teaches all the features with respect to claim 11 as outlined above. The combination of Sela further teaches the system of claim 11, wherein the controller is configured to maintain the respective endurance threshold of each of the one or more first virtual partitions at a respective fixed value (Wakutsu, Fig.15, see partition 230 can only have SLC memory blocks while partition 240 can have MLC/TLC/QLC memory blocks that can be converted to SLC memory blocks).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Sela to maintain different endurance threshold for each virtual partition. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Wakutsu because it improves efficiency of the storage system disclosed in Sela by storing data having similar characteristics together in order to manage the similar data together, which increases endurance of the nonvolatile memory storage storing the data.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Sela, Bode, Seo, Rathore, and Wakutsu as applied to claim 1 above, and further in view of Kuang et al. (US 2016/0041760), hereinafter Kuang.
Regarding claim 8, the combination of Sela teaches all the features with respect to claim 1 as outlined above. The combination of Sela does not explicitly teach the system of claim 1, wherein the second endurance parameter is a valley margin between pairs of adjacent programming distributions of the wear-leveling media pool, wherein the second endurance parameter is a total quantity of error detection and correction operations performed on the wear-leveling media pool, or wherein the second endurance parameter is a total quantity of errors detected within the wear-leveling media pool, as claimed.
However, the combination of Sela in view of Kuang teaches the system of claim 1, wherein the second endurance parameter is a valley margin between pairs of adjacent programming distributions of the wear-leveling media pool, wherein the second endurance parameter is a total quantity of error detection and correction operations performed on the wear-leveling media pool, or wherein the second endurance parameter is a total quantity of errors detected within the wear-leveling media pool (Kuang, [0076], the selection based on physical location of the pages may be performed at a different threshold than the MLC threshold or in response to an event, such as a number of errors encountered over the lifetime of the MLC flash memory device reaching a particular value, a certain number of errors occurring within a particular period of time, or the like. In such a case, the triggering of the transition from the MLC mode to the SLC mode of operation may occur at a different time).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Sela to incorporate teachings of Kuang to switch from MLC mode to SLC mode based on number of errors of a flash memory. A person of ordinary skill in the art would have been motivated to combine the teachings of Sela with Kuang because it improves efficiency and reliability of the storage system disclosed in the combination of Sela by switching from MLC mode to SLC mode in order to extend lifetime of a flash storage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dalmatov (US2021/0200458) teaches a factory-guaranteed write cycles as an initial endurance limit.
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/NANCI N WONG/Primary Examiner, Art Unit 2137