DETAILED ACTION
This office action is in response to the application filed on 2/22/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matthew et al. (US10122265, hereinafter Matthew).
Regarding Claim 1, Matthew discloses a dithering circuit for low-power applications (fig. 2, 3), the dithering circuit comprising: an offset generator (310/306) configured, in different cycles, to output different offset values (311 ); and a comparator circuit (322) coupled to the offset generator, the offset generator further configured to control the comparator circuit to perform steps comprising: receiving threshold values adjusted based on the different offset values (from 320); and using the threshold values to generate a non-periodic output signal (364).
Regarding Claim 2, Matthew discloses (fig. 2, 3) the offset generator is implemented as a linear feedback shift register (LFSR) configured to create the different offset values (col. 6, lines 38-40).
Regarding Claim 3, Matthew discloses (fig. 2, 3) a wake-up circuit configured to use the non-periodic output signal to cause a DC-to-DC converter (fig. 2, 200) to wake-up in non-periodic intervals (based on Reset and 364 to 108a) such as to spread an energy associated with a switching frequency over a range of frequencies in a frequencies spectrum to suppress one or more audible tones (col. 1, lines 25-45).
Regarding Claim 4, Matthew discloses (fig. 2, 3) the offset generator is configured to output the different offset values in response to receiving a signal that indicates that the dithering circuit is in a low-power mode (based on Ipeak).
Regarding Claim 6, Matthew discloses (fig. 2, 3) the offset generator is configured to randomize the threshold values by using a randomized code to generate the different offset values (col. 6, lines 38-40).
Regarding Claim 7, Matthew discloses (fig. 2, 3) the offset generator is configured to generate the randomized code by using a counter that dithers between two or more bit values (col. 6, lines 38-40).
Regarding Claim 8, Matthew discloses a dithering method for reducing audible noise in low-power switching circuits (fig. 2, 3), the method comprising: generating a set of offset values (311) that are different from each other (col. 6, lines 7-44); using the set of offset values to adjust a set of threshold values (316) of a comparator circuit (322); using the set of threshold values to generate a non-periodic wake-up signal (317-R); and using the non-periodic wake-up signal to cause a wake-up circuit to reduce or eliminate one or more audible tones (col. 1, lines 25-45).
Regarding Claim 9, Matthew discloses (fig. 2, 3) using the wake-up signal to operate a DC-to-DC converter (fig. 2, 200) without the comparator circuit triggering at the same times in two subsequent cycles to spread an energy associated with a switching frequency over a range of frequencies in a frequencies spectrum thereby suppressing one or more audible tones (322 triggers 360 subsequently based on different generation of random numbers).
Regarding Claim 10, Matthew discloses (fig. 2, 3) the set of offset values are generated by an offset generator that is implemented as a linear feedback shift register (LFSR) (col. 6, lines 38-40).
Regarding Claim 11, Matthew discloses (fig. 2, 3) the offset generator uses a randomized code to generate the different offset values, the offset values randomizing the threshold values (col. 6, lines 38-40).
Regarding Claim 12, Matthew discloses (fig. 2, 3) the offset generator generates the randomized code by using a counter that dithers between two or more bit values (col. 6, lines 38-40).
Regarding Claim 13, Matthew discloses (fig. 2, 3) the offset generator generates the different offset values in response to receiving a signal that indicates that the dithering circuit is in a low-power mode (based on Ipeak).
Regarding Claim 14, Matthew discloses a dithering circuit (fig. 2, 3) comprising: a voltage threshold circuit configured to output a threshold voltage (346) based on an offset (340) that has different offset values in different switching cycles (col. 6, lines 7-44), the threshold voltage having different threshold values in different switching cycles (col. 6, lines 7-44); and a comparator circuit (352) configured to compare the threshold voltage to a voltage present in an input of the comparator circuit (106) to generate a comparator output (347).
Regarding Claim 15, Matthew discloses (fig. 2, 3) an offset generator that is implemented as a linear feedback shift register (LFSR) configured to create the different offset values (col. 6, lines 38-40).
Regarding Claim 16, Matthew discloses (fig. 2, 3) the offset generator is configured to output the offset in response to receiving a signal that indicates that the dithering circuit is in a low-power mode (based on Ipeak).
Regarding Claim 18, Matthew discloses (fig. 2, 3) the offset generator is configured to randomize the threshold voltage by using a randomized code to generate the different offset values (col. 6, lines 38-40).
Regarding Claim 19, Matthew discloses (fig. 2, 3) the offset generator is configured to generate the randomized code by using a counter that dithers between two or more bit values (col. 6, lines 38-40).
Regarding Claim 20, Matthew discloses (fig. 2, 3) a wake-up circuit configured to use the comparator output to cause a DC-to-DC converter to wake up in non-periodic intervals such as to spread an energy associated with a switching frequency over a range of frequencies in a frequencies spectrum to suppress one or more audible tones (322 triggers 360 subsequently based on different generation of random numbers).
Allowable Subject Matter
Claims 5 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art fails to disclose: “...the offset generator is configured to generate, for a first cycle, a first offset and, for a second cycle, a second offset, and wherein the comparator circuit is configured to output, in the first cycle, a first threshold, and, in the second cycle, a second threshold” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 17, the prior art fails to disclose: “...the offset generator is configured to generate, for a first cycle, a first offset value and, for a second cycle, a second offset value, and wherein the comparator circuit is configured to output, in the first cycle, a first threshold value, and, in the second cycle, a second threshold value” in combination with the additionally claimed features, as are claimed by the Applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 11171662, Steensgaard-Madsen; Jesper discloses an analog-to-digital conversion circuit with improved linearity.
US 20040032353, Kattan, Shalom discloses a method for calibrating threshold levels on comparators with dithered DC signals.
US 20080084340, Hurrell; Christopher Peter discloses a dither technique for improving dynamic non-linearity in an analog to digital converter, and an analog to digital converter having improved dynamic non-linearity.
US 20230223987, Chen; Jung-Sheng et al. discloses a spread spectrum switching converter and spread spectrum control method thereof.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE J MOODY/
Primary Examiner, Art Unit 2838