DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Porter et al. (US Patent No. 5,263,032), hereinafter referred to as PORTER.
Consider Claim 1,
PORTER teaches a method for operating a memory system, the method comprising:
providing, by a memory controller, a memory with information on an off-lined region (PORTER, e.g., Col 7:56-57, list of bad pages; Col 15:14-15, read error data from memory controller.); and
performing, by the memory, an error check and scrub operation while changing regions except for the off-lined region among a plurality of regions in the memory (PORTER, e.g., Fig 7, perform error check for a DRAM read access; Fig 8, perform scrub responsive to DRAM access (access to a new location is considered changing regions); Col 2:31-39, do not use bad pages (i.e., off-lined regions).).
Consider Claim 2,
PORTER further teaches:
performing, by the memory, the error check and scrub operation while changing regions for all regions in the memory (PORTER, e.g., Fig 7, perform error check for a DRAM read access; Fig 8, perform scrub responsive to DRAM access. The examiner notes that prior to identifying an off-lined region this applies to all scrubbable memory.);
providing, by the memory, the memory controller with information about a bad region in which a number of detected errors is equal to or greater than a threshold value as a result of the error check and scrub operation (PORTER, e.g., Col 8:11-17, describes exceeding an internal threshold.); and
off-lining, by the memory controller, the bad region to generate the information on the off-lined region (PORTER, e.g., Col 8:11-16, error log generated when hard fault is detected; Col 6:1-12, detection of a hard error results in the old page being marked bad and not used.).
Consider Claim 3,
PORTER teaches a method for operating a memory, the method comprising:
receiving an address of an off-lined region from a memory controller; storing the address of the off-lined region (PORTER, e.g., Col 8:11-16, error log generated when hard fault is detected; Col 6:1-12, detection of a hard error results in the old page being marked bad and not used.);
generating a first address for a first region (PORTER, e.g., Fig 6(61), read request received.); confirming that the first address is different from the address of the off-lined region (Col 9:1-18, determine if requested page is in permissible range (i.e., not off lined).); performing error check and scrub operation on the first region (PORTER, e.g., Col 9:1-19, perform error check and scrub if region is not off-lined (e.g., Col 16:Table B:paged pool.).);
generating a second address for a second region (PORTER, e.g., Fig 6(61), read request received.); confirming that the second address and the address of the off-lined region are the same (Col 9:1-18, determine if requested page is off-lined (i.e., not permissible).); and skipping the error check and scrub operation on the second region (PORTER, e.g., Col 9:14-18, system regions which cannot be accessed are indicated “no-scrub” and “no-replace.”).
Consider Claim 4,
PORTER teaches a memory comprising:
a cell array including a plurality of regions each including a plurality of memory cells (PORTER, e.g., Fig 3(20), DRAM array.);
an off-lined region storing circuit configured to store information of an off-lined region, the information being transferred from a memory controller (PORTER, e.g., Col 7:56-57, list of bad pages; Col 15:14-15, read error data from memory controller.);
an error detection circuit configured to detect one or more errors in data read from each of the regions (PORTER, e.g., Fig 3, shows ECC elements.);
an error counting circuit configured to count a number of the detected errors (PORTER, e.g., Fig 5(55); Col 14:10-12, match count.);
an error log circuit configured to store a result of the counting (PORTER, e.g., Fig 5(55), store number of matches.); and
a blocking circuit configured to prevent the error log circuit from storing the result of a region which is the same as the off-lined region among the regions (PORTER, e.g., Col 6:1-17, suppress footprint if bad page.).
Consider Claim 5,
PORTER further teaches wherein the result includes information of a region, of which the number of the detected errors is equal to or greater than a threshold value (PORTER, e.g., Col 8:11-17, detect if internal threshold is exceeded.).
Consider Claim 6,
PORTER further teaches wherein the result includes the number of the detected errors of each of the regions (PORTER, e.g., Fig 5, each FP block has its own counter; Col 11:1+, FP block for each region.).
Consider Claim 7,
PORTER teaches a memory, comprising:
a cell array including a plurality of regions each including a plurality of memory cells (PORTER, e.g., Fig 3(20), DRAM array.);
an off-lined region storing circuit configured to store information of an off-lined region, the information being transferred from a memory controller (PORTER, e.g., Col 7:56-57, list of bad pages; Col 15:14-15, read error data from memory controller.);
an error detection circuit configured to detect one or more errors in data read from each of the regions (PORTER, e.g., Fig 3, shows ECC elements.);
an error counting circuit configured to count a number of the detected errors (PORTER, e.g., Fig 5(55); Col 14:10-12, match count.);
an error log circuit configured to store a result of the counting (PORTER, e.g., Fig 5(55), store number of matches.); and
a blocking circuit configured to prevent the error counting circuit from counting the detected errors of a region which is the same as the off-lined region among the regions (PORTER, e.g., Col 6:1-17, suppress footprint if bad page; Fig 5(55), footprint information includes count. Therefore if a region is bad/off-lined the counting is avoided by suppressing the footprint.).
Consider Claim 8,
PORTER further teaches wherein the result includes information of a region, of which the number of the detected errors is equal to or greater than a threshold value(PORTER, e.g., Col 8:11-17, detect if internal threshold is exceeded.).
Consider Claim 9,
PORTER further teaches wherein the result includes the number of the detected errors for each of the regions (PORTER, e.g., Fig 5, each FP block has its own counter; Col 11:1+, FP block for each region.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Gary W. Cygiel/Primary Examiner, Art Unit 2137
Prosecution Insights