DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it is merely a slightly revised version of claim 1 and does not serve as a concise statement of the technical disclosure of the patent. Correction is required. See MPEP § 608.01(b).
Distinctly different roles are served by the claims and abstract. The claims define the legal scope of protection while the abstract is a concise statement of the technical disclosure. Moreover, the technical disclosure in this case is not coextensive with the claims. Also, it should be recognized that a properly drafted abstract increases the defensive value of Applicant’s asset and better serves the public interest by making the full breadth of the disclosure more readily discernable. In other words, an abstract is also a search tool and having a claim charade as an abstract dulls that tool.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 12 recite “the second resolution at least reaches a requirement of full high definition”. The term “full high definition is a relative term which renders the claim indefinite. The term “full high definition” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Indeed, these terms are subject to change as video image processing science advances; e.g. what was once “high” definition is no longer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Pandya {K. Pandya, D. Varshney, A. Aggarwal and A. Singh Parihar, "An Analytical Study of CNN-based Video Frame Interpolation Techniques," 2020 4th International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2020, pp. 1124-1131, doi: 10.1109/ICICCS48265.2020.9120989} and Ramanujan {US 9600416 B2}.
Claim 1
In regards to claim 1, Pandya discloses an image resolution adjustment method, comprising:
executing a target application to obtain a target image with a first resolution based on a first frame rate {see title, abstract, Introduction, Figs. 2, 4, 6 Section II, Kernel based methods, pgs. 1126-1127 discussing CNN-based video frame interpolation (target application) to convert a low frame rate video, generate slow-motion video using a less expensive video camera that records at a lower frame rate by upscaling (increasing resolution) using VFI (video frame interpolation) using a machine learning CNN model};
processing the target image by an image processing model and the target memory to adjust a resolution of the target image from the first resolution to a second resolution, wherein the second resolution is higher than the first resolution
{see title, abstract, Introduction, Figs. 2, 4, 6 Section II, Kernel based methods, pgs. 1126-1127 discussing CNN-based video frame interpolation (VFI) image processing model};
and controlling a display interface to present the target image with the second resolution based on the first frame rate {see displayed output frames in Fig. 7, Introduction discussing display of slow-motion videos that may be produced by the disclosed VFI image processing model. See also Section IV performance analysis}.
Ramanujan teaches
during an execution of the target application, selecting a target memory from a plurality of buffer memories according to a usage rate of each of the plurality of buffer memories {see Fig. 1 including plural buffers (processor caches 120, cache 107-109); column 1, lines 22-65}
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It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified Pandya which already discloses an image resolution adjustment method (target application) using an image processing model and a memory such that during an execution of the target application, selecting a target memory from a plurality of buffer memories according to a usage rate of each of the plurality of buffer memories as taught by Ramanujan because Ramanujan motivates doing so in cllumn 1, lines 38-43 stating that “cache management protocols may be used to ensure that the most frequently accessed data and instructions are stored within one of the levels of the cache, thereby reducing the number of memory access transactions and improving performance”, because there is a reasonable expectation of success and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Claim 2
In regards to claim 2, Pandya is not relied upon to disclose but Ramanujan teaches wherein during the execution of the target application, the step of selecting the target memory from the plurality of buffer memories according to the usage rate of each of the plurality of buffer memories comprises: comparing the usage rate of each of the plurality of buffer memories during the execution of the target application; and selecting the target memory from the plurality of buffer memories according to a comparison result {see Fig. 1 including plural buffers (processor caches 120, cache 107-109), see column 1, lines 22-65 in which one of the levels of the cache (buffer memory) is selected/used by comparing which has the most frequently accessed data and instructions}.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified Pandya which already discloses an image resolution adjustment method (target application) using an image processing model and a memory such that it includes comparing the usage rate of each of the plurality of buffer memories during the execution of the target application; and selecting the target memory from the plurality of buffer memories according to a comparison result
as taught by Ramanujan because Ramanujan motivates doing so in column 1, lines 38-43 stating that “cache management protocols may be used to ensure that the most frequently accessed data and instructions are stored within one of the levels of the cache, thereby reducing the number of memory access transactions and improving performance”, because there is a reasonable expectation of success and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Claim 3
In regards to claim 3, Pandya is not relied upon to disclose but Ramanujan teaches wherein the target memory is a buffer memory with a highest usage rate in the plurality of buffer memories during the execution of the target application {see Fig. 1 including plural buffers (processor caches 120, cache 107-109), see column 1, lines 22-65}.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified Pandya which already discloses an image resolution adjustment method (target application) using an image processing model and a memory such that during an execution of the target application, selecting a target memory from a plurality of buffer memories according to a usage rate of each of the plurality of buffer memories wherein the target memory is a buffer memory with a highest usage rate in the plurality of buffer memories during the execution of the target application as taught by Ramanujan because Ramanujan motivates doing so in column 1, lines 38-43 stating that “cache management protocols may be used to ensure that the most frequently accessed data and instructions are stored within one of the levels of the cache, thereby reducing the number of memory access transactions and improving performance”, because there is a reasonable expectation of success and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Claim 4
In regards to claim 4, Pandya is not relied upon to disclose but Ramanujan teaches disposing a reserved space in the target memory after selecting the target memory, wherein the reserved space is dedicated to storing data used by the image processing model in a process of processing the target image {see Fig. 1 including plural buffers (processor caches 120, cache 107-109), see column 1, lines 22-65 wherein the selected cache (buffer) is dedicated to storing instructions and data for the most frequently access are stored in that cache to reduce the number of memory access transactions and improve performance}.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified Pandya which already discloses an image resolution adjustment method (target application) using an image processing model and a memory such that it includes disposing a reserved space in the target memory after selecting the target memory, wherein the reserved space is dedicated to storing data used by the image processing model in a process of processing the target image as taught by Ramanujan because Ramanujan motivates doing so in column 1, lines 38-43 stating that “cache management protocols may be used to ensure that the most frequently accessed data and instructions are stored within one of the levels of the cache, thereby reducing the number of memory access transactions and improving performance”, because there is a reasonable expectation of success and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Claim 5
In regards to claim 5, Pandya discloses wherein the step of controlling the display interface to present the target image with the second resolution based on the first frame rate comprises: in a slow motion playing mode, controlling the display interface to present the target image with the second resolution based on the first frame rate {see title, abstract, Introduction, Figs. 2, 4, 6 Section II, Kernel based methods, pgs. 1126-1127 discussing CNN-based video frame interpolation (target application) to convert a low frame rate video, generate slow-motion video using a less expensive video camera that records at a lower frame rate by upscaling (increasing resolution) using VFI (video frame interpolation) using a machine learning CNN model}.
Claims 7-11
The rejection of method claims 1-5 above applies mutatis mutandis to the corresponding limitations of device claim 7-11 while noting that the rejection above cites to both device and method disclosures. Further as to the image capturing interface, processor and display interface see Padya including inputting video from video cameras for resolution and frame rate conversion for output on a display. Ramanujan teaches the plural buffer memories as per Fig. 1 copied above for claim 1.
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Padya and Ramanujan as applied to claims 1 and 7 above, and further in view of Official Notice and/or AAPA (applicant admitted prior art)
Claims 6 and 12
In regards to claims 6 and 12, Pandya discloses wherein the first frame rate reaches at least
Official Notice and/or AAPA (applicant admitted prior art) disclose that image capturing devices/methods are and image processing models are capable of producing the first frame rate of at least 120fps and “full high definition”. Indeed, Applicant’s specification relies upon conventional cameras and image processing models and such techniques and devices are very well known in the art and conventional.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified Pandya which already discloses an image resolution adjustment method (target application) using an image processing model and a memory such that wherein the first frame rate reaches at least 120 frames per second, and the second resolution at least reaches a requirement of full high definition as taught by Office Notice and/or AAPA because doing so is merely routine optimization. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See also MPEP 2144.05(II)(A). Here, at least the general conditions are disclosed because Pandya clearly converts frame rate and resolution using an image processing model, because there is a reasonable expectation of success and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
WO 2021189203 A1 discloses determining a hot spot cache memory buffer based on the highest access frequency.
CN 101388110 A employs highest usage frequency to determine data cache space.
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/MICHAEL ROBERT CAMMARATA/ Primary Examiner, Art Unit 2667