DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 12/12/25, for application number 18/585,225 has been received and entered into record. Claims 1, 2, 10, 11, and 14 have been amended. Therefore, Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9-14, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen et al., US 2022/0244966 A1, in view of Datta et al., US 2004/0221196 A1, and further in view of Rothman et al., US 2008/0148037 A1.
Regarding Claim 1, Nguyen discloses a control method, applied to a first device including a first processor and a second processor [using the system 100 of Fig. 1], comprising:
responding to a boot command for the first device to boot the first processor [the first CPU is configured to receive a master reset signal indicating at boot-up state. In response to the master reset signal indicating the boot-up state, the first CPU is further configured to execute first boot program code to perform a first CPU boot-up operation to set up a sideband communication channel on the sideband communication link, communicate a slave boot-up synchronization signal indicating the boot-up state on the sideband communication channel, and perform a first CPU boot-up task, par 7];
responding to a control signal of the first processor to boot the second processor to execute a plurality of boot tasks corresponding to the first device in parallel, the second processor being configured to execute at least one boot task of the plurality of boot tasks [The second CPU is configured to, in response to the slave boot-up synchronization signal indicating the boot-up state, execute second boot program code to perform a second CPU boot-up operation comprising a second CPU boot-up task partially concurrent with the performance of the first CPU boot-up operation, i.e. slave boot-up signal sent from first CPU, and the tasks are of the same device, so it would correspond to the device while in parallel with the first boot-up operation, par 7];
the at least one boot task including at least one of a peripheral component interconnect (PCI) enumeration task or a network boot task [the APs 220, 230, 240 may perform initialization tasks assigned by BSP 210. For example, the initialization tasks may include testing the memory 130, initializing hardware such as input device(s) 160, output device(s) 170, and/or mass storage device(s) 180, and/or any other tasks to boot the processor system 100, i.e. hardware includes network interface such as a modem or network interface card, par 21, 17], the at least one boot task being executed by the second processor according to a preconfigured correspondence between the second processor and at least one of a PCI bus code segment or a network port of the first device [preconfigured correspondence being the correspondence between the slave CPU and slave CPU socket (which is a socket of the system, i.e. first device)), par 5].
However, Nguyen does not explicitly teach the first processor comprising a bootstrap processor (BSP) core of a central processing unit (CPU); and the second processor comprising an application processor (AP) core of the CPU; and the preconfigured correspondence being stored in a resource table of the first device.
In the analogous art of system boot management, Datta teaches the first processor comprising a bootstrap processor (BSP) core of a central processing unit (CPU); and the second processor comprising an application processor (AP) core of the CPU [during boot time of the multiple-processor system, the BSP dispatches a request to an AP to perform an initialization task such as testing a memory, initializing hardware, and/or other tasks to boot the multiple-processor system, par 3].
It would have been obvious to one of ordinary skill in the art, having the teachings of Nguyen and Datta before him before the effective filing date of the claimed invention, to incorporate the BSP and APs as taught by Datta into the method as disclosed by Nguyen, to allow the APs to perform time consuming tasks and free up the BSP, which results in faster execution time for the overall system [Datta, par 2].
However, the combination of references does not explicitly teach the preconfigured correspondence being stored in a resource table of the first device.
In the analogous art of system booting, Rothman teaches a preconfigured correspondence being stored in a resource table of the first device [i.e. initialization would necessarily be according to the resource table of the first device, as the hardware components detected by the secondary processor are the same components shared by the main CPU; this time-intensive process may be shortened when the secondary processor performs some of this processing 208 to initialize other hardware devices in parallel with the main CPU, Fig. 3; par 52, 53].
It would have been obvious to one of ordinary skill in the art, having the teachings of Nguyen, Datta, and Rothman before him before the effective filing date of the claimed invention, to incorporate the storing of preconfigured configuration settings as taught by Rothman into the method as disclosed by Nguyen and Datta, to ensure the system completes its booting process as quickly as possible [Rothman, par 4].
Regarding Claim 2, Nguyen and Datta disclose the method according to Claim 1. Nguyen further discloses the preconfigured correspondence is used to instruct the first processor to control the second processor to execute the corresponding boot task [the second CPU boot-up operation involves performing one or more CPU boot-up tasks to boot up and initialize the second, slave CPU and/or shared computing resources coupled to the slave CPU socket (the correspondence between the second CPU and the resources coupled to the slave CPU socket); first CPU sends salve boot-up synchronization signal from the first CPU to perform the second boot-up of the second boot-up, which involves components coupled to the slave CPU socket, par 5, 7].
Regarding Claim 3, Nguyen, Datta, and Rothman disclose the method according to Claim 1. Rothman further teaches wherein: the at least one boot task corresponds to a first member of the first device [secondary processor boot task of initializing hardware devices, step 208, Fig. 2; par 52]; the first member is able to connect to another member of the first device [members being hardware components of the device, including southbridge 318, I/O devices 314, audio I/O 324, keyboard/mouse 322, etc., Fig. 3]; and the second processor executing the at least one boot task includes the second processor detecting at least one member attribute of the first member and performing initialization on a member parameter of the first member [secondary processor performs processing at step 208 to initialize other hardware devices in parallel with the main CPU; initializing includes determining the characteristics of the hardware components (i.e. detecting the member attributes and performing initialization on the member parameters by determining the characteristics and subsequently initializing the components), par 52, 53].
Regarding Claim 4, Nguyen, Datta, and Rothman disclose the method according to Claim 3. Rothman further teaches the member attribute includes any one or more of a resource attribute, a bus attribute, and an Option ROM attribute; and the member parameter includes one or more of a resource parameter, a bus parameter, and an Option ROM parameter [members being hardware components of the device, including southbridge 318, I/O devices 314, audio I/O 324, keyboard/mouse 322, etc., which necessarily have bus attributes (i.e. attributes relating to I/O devices connecting to the rest of the system), and necessarily having associated parameters (i.e. values relating to the I/O device connections) Fig. 3].
Regarding Claim 5, Nguyen, Datta, and Rothman disclose the method according to Claim 3. Rothman further teaches wherein the second processor performing the initialization on the member parameter of the first device includes: the second processor performing initialization on the member parameter of the first device according to the resource table of the first device [i.e. initialization would necessarily be according to the resource table of the first device, as the hardware components detected by the secondary processor are the same components shared by the main CPU; this time-intensive process may be shortened when the secondary processor performs some of this processing 208 to initialize other hardware devices in parallel with the main CPU, Fig. 3; par 52, 53].
Regarding Claim 9, Nguyen, Datta, and Rothman disclose the method according to Claim 1. Nguyen further discloses wherein booting the first processor includes: the first processor calling a target service assembly configured in the first device, the target service assembly being configured to trigger the second processor to boot [the first CPU is configured to receive a master reset signal indicating at boot-up state. In response to the master reset signal indicating the boot-up state, the first CPU is further configured to execute first boot program code to perform a first CPU boot-up operation to set up a sideband communication channel on the sideband communication link, communicate a slave boot-up synchronization signal indicating the boot-up state on the sideband communication channel, and perform a first CPU boot-up task; The second CPU is configured to, in response to the slave boot-up synchronization signal indicating the boot-up state, execute second boot program code to perform a second CPU boot-up operation comprising a second CPU boot-up task partially concurrent with the performance of the first CPU boot-up operation; that is, the first CPU communicates a slave boot-up synchronization signal which causes the second CPU to execute the second boot program code to perform a second CPU boot-up operation, par 7].
Regarding Claim 10, Nguyen discloses an electronic device [system 100 of Fig. 1] comprising: a first processor; a second processor; and a memory [CPU 0 106(0), CPU 1 106(1), memory 120(0), 120(1), and 122]. The remainder of Claim 10 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claims 11-14 and 18, Nguyen discloses the device according to Claim 10. Claims 11-14 and 18 repeat the same limitations as recited in Claims 2-5 and 9, respectively, and are rejected accordingly.
Regarding Claim 19, Nguyen, Datta, and Rothman disclose the method according to Claim 2. Datta further teaches wherein the correspondence is preconfigured to map the second processor to a peripheral component interconnect (PCI) bus code segment or a network port of the first device [the APs 220, 230, 240 may perform initialization tasks assigned by BSP 210. For example, the initialization tasks may include testing the memory 130, initializing hardware such as input device(s) 160, output device(s) 170, and/or mass storage device(s) 180, and/or any other tasks to boot the processor system 100, i.e. hardware includes network interface such as a modem or network interface card, par 21, 17].
Claims 6-8 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen, Datta, and Rothman, and further in view of Qiu et al., US 2023/0133490 A1.
Regarding Claim 6, Nguyen, Datta, and Rothman disclose the method according to Claim 1. However, the combination of references does not explicitly teach wherein: the at least one boot task corresponds to a second member configured in the first device; the second member enables the first device to be connected to a second device; the second processor executing the at least one boot task includes the second processor detecting whether the second member is connected to the second device to obtain and send an execution result to the first processor.
In the analogous art of initialization, Qiu teaches wherein: the at least one boot task corresponds to a second member configured in the first device [memory channel 1 being a second member to be initialized during boot process, par 92]; the second member enables the first device to be connected to a second device [second device being memory chips outside of processor 30, Fig. 5]; the second processor executing the at least one boot task includes the second processor detecting whether the second member is connected to the second device to obtain and send an execution result to the first processor [after all testing such as S907 to S909 is passed, the second processor core 321-1 may report configuration information of the memory channel 1 to the first processor core 31 after channel initialization, Fig. 9; par 187].
It would have been obvious to one of ordinary skill in the art, having the teachings of Nguyen, Datta, Rothman, and Qiu before him before the effective filing date of the claimed invention, to incorporate the initialization by the first and second processors as taught by Qiu into the method as disclosed by Nguyen, Datta, and Rothman, to reduce initialization time in providing memory access [Qiu, par 5].
Regarding Claim 7, Nguyen, Datta, Rothman, and Qiu disclose the method according to Claim 6. Qiu further teaches wherein the second processor detecting whether the second member is connected to the second device includes: the second processor collecting a member status of the second member, the member status indicating whether the second member is connected to the second device [after all testing such as S907 to S909 is passed, the second processor core 321-1 may report configuration information of the memory channel 1 to the first processor core 31 after channel initialization (configuration information being the member status), Fig. 9; par 187].
Regarding Claim 8, Nguyen, Datta, Rothman, and Qiu disclose the method according to Claim 6. Qiu further teaches when the execution result indicates that the second member is connected to the second device: in response to the control signal of the first processor, the second processor obtaining and transmitting functional data corresponding to the second device connected to the second member to the first processor, the functional data indicating whether the second device is able to realize a target function [after all testing such as S907 to S909 is passed, the second processor core 321-1 may report configuration information of the memory channel 1 to the first processor core 31 after channel initialization. The configuration information of the memory channel 1 may include information such as an actual available memory capacity of the memory channel 1, Fig. 9; par 187].
Regarding Claims 15-17, Nguyen, Datta, and Rothman disclose the device according to Claim 10. Claims 15-17 repeat the same limitations as recited in Claims 6-8, respectively, and are rejected accordingly.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nguyen, Datta, and Rothman, and further in view of Prasad et al., US 2017/0068549 A1.
Regarding Claim 20, Nguyen, Datta, and Rothman disclose the method according to Claim 9. However, the combination of references does not explicitly teach wherein the target service assembly comprises a unified extensible firmware interface (UEFI) multi-processor service (MPService) assembly.
In the analogous art of boot management, Prasad teaches wherein the target service assembly comprises a unified extensible firmware interface (UEFI) multi-processor service (MPService) assembly [the Multi-Processor (MP) services feature of UEFI may be used to offload processing of option ROM data to a pre-initialized co-processor, such as an AP, par 20].
It would have been obvious to one of ordinary skill in the art, having the teachings of Nguyen, Datta, Rothman, and Prasad before him before the effective filing date of the claimed invention, to incorporate the multi-processor service assembly as taught by Prasad into the method as disclosed by Nguyen, Datta, and Rothman, to reduce user wait time [Prasad, par 4].
Response to Arguments
Applicant's arguments filed 12/12/25 have been fully considered but they are not persuasive.
Applicant appears to simply state the teachings of Nguyen and Datta, without an explanation as to why or how the teachings fail to address the claim limitations. As such, the arguments are merely conclusory statements.
That is, Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Nonetheless, the newly-amended claims have been rejected with newly cited, as well as previously cited, portions of the references previously presented.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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/Paul Yen/Primary Examiner, Art Unit 2175