DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Oath/Declaration
3. The receipt of Oath/Declaration is acknowledged.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/12/2021 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. The drawing(s) filed on 02/23/2024 are accepted by the Examiner.
Status of Claims
6. Claims 1-16 are pending in this application.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claims 1, 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kabune (US 10,424,994 B2) in view of Hellinger et al. (US 7,794,115 B2).
Regarding Claim 1:
Kabune discloses a circuit board (Kabune discloses a circuit board 41 in an ECU/drive device. (Figs. 3 and 9; Col. 8, line 66 – Col. 9, line 9) comprising:
a first surface including a first region in which a first electronic part is mountable (Kabune discloses a heat generation element mount surface 42 of circuit board 41 on which SW elements (drive elements) are mounted, and defines regions (e.g., first region R1); Col. 15, lines 1-7); and
a second surface including a second region in which a second electronic part different from the first electronic part is mountable (Kabune discloses mounting electronic components on a reverse side of the circuit board 41 (e.g., capacitors 86/87; microcomputer 81; ASIC 82) and also defines regions (e.g., second region R2); Col. 15, lines 1-7, Col. 14, lines 41-52),
wherein the first region of the first surface and the second region of the second surface are provided at positions opposed to each other across the circuit board (Kabune explicitly teaches reverse-side components partially overlapping the SW-element regions (e.g., opposed across the board) to efficiently use mounting area; Col. 14, lines 1-8; Col. 14, lines 41-52).
Kabune does not expressly disclose wherein the circuit board has a via for heat dissipation to be shared for heat dissipation of the first electronic part and the second electronic part formed therein to connect the first region and the second region to each other.
Hellinger discloses wherein the circuit board has a via for heat dissipation to be shared for heat dissipation of the first electronic part and the second electronic part formed therein to connect the first region and the second region to each other Hellinger teaches a planar carrier/printed circuit board with components on both opposite sides and thermal vias/thermal through-connections used to transfer heat through the board between opposite surfaces (i.e., a via connecting opposite
side regions for heat dissipation); Col. 1, lines 12-17, Col. 2 lines 51-58; Col. 4, lines 1-7 and 37-44.
Kabune in view of Hellinger are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Hellinger’s thermal-via heat-transfer technique into Kabune’s opposed two-sided mounting arrangement. The suggestion/motivation for doing so is to improve heat dissipation while maintaining compact packaging, especially where opposite-side parts occupy overlapping regions. Therefore, it would have been obvious to combine Kabune with Hellinger to obtain the invention as specified in claim 1.
Regarding Claim 2:
The proposed combination of Kabune in view of Hellinger further discloses the circuit board according to claim 1, wherein the via for heat dissipation is formed in a region in which one of the first electronic part or the second electronic part having a smaller package is to be mounted.
Hellinger teaches mounting relatively large size components (e.g., capacitors 86/87) on a large size component mount surface and other components on the reverse side; the placement of thermal vias within a selected footprint is a routine thermal layout optimization; Kabune: Col. 15, lines 8-16; Hellinger: Col. 4, lines 37-44.
Kabune in view of Hellinger are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose wherein the via for heat dissipation is formed in a region in which one of the first electronic part or the second electronic part having a smaller package is to be mounted. The suggestion/motivation for selecting the via location in the smaller footprint region is to maximize thermal path effectiveness without consuming primary mounting area(s). Therefore, it would have been obvious to combine Kabune with Hellinger to obtain the invention as specified in claim 2.
Regarding Claim 14:
The proposed combination of Kabune in view of Hellinger further discloses the circuit board according to claim 1, wherein the first electronic part has been mounted in the first region, and at least a part of the second region has no part mounted therein (Kabune e.g., Fig. 9 wherein the two capacitors 86 are on surface 43 (top side in Fig. 9) but nothing is on the opposite side 42).
12. Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kabune in view of Hellinger as applied to claim 2 above, and further in view of Hugo et al. (US 10,679,926), hereinafter ‘Hugo’.
Regarding Claim 3:
The proposed combination of Kabune in view of Hellinger discloses the circuit board according to claim 2, but do not expressly disclose wherein the first electronic part and the second electronic part are each a semiconductor device in which an integrated circuit is mounted on a die pad, and wherein the via for heat dissipation is configured to come into contact with the die pad.
Hugo discloses wherein the first electronic part and the second electronic part are each a semiconductor device in which an integrated circuit is mounted on a die pad, and wherein the via for heat dissipation is configured to come into contact with the die pad.
Hugo teaches a bottom-terminated component having a die paddle (i.e., a thermal pad/die pad region) mounted to a PCB having a PCB thermal pad, wherein the PCB thermal pad includes one or more thermal vias (holes or plated apertures), and when the die paddle and PCB thermal pad are in contact, thermal/electrical energy transfer is enabled; Col. 1, lines 32-42. Thus, Hugo evidences the well-known practice of configuring a semiconductor package’s die pad/die paddle to interface with PCB thermal pad region that includes thermal vias.
Kabune, Hellinger & Hugo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, when implementing the through-board thermal-via heat dissipation approach of Hellinger in the opposed/overlapping two-sided mounting configuration of Kabune, to configure the thermal via structure to thermally interface with the semiconductor package thermal interface region (die pad/die paddle) via a PCB thermal pad region as taught by Hugo. The suggestion/motivation for doing so is to improve heat transfer. Therefore, it would have been obvious to combine Kabune, Hellinger & Hugo to obtain the invention as specified in claim 3.
Regarding Claim 4:
The proposed combination of Kabune, Hellinger & Hugo further discloses the circuit board according to claim 3, wherein the first surface has a first wiring pattern provided to come into contact with the die pad of the first electronic part (Hugo teaches the package contacting the PCB at a thermal pad region (functionally a wiring/metal pattern region for the thermal/electrical interface; Col. 2, lines 27-46); ,
wherein the second surface has a second wiring pattern provided to come into contact with the die pad of the second electronic part (Hugo similarly supports the concept of patterned interface regions used for contact/thermal transfer at the package interface; Col. 2, lines 47-59), and wherein the via for heat dissipation is configured to come into contact with the die pad of the first electronic part through intermediation of the first wiring pattern, and come into contact with the die pad of the second electronic part through intermediation of the second wiring pattern (Hugo teaches thermal vias aligned under the thermal pad/openings for heat transfer through the PCB interface structure; Col. 4, lines 4-16).
Kabune, Hellinger & Hugo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to disclose
wherein the first surface has a first wiring pattern provided to come into contact with the die pad of the first electronic part , wherein the second surface has a second wiring pattern provided to come into contact with the die pad of the second electronic part, and wherein the via for heat dissipation is configured to come into contact with the die pad of the first electronic part through intermediation of the first wiring pattern, and come into contact with the die pad of the second electronic part through intermediation of the second wiring pattern. The suggestion/motivation for doing is so liquid solder is not able to wick down the thermal vias and remains where it was originally printed/reflowed, depending on the mounting process used as disclosed by Hugo. Therefore, it would have been obvious to combine Kabune, Hellinger & Hugo to obtain the invention as specified in claim 4.
Regarding Claim 5:
The proposed combination of Kabune, Hellinger & Hugo further discloses the circuit board according to claim 4, wherein the first wiring pattern is formed to come into contact with an entire surface of the die pad of the first electronic part, and wherein the second wiring pattern is formed to come into contact with an entire surface of the die pad of the second electronic part (Hugo supports broad-area thermal contact via the thermal-pad interface arrangement (full/large-area contact as a known thermal design objective; Fig. 5 lines 26-64).
Kabune, Hellinger & Hugo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to disclose
wherein the first wiring pattern is formed to come into contact with an entire surface of the die pad of the first electronic part, and wherein the second wiring pattern is formed to come into contact with an entire surface of the die pad of the second electronic part. The suggestion/motivation for doing is so liquid solder is not able to wick down the thermal vias and remains where it was originally printed/reflowed, depending on the mounting process used as disclosed by Hugo. Therefore, it would have been obvious to combine Kabune, Hellinger & Hugo to obtain the invention as specified in claim 5.
Regarding Claim 6:
The proposed combination of Kabune, Hellinger & Hugo further discloses the circuit board according to claim 5, wherein the circuit board has a multilayer structure (Hellinger teaches PCB internal structure including drilled holes and conductive/filled regions consistent with multilayer PCB manufacture (vias through the substrate)),
wherein the first surface and the second surface are outermost layers of the multilayer structure (Kabune expressly describes a circuit substrate with first side and second side (outer surfaces)), and
wherein the via for heat dissipation passes through the circuit board from the first surface to the second surface (Hellinger teaches thermal vias formed as drilled holes with openings (i.e., through-substrate via structures).
Kabume teaches mounting heat-generating components on one surface of a circuit substrate and mounting other components on the opposite surface of a circuit substrate in an opposed/overlapping arrangement, which inherently raises thermal constraints in a compact footprint. Hellinger teaches implementing heat dissipation using thermal vias formed as holes/openings through the carrier part (board) (e.g., drilled holes/openings used as thermal vias), i.e., a through-substrate conduction surface.
Kabune, Hellinger & Hugo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the thermal-via heat dissipation technique of Hellinger in the opposed two-sided configuration of Kabune using a through-board via extending from the first surface to the second surface (and, as recited, where those surfaces are the outermost layers of a multilayer board), and configuring them to traverse the multilayer stack from the first surface to the second surface. The suggestion/motivation for doing is to provide a direct low-thermal resistance conduction path in the overlap footprint, to improve heat dissipation. Therefore, it would have been obvious to combine Kabune, Hellinger & Hugo to obtain the invention as specified in claim 6.
13. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kabune, Hellinger & Hugo as applied to claim 6 above, and further in view of Marvin et al. (US 2018/0048255), hereinafter ‘Marvin’.
Regarding Claim 7:
The proposed combination of Kabune, Hellinger & Hugo further disclose the circuit board according to claim 6, wherein, on the first surface, a first semiconductor device of a motor driver configured to drive a motor is mountable as the first electronic part, and wherein, on the second surface,
Kabune is directed to a motor drive device and teaches mounting semiconductor switching elements on a first side heat-generation element mount surface, with components also mounted on the opposite side in an overlapped/opposed arrangement to achieve compact packaging. Hellinger teaches implementing through board thermal-via structures to conduct heat through a carrier/board.
Kabune, Hellinger & Hugo do not disclose a second semiconductor device of a motor driver configured to drive the motor is mountable as the second electronic part.
Marvin discloses a second semiconductor device of a motor driver configured to drive the motor is mountable as the second electronic part.
Marvin teaches that a half-bridge switching circuit system can be implemented in a motor driver system to control a motor (including variable speed control). Marvin further teaches implementing such switching circuitry on a double-sided multilayer PCB with components soldered on both sides, including a MOSFET switch mounted to one surface and a complementary MOSFET switch mounted to the other surface, optionally at an approximately same location on opposite sides (directly opposing each other). Kabune, Hellinger, Hugo and Marvin are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the well-known practice of mounting motor-driver semiconductor switching devices on opposite surfaces of a PCB. Therefore, it would have been obvious to combine Kabune, Hellinger & Marvin to obtain the invention as specified in claim 7.
14. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kabune (US 10,424,994 B2) in view of Hellinger et al. (US 7,794,115 B2), and further in view of Zhang et al. (US 2014/0268614), hereinafter ‘Zhang’.
Regarding Claim 8:
Kabune discloses a circuit board (Kabune discloses a circuit board 41 in an ECU/drive device. (Figs. 3 and 9; Col. 8, line 66 – Col. 9, line 9) comprising:
a first surface including a first region in which a first electronic part is mountable (Kabune discloses a heat generation element mount surface 42 as a mounting region on a first surface (Col. 9, lines 14-27; Figs. 8 and 10), and defines regions (e.g., first region R1); Col. 15, lines 1-7); a second surface including a second region in which a second electronic part different from the first electronic part is mountable (Kabune discloses mounting electronic components on a reverse side of the circuit board 41 (e.g., capacitors 86/87; microcomputer 81; ASIC 82) and also defines regions (e.g., second region R2); Col. 15, lines 1-7, Col. 14, lines 41-52);
wherein, as viewed in a direction perpendicular to the first surface, a first part of the first region including an outer edge of the first region, overlaps with the second region, and a second part of the first region is outside of the second region (Kabune teaches large-size component mount surface 43 as a mounting region on a second surface for different parts reverse-side components partially overlapping regions R1/R2 on the opposite side, which necessarily implies overlapping and non-overlapping parts as viewed perpendicular to the board; Col. 15, lines 1-8; Col. 14, lines 41-52),
wherein, as viewed in the direction, a first part of the second region including an outer edge of the second region overlaps with the first region, and a second part of the second region is outside of the first region (Kabune teaches partial overlap across sides/regions; Col. 15, lines 1-9; Figs. 7 and 11 Col. 18, lines 54-60; Col. 11, lines 12-25).
Kabune does not disclose a via connecting the first region and the second region.
Hellinger discloses a via connecting the first region and the second region.
Hellinger teaches a planar carrier/printed circuit board with components on both opposite sides and thermal vias/thermal through-connections used to transfer heat through the board between opposite surfaces (i.e., a via connecting opposite
side regions for heat dissipation); Col. 1, lines 12-17, Col. 2 lines 51-58; Col. 4, lines 1-7 and 37-44.
Kabune in view of Hellinger are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Hellinger’s thermal-via heat-transfer technique into Kabune’s opposed two-sided mounting arrangement. The suggestion/motivation for doing so is to improve heat dissipation while maintaining compact packaging, especially where opposite-side parts occupy overlapping regions. Therefore, it would have been obvious to combine Kabune with Hellinger to obtain the invention as specified.
Kabune in view of Hellinger do not expressly disclose wherein the via is formed in an overlapping region in which the first region and the second region overlap.
Zhang discloses wherein the via is formed in an overlapping region in which the first region and the second region overlap.
Zhang teaches via/vertical transition located in an overlapped area at ¶[0031], and metal-filled via/via structure at ¶[0022], together supporting forming a via/transition in the overlap footprint. Specifically, Zhang teaches an upper feature/area (pad/region) that overlaps a lower feature/area when viewed normal to the board, and also discusses forming the via relative to the overlap condition. Zhang also describes the lower pad/region relative to the upper pad/region (including overlap and non-overlap portions) when viewed perpendicular. Zhang further teaches a through-hole (filled/plated) formed in a position where the upper pad overlaps the lower pad (“overlap region”); (Abstract; [0020], [0022], [0031]).
Kabune, Hellinger & Zhang are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to
apply Zhang’s placement rule for vias in overlap regions to the double-sided mounting arrangement of Kabune/Hellinger. The suggestion/motivation for doing so is to conserve area and promote thermal/electrical performance. Therefore, it would have been obvious to combine Kabune, Hellinger & Zhang to obtain the invention as specified in claim 8.
Regarding Claim 9:
The proposed combination of Kabune, Hellinger & Zhang further discloses the circuit board according to claim 8, wherein a first through via that passes through the circuit board is formed in the second part of the first region, which is outside of the second region as viewed in the direction, and wherein a second through via that passes through the circuit board is formed in a part of the second region, which is outside of the first region as viewed in the direction.
Hellinger discloses through via structure, drilled holes/solder-filled thermal via (Col. 4, lines 35-48) and Kabune teaches the existence of non-overlap portion (outside region) from partial overlap (Col. 15, lines 1-9; Figs. 7 and 11).
Kabune, Hellinger & Zhang are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional through vias in non-overlapping portions. The suggestion/motivation for doing so is to balance thermal conduction and layout/routing freedom by using a routine PCB optimization. Therefore, it would have been obvious to combine Kabune, Hellinger & Zhang to obtain the invention as specified in Claim 9.
15. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kabune, Hellinger & Zhang as applied to claim 9 above, and further in view of Yoo et al. (US 2021/0267043), hereinafter ‘Yoo’.
Regarding Claim 10:
The proposed combination of Kabune, Hellinger & Zhang further discloses the circuit board according to claim 9, wherein the first surface has a first wiring pattern provided to come into contact with a heat dissipation plate of the first electronic part, (Hellinger teaches semiconductor components on a carrier/PCB and emphasizes efficient heat conduction from the component to thermal structures/heat sinks),
wherein the second surface has a second wiring pattern provided to come into contact with a heat dissipation plate of the second electronic part (Hellinger teaches semiconductor components arranged on each of two sides, each thermally coupled to corresponding heat transfer structures), wherein the via for heat dissipation, the first through via, and the second through via are formed (Zhang teaches forming the through hole in an area defined by pad overlap/non-overlap relationships (placement control relative to conductive features), and wherein the via for heat dissipation, the first through via, and the second through via are formed (Zhang teaches again, that via placement depends on overlap/non-overlap relative to the opposite-side pad/feature).
Kabune, Hellinger & Zhang do not expressly disclose vias formed outside of the wiring pattern.
Yoo discloses vias formed outside of the wiring pattern.
Yoo teaches a pad/pattern interface used for component contact, and teaches the via upper surface is spaced away from a pad edge region, evidencing a keep-out relationship between vias and the pad/pattern area used for contact (Yoo [0188]).
Kabune, Hellinger, Zhang & Yoo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose vias formed outside of the wiring pattern. The suggestion/motivation for doing so is to reduce the risk of shorting, soler-bridging, or thermal mechanical interference while still gaining the thermal benefits of vias for reliability of manufacturing. Therefore, it would have been obvious to combine Kabune, Hellinger, Zhang & Yoo to obtain the invention as specified in Claim 10.
16. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kabune in view of Hellinger as applied to claim 1 above, and further in view of Yoo et al. (US 2021/0267043), hereinafter ‘Yoo’.
Regarding Claim 11:
The proposed combination of Kabune in view of Hellinger further discloses the circuit board according to claim 1,
wherein the circuit board includes an overlapping region in which, as viewed in a direction perpendicular to the first surface, the first region and the second region overlap with each other (Kabune teaches establishing the overlapping region (Col. 15, lines 1-9; Figs. 7 and 11 (“partially overlapping”)), and
wherein the via for heat dissipation includes a first through via (Hellinger teaches that the transfer of heat through the printed circuit board can be embodied advantageously as thermal through-connections, so called "thermal vias". These "thermal vias" consist of solder-filled drilled holes and are handled in the manufacturing process of a printed circuit board largely like electrical through-connections. (Col. 2, lines 51-60, Col. 4, lines 35-48)), and
a second through via (Hellinger further teaches multiple thermal vias in the process of a printed circuit board. See Fig. 6 ‘thermal vias 16’).
Kabune in view of Hellinger do not expressly disclose a first through via arranged in the overlapping region, and a second through via having an opening area different from an opening area of the first through via.
Yoo discloses a first through via arranged in the overlapping region, and a second through via having an opening area different from an opening area of the first through via.
Yoo teaches “vertically overlapping” wherein heat dissipating parts (vias) are disposed in a region vertically overlapping the pad(s). See Fig. 3 vias V1, V2 and V3 which correspond to the claimed plurality of through vias. Yoo further teaches that the horizontal width W1 and W2 of the vias differ which reads on the claimed ‘different opening areas’ (¶[0229].
Kabune, Hellinger & Yoo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose multiple vias with differing opening areas/widths in different regions of the board. The suggestion/motivation for doing so is to balance thermal conduction, current capacity, and manufacturing of circuit boards and its components.
Therefore, it would have been obvious to combine Kabune, Hellinger & Yoo to obtain the invention as specified in Claim 11.
Regarding Claim 12:
The proposed combination of Kabune, Hellinger & Yoo further discloses the circuit board according to claim 11,
wherein an area of the first region is smaller than an area of the second region (Kabune discloses differentiating the heat generation element mount surface 42 from the large-size component mount surface 43, supporting different region footprints/areas; Col. 9, lines 14-27; Figs. 8 and 10), and wherein the first through via is formed in a region in which the first region and the second region overlap each other as viewed from the direction (Yoo: ‘vertically overlapping’ ¶[0025-0027]), and has an opening area smaller than the opening area of the second through via (Yoo teaches wherein the horizontal width W1 and W2 of the vias differ which reads on the claimed ‘area of the first region is smaller than area of the second region’ ¶[0229].
Kabune, Hellinger & Yoo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose multiple vias with differing opening areas/widths in different regions of the board. The suggestion/motivation for doing so is to balance thermal conduction, current capacity, and manufacturing of circuit boards and its components.
Therefore, it would have been obvious to combine Kabune, Hellinger & Yoo to obtain the invention as specified in Claim 12.
Regarding Claim 13:
The proposed combination of Kabune, Hellinger & Yoo further discloses the circuit board according to claim 12, wherein the second through via is formed in, in the second region, a region in which the first region and the second region do not overlap each other as viewed from the direction.
Yoo teaches wherein a heat dissipating part disposed through the substrate in a region does not vertically overlap the pad (¶[0027]).
Kabune, Hellinger & Yoo are combinable because they are from the same field of endeavor of image processing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose wherein the second through via is formed in, in the second region, a region in which the first region and the second region do not overlap each other as viewed from the direction. The suggestion/motivation for doing so is to satisfy clearance/routing/keep-out constraints while maintaining thermal performance. Therefore, it would have been obvious to combine Kabune, Hellinger & Yoo to obtain the invention as specified in Claim 13.
17. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kabune (US 10,424,994 B2) in view of Takahashi (US 2013/0135421), and further in view of Hellinger et al. (US 7,794,115 B2).
Regarding Claim 15:
Kabune discloses an
a circuit board (Kabune discloses a circuit board 41 in an ECU/drive device. (Figs. 3 and 9; Col. 8, line 66 – Col. 9, line 9) including:
a first surface including a first region in which a first electronic part is mountable (Kabune discloses a heat generation element mount surface 42 of circuit board 41 on which SW elements (drive elements) are mounted, and defines regions (e.g., first region R1); Col. 15, lines 1-7); and
a second surface including a second region in which a second electronic part different from the first electronic part is mountable Kabune discloses mounting electronic components on a reverse side of the circuit board 41 (e.g., capacitors 86/87; microcomputer 81; ASIC 82) and also defines regions (e.g., second region R2); Col. 15, lines 1-7, Col. 14, lines 41-52); and
wherein the circuit board is configured such that:
the first region of the first surface and the second region of the second surface are provided at positions opposed to each other across the circuit board (Kabune explicitly teaches reverse-side components partially overlapping the SW-element regions (e.g., opposed across the board) to efficiently use mounting area; Col. 14, lines 1-8; Col. 14, lines 41-52); and
Kabune does not expressly disclose a constituent part to be controlled by any of the first electronic part or the second electronic part mounted on the circuit board to form an image.
Takahashi discloses a constituent part to be controlled by any of the first electronic part or the second electronic part mounted on the circuit board to form an image. (Takahashi discloses ‘image forming apparatus 1’ in Figs. 1 and 2. Figure 2 shows the internal configuration of the image forming apparatus describing devices/units housed in the apparatus for image forming and operation. Takahashi discloses a ‘drive circuit board’ ¶[0003-0004] for performing various processing.
Kabune in view of Takahashi are combinable they both disclose board-mounted electronic arrangements. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Kabune’s two sided board mounting arrangement within an image forming apparatus as taught by Takahashi. The suggestion/motivation for doing so is to improve heat dissipation and compact packaging of an image forming apparatus. Therefore, it would have been obvious to combine Kabune with Takahashi to obtain the invention as specified.
The proposed combination of Kabune in view of Takahashi do not expressly disclose a via for heat dissipation to be shared for heat dissipation of the first electronic part and the second electronic part is formed to connect the first region and the second region to each other.
Hellinger discloses a via for heat dissipation to be shared for heat dissipation of the first electronic part and the second electronic part is formed to connect the first region and the second region to each other.
Hellinger teaches a planar carrier/printed circuit board with components on both opposite sides and thermal vias/thermal through-connections used to transfer heat through the board between opposite surfaces (i.e., a via connecting opposite
side regions for heat dissipation); Col. 1, lines 12-17, Col. 2 lines 51-58; Col. 4, lines 1-7 and 37-44.
Kabune, Takahashi & Hellinger are combinable because they all disclose improving board-mounted electronics. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Hellinger’s thermal-via heat-transfer technique into Kabune’s opposed two-sided mounting arrangement within an image forming apparatus environment as taught by Takahashi. The suggestion/motivation for doing so is to improve heat dissipation while maintaining compact packaging in imaging equipment. Therefore, it would have been obvious to combine Kabune, Takahashi & Hellinger to obtain the invention as specified in claim 15.
18. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kabune, Takahashi and Hellinger as applied to claim 15 above and further in view of Marvin et al. (US 2018/0048255).
Regarding Claim 16:
The proposed combination of Kabune, Takahashi and Hellinger further discloses the image forming apparatus according to claim 15, wherein the constituent part is a motor (Takahashi: ‘polygon motor unit includes a motor portion’ ¶[0033] and polygon motor 71 is mounted on the board ¶[0046]), and wherein the circuit board is configured such that;
on the first surface, a first semiconductor device of a motor driver configured to drive the motor is mountable as the first electronic part (Kabune discloses a first surface mount region (Col. 9, lines 14-27; Figs. 8 and 10); and
on the second surface, a second semiconductor device (Kabune discloses a second surface mount region (Col. 9, lines 14-27; Figs. 8 and 10).
Kabune is directed to a motor drive device and teaches mounting semiconductor switching elements on a first side heat-generation element mount surface, with components also mounted on the opposite side in an overlapped/opposed arrangement to achieve compact packaging.
Kabune, Takahashi and Hellinger do not disclose a second semiconductor device of a motor driver configured to drive the motor is mountable as the second electronic part.
Marvin discloses a second semiconductor device of a motor driver configured to drive the motor is mountable as the second electronic part.
Marvin teaches that a half-bridge switching circuit system can be implemented in a motor driver system to control a motor (including variable speed control). Marvin further teaches implementing such switching circuitry on a double-sided multilayer PCB with components soldered on both sides, including a MOSFET switch mounted to one surface and a complementary MOSFET switch mounted to the other surface, optionally at an approximately same location on opposite sides (directly opposing each other). Kabune, Takahashi, Hellinger and Marvin are combinable because they all disclose board-mounted electronic arrangements. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the well-known practice of mounting motor-driver semiconductor switching devices on opposite surfaces of a PCB. Therefore, it would have been obvious to combine Kabune, Takahashi, Hellinger and Marvin to obtain the invention as specified in claim 16.
Conclusion
19. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
McKnight-MacNeil et al. (US 9,824,949) discloses packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.
20. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R MCLEAN whose telephone number is (571)270-1679. The examiner can normally be reached Monday-Thursday, 6AM - 4PM, PST.
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/NEIL R MCLEAN/Primary Examiner, Art Unit 2681